Including Multiple Vertical Junction Or V-groove Junction Solar Cells Formed In A Semiconductor Substrate (epo) Patents (Class 257/E27.126)
  • Patent number: 8993366
    Abstract: The method of the invention includes the sequential steps of providing a plurality of solar cells, interconnecting the solar cells using one or more interconnect tabs, attaching the interconnect tabs to a top side of the solar cell to interconnect the plurality of solar cells by coupling an exposed top surface of a first solar cell to a top surface of an adjacent second solar cell, attaching one or more bypass diodes to a top side of the solar cell, then next applying an adhesive to a first film layer, placing the plurality of solar cells onto the first film layer, then next applying an adhesive to a second film layer, placing the plurality of solar cells and first film layer onto the second film layer to form a sheet assembly, and then forming the solar sheet from the sheet assembly.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: March 31, 2015
    Assignee: MicroLink Devices, Inc.
    Inventors: Raymond Chan, Haruki Miyamoto
  • Patent number: 8945978
    Abstract: A metal contact of a solar cell is formed by electroplating copper using an electroplating seed that is formed on a dielectric layer. The electroplating seed includes an aluminum layer that connects to a diffusion region of the solar cell through a contact hole in the dielectric layer. A nickel layer is formed on the aluminum layer, with the nickel layer-aluminum layer stack forming the electroplating seed. The copper is electroplated in a copper plating bath that has methanesulfonic acid instead of sulfuric acid as the supporting electrolyte.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: February 3, 2015
    Assignee: SunPower Corporation
    Inventor: Joseph Frederick Behnke
  • Patent number: 8883548
    Abstract: Electronic device quality Aluminum Antimonide (AlSb)-based single crystals produced by controlled atmospheric annealing are utilized in various configurations for solar cell applications. Like that of a GaAs-based solar cell devices, the AlSb-based solar cell devices as disclosed herein provides direct conversion of solar energy to electrical power.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: November 11, 2014
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: John W. Sherohman, Jick Hong Yee, Arthur W. Combs, III
  • Patent number: 8835980
    Abstract: Provided is a semiconductor wafer including: a base wafer containing silicon; an inhibitor that has been formed on the base wafer, has an aperture in which a surface of the base wafer is exposed, and inhibits crystal growth; and a light-absorptive structure that has been formed inside the aperture in contact with a surface of the base wafer exposed inside the aperture, where the light-absorptive structure includes a first semiconductor and a second semiconductor.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: September 16, 2014
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Masahiko Hata, Taro Itatani
  • Patent number: 8513104
    Abstract: A method of forming a floating junction on a substrate is disclosed. The method includes providing the substrate doped with boron atoms, the substrate comprising a front surface and a rear surface. The method also includes depositing a set of masking particles on the rear surface in a set of patterns; and heating the substrate in a baking ambient to a first temperature and for a first time period in order to create a particle masking layer. The method further includes exposing the substrate to a phosphorous deposition ambient at a second temperature and for a second time period, wherein a front surface PSG layer, a front surface phosphorous diffusion, a rear surface PSG layer, and a rear surface phosphorous diffusion are formed, and wherein a first phosphorous dopant surface concentration in the substrate proximate to the set of patterns is less than a second dopant surface concentration in the substrate not proximate to the set of patterns.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: August 20, 2013
    Assignee: Innovalight, Inc.
    Inventors: Malcolm Abbott, Maxim Kelman, Eric Rosenfeld, Elena Rogojina, Giuseppe Scardera
  • Patent number: 8466003
    Abstract: Embodiments of the current invention describe methods of forming different types of crystalline silicon based solar cells that can be combinatorially varied and evaluated. Examples of these different types of solar cells include front and back contact silicon based solar cells, all-back contact solar cells and selective emitter solar cells. These methodologies all incorporate the formation of site-isolated regions using a combinatorial processing tool and the use of these site-isolated regions to form the solar cell area. Therefore, multiple solar cells may be rapidly formed on a single crystalline silicon substrate for use in combinatorial methodologies. Any of the individual processes of the methods described may be varied combinatorially to test varied process conditions or materials.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: June 18, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Jian Li, James Craig Hunter, Nikhil Kalyankar, Nitin Kumar, Minh Anh Anh Nguyen
  • Patent number: 8440489
    Abstract: A method of manufacturing a solar cell includes providing a semiconductor substrate; disposing a reflection layer on one side of the semiconductor substrate, wherein the disposing the reflection layer comprises implanting gas into a surface of the one side of the semiconductor substrate and heating the gas; disposing an n+ region and a p+ region separated from each other on the other opposite facing side of the semiconductor substrate; disposing a first electrode connected to the n+ region; and disposing a second electrode connected to the p+ region.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: May 14, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Kyun Kim, Yun-Gi Kim, Jin-Wook Lee, Hwa-Young Ko
  • Patent number: 8426236
    Abstract: A grid stack structure of a solar cell, which includes a silicon substrate, wherein a front side of the silicon is doped with phosphorus to form a n-emitter and a back side of the silicon is screen printed with aluminum (Al) metallization; a dielectric layer, which acts as an antireflection coating (ARC), applied on the silicon; a mask layer applied on the front side to define a grid opening of the dielectric layer, wherein an etching method is applied to open an unmasked grid area; a light-induced plated nickel or cobalt layer applied to the front side with electrical contact to the back side Al metallization; a silicide layer formed by rapid thermal annealing of the plated nickel (Ni) or cobalt (Co); an optional barrier layer electrodeposited on the silicide; a copper (Cu) layer electrodeposited on the silicide/barrier film layer; and a thin protective layer is chemically applied or electrodeposited on top of the Cu layer.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: April 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Harold J. Hovel, Xiaoyan Shao
  • Patent number: 8410563
    Abstract: Electrical energy generation apparatuses, in which a solar battery device and a piezoelectric device are combined in a single body by using a plurality of nano wires formed of a semiconductor material having piezoelectric properties.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: April 2, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-jun Park, Seung-nam Cha
  • Patent number: 8383929
    Abstract: Under one aspect, a nonplanar photovoltaic module having a length includes: (a) an elongated nonplanar substrate; and (b) a plurality of solar cells disposed on the elongated nonplanar substrate, wherein each solar cell in the plurality of solar cells is defined by (i) a plurality of grooves around the nonplanar photovoltaic module and (ii) a groove along the length of the photovoltaic module. In some embodiments, each groove of the plurality of grooves about the photovoltaic module, independently, has a repeating pattern, a non-repeating pattern, or is helical. In some embodiments, the module further includes a patterned conductor providing serial electrical communication between adjacent solar cells. In some embodiments, portions of the patterned conductor providing serial electrical communication between adjacent solar cells are within a groove of the plurality of grooves about the photovoltaic module.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: February 26, 2013
    Assignee: Solyndra LLC
    Inventors: Erel Milshtein, Benyamin Buller
  • Patent number: 8318528
    Abstract: Implementations and techniques for solar arrays of transparent nanoantennas are generally disclosed.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: November 27, 2012
    Assignee: Empire Technology Development LLC
    Inventor: Ezekiel Kruglick
  • Patent number: 8283739
    Abstract: Electrical energy generation apparatuses, in which a solar battery device and a piezoelectric device are combined in a single body by using a plurality of nano wires formed of a semiconductor material having piezoelectric properties.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: October 9, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-jun Park, Seung-nam Cha
  • Patent number: 8241945
    Abstract: Solar cells and methods for fabrication thereof are provided. A method may include forming a via through at least one dielectric layer formed on a semiconductor wafer by using a laser to ablate a region of the at least one dielectric layer such that at least a portion of the surface of the semiconductor wafer is exposed by the via. The method may further include applying a self-doping metal paste to the via. The method may additionally include heating the semiconductor wafer and self-doping metal paste to a temperature sufficient to drive at least some dopant from the self-doping metal paste into the portion of the surface of the semiconductor wafer exposed by the via to form a selective emitter region and a contact overlying and self-aligned to the selective emitter region.
    Type: Grant
    Filed: February 8, 2010
    Date of Patent: August 14, 2012
    Assignee: Suniva, Inc.
    Inventors: Adam M. Payne, Daniel L. Meier, Vinodh Chandrasekaran
  • Patent number: 8187907
    Abstract: A method of manufacturing a solar cell by providing a first substrate; depositing on the first substrate a sequence of layers of semiconductor material forming a solar cell including a top subcell and a bottom subcell; forming a metal back contact over the bottom subcell; forming a group of discrete, spaced-apart first bonding elements over the surface of the back metal contact; attaching a surrogate substrate on top of the back metal contact using the bonding elements; and removing the first substrate to expose the surface of the top subcell.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: May 29, 2012
    Assignee: Emcore Solar Power, Inc.
    Inventor: Fred Newman
  • Patent number: 8148796
    Abstract: Disclosed are a solar cell and a manufacturing method thereof. The solar cell in accordance with an embodiment of the present invention includes: a substrate having a plurality of holes formed on one surface thereof; a metal layer formed on an inner wall of the hole and on one surface of the substrate; a p-type semiconductor coated on the metal layer; an n-type semiconductor formed inside the hole and on one surface of the substrate; a transparent conductive oxide formed on the n-type semiconductor; and an electrode terminal formed on the p-type semiconductor and on the transparent conductive oxide.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: April 3, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Ro-Woon Lee, Jae-Woo Joung, Shang-Hoon Seo, Tae-Gu Kim
  • Patent number: 8129822
    Abstract: A template 100 for three-dimensional thin-film solar cell substrate formation for use in three-dimensional thin-film solar cells. The template 100 comprises a substrate which comprises a plurality of posts 102 and a plurality of trenches 104 between said plurality of posts 102. The template 100 forms an environment for three-dimensional thin-film solar cell substrate formation.
    Type: Grant
    Filed: October 6, 2007
    Date of Patent: March 6, 2012
    Assignee: Solexel, Inc.
    Inventor: Mehrdad Moslehi
  • Patent number: 8053343
    Abstract: A method for forming a selective emitter of a solar cell and a diffusion apparatus for forming the same are provided. The method includes texturing a surface of a silicon substrate by etching the silicon substrate, coating an impurity solution on the surface of the silicon substrate, injecting a first thermal energy into the whole surface of the silicon substrate, and, while the first thermal energy is injected into the whole surface of the silicon substrate, injecting a second thermal energy by irradiating a laser beam into a partial region of the surface of the silicon substrate.
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: November 8, 2011
    Assignee: SNT. Co., Ltd.
    Inventors: Yusung Huh, Seungil Park, Mangeun Lee
  • Patent number: 7932184
    Abstract: A method of manufacturing a solar cell module, including: forming a laminated body including a first protective member, a first sealing member having a first melting point, a plurality of solar cells, a second sealing member having a second melting point higher than the first melting point, and the second protective member; heating the first sealing member to a temperature equal to or higher than the first melting point but lower than the second melting point; and heating the second sealing member to a temperature equal to or higher than the second melting point. In forming the laminated body, the second sealing member is arranged to form a surface including a plurality of convex portions faces the first sealing member.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: April 26, 2011
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Yousuke Ishii
  • Patent number: 7888160
    Abstract: A process of manufacturing a solar cell is disclosed. The process comprises steps of (a) providing a semiconductor substrate, (b) forming a dielectric layer with amorphous silicon structure on the semiconductor substrate, (c) partially removing the dielectric layer with amorphous silicon structure to expose parts of the semiconductor substrate, (d) simultaneously forming a heavily doped region on a surface of the exposed semiconductor substrate and a lightly doped region on a surface of the unexposed semiconductor substrate using the dielectric layer with amorphous silicon structure as a translucent barrier layer, (e) removing the dielectric layer with amorphous silicon structure, (f) forming an anti-reflection coating on the semiconductor substrate, and (g) forming a first electrode on the anti-reflection coating and coupled with the heavily doped region.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: February 15, 2011
    Assignee: Mosel Vitelic Inc.
    Inventors: Chang Hong Shen, Pei Ting Lo
  • Publication number: 20100243030
    Abstract: A substrate of the invention has a positioning marker formed with a light absorbing agent that selectively absorbs light of a specific wavelength region or with a light reflecting agent that selectively reflects light of a specific wavelength region. Preferably, the light of a specific wavelength range is near infrared light, infrared light, near ultraviolet light, or ultraviolet light. Preferably, the positioning marker is formed on a rear surface of the substrate.
    Type: Application
    Filed: March 29, 2010
    Publication date: September 30, 2010
    Applicant: FUJIFILM CORPORATION
    Inventor: Haruo YAGO
  • Patent number: 7595543
    Abstract: The invention provides a method for increasing the usable surface area of a semiconductor wafer having a substantially planar surface and a thickness dimension at right angles to said substantially planar surface, the method including the steps of selecting a strip thickness for division of the wafer into a plurality of strips, selecting a technique for cutting the wafer into the strips at an angle to the substantially planar surface, in which the combined strip thickness and width of wafer removed by the cutting is less than the thickness of the wafer, cutting the wafer into strips using the selected technique and separating the strips from each other.
    Type: Grant
    Filed: July 29, 2005
    Date of Patent: September 29, 2009
    Assignee: Australian National University
    Inventors: Klaus Johannes Weber, Andrew William Blakers
  • Publication number: 20090130794
    Abstract: Thermal evaporation apparatus for depositing of a material on a substrate, comprising material storage means; heating means to generate a vapour of the material in the material storage means; vapour outlet means comprising a vapour receiving pipe having vapour outlet passages, and emission reducing means arranged such that an external surface of the vapour outlet means directed to said substrate exhibits low emission, and wherein the apparatus further comprises pipe heating means in the interior of said vapour outlet means, wherein at least the surfaces of the material storage means, heating means, and emission reducing means and pipe heating means arranged to come into contact with the material vapour are of a corrosion-resistant material.
    Type: Application
    Filed: April 20, 2007
    Publication date: May 21, 2009
    Inventors: Volker Probst, Walter Stetter