Semiconductors Devices Adapted For Rectifying, Amplifying, Oscillating, Or Switching, Capacitors, Or Resistors With At Least One Potential-jump Barrier Or Surface Barrier (epo) Patents (Class 257/E29.001)

  • Patent number: 10230913
    Abstract: A transmitter according to the disclosure includes a driver, a first pre-driver, a second pre-driver, and a power-supply-voltage generator. The driver includes a first transistor and a second transistor. The first transistor has a drain supplied with a first power supply voltage, a source led to an output terminal, and a gate. The second transistor has a drain led to the output terminal, a grounded source, and a gate. The first pre-driver is supplied with a second power supply voltage and drives the gate of the first transistor. The second power supply voltage has a positive correlation with the first power supply voltage. The second pre-driver is supplied with a third power supply voltage and drives the gate of the second transistor. The power-supply-voltage generator generates the first power supply voltage, the second power supply voltage, and the third power supply voltage.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: March 12, 2019
    Assignee: SONY CORPORATION
    Inventor: Riichi Nishino
  • Patent number: 9041147
    Abstract: According to a semiconductor substrate (40), a space (A) between a plurality of Si thin film (16), which are provide apart from one another on the insulating substrate (30), is (I) larger than a difference between elongation of part of the insulating substrate which part corresponds to the space (A) and elongation of each of Si wafers (10) when a change is made from room temperature to 600° C. and (II) smaller than 5 mm. This causes an increase in a region of each of a plurality of semiconductor thin films which region has a uniform thickness, and therefore prevents transferred semiconductor layers and the insulating substrate from being fractured or chipped.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: May 26, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Masahiro Mitani
  • Patent number: 9029978
    Abstract: A semiconductor structure includes a semiconductor substrate with a substrate region and a trench extending into the surface region of the semiconductor substrate. The trench includes sidewalls, a bottom and a depth. The semiconductor structure further includes a trench liner overlying the bottom and the sidewalls of the trench. The semiconductor structure also includes a shallow trench isolation structure filling at least the depth of the trench. The shallow trench isolation structure is formed from alternating layers of silicon nitride and high-density plasma oxide.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: May 12, 2015
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Ting Cheong Ang
  • Patent number: 9018046
    Abstract: An area efficient distributed device for integrated voltage regulators comprising at least one filler cell coupled between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size portion of said device is coupled to said I/O rails for distributing portions of said device on the periphery of said chip. The device is coupled as small size portion on the lower portion of said second filler cell for distributing said device on the periphery of said chip and providing maximal area utilization.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 28, 2015
    Assignees: STMicroelectronics International N.V., STMicroelectronics S.r.l.
    Inventors: Joshipura Jwalant, Nitin Bansal, Amit Katyal, Massimiliano Picca
  • Patent number: 9000536
    Abstract: The present disclosure relates a Fin field effect transistor (FinFET) device having large effective oxide thickness that mitigates hot carrier injection, and an associated method of formation. In some embodiments, the FinFET device has a conductive channel of a first fin protruding from a planar substrate. The conductive channel has a non-conductive highly doped region located along multiple outer edges of the channel region. A gate region protrudes from the planar substrate as a second fin that overlies the first fin. A gate dielectric region is located between the non-conductive highly doped region and the gate region. The non-conductive highly doped region and the gate dielectric region collectively provide for an effective oxide thickness of the FinFET device that allow a low electric field across gate oxide and less hot carrier injection.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wei Kuo, Hou-Yu Chen, Shyh-Horng Yang
  • Patent number: 8987870
    Abstract: A bridge rectifier including a common P-type diode, a common N-type diode, two first metal layers, two pairs of second metal layers, two AC inputs and two DC outputs. The P-type diode includes a common P-type doping region, a pair of first N-type substrate regions and a pair of P-type doping regions. The N-type diode includes a common N-type doping region, a pair of second N-type substrate regions and a pair of N-type doping regions. The first metal layers connect to the common N-type doping region and the common P-type doping region. The second metal layers connect to the P-type doping region and the N-type doping region. Two AC inputs connect to one of the second metal layers of the P-type diode and one of the second metal layers of the N-type diode respectively. Two DC inputs connect to the first metal layers respectively.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: March 24, 2015
    Assignee: Lite-On Semiconductor Corp.
    Inventor: Ching-Chiu Tseng
  • Patent number: 8987825
    Abstract: A semiconductor device includes a substrate having a first type doping. The semiconductor device further includes a first deep well in the substrate, the first deep well having a second type doping. The semiconductor device further includes a second deep well in the substrate, the second deep well having the second type doping and being separated and above the first deep well. The semiconductor device further includes a first well over the second deep well, the first well having the first type doping and a gate structure over the first well.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hua-Chou Tseng, Chien-Chih Ho
  • Patent number: 8963259
    Abstract: Embodiments herein provide approaches for device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of replacement fins is formed over the retrograde doped layer, each of the set of replacement fins comprising a high mobility channel material (e.g., silicon, or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of replacement fins to prevent carrier spill-out to the replacement fins.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: February 24, 2015
    Assignees: GlobalFoundries Inc., International Business Machines Corporation, Renesas Electronics Corporation
    Inventors: Ajey P. Jacob, Murat K. Akarvardar, Steven J. Bentley, Toshiharu Nagumo, Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz
  • Patent number: 8889452
    Abstract: A piezoelectric device includes a piezoelectric thin film formed by separating and forming a piezoelectric single crystal substrate, an inorganic layer formed on a back surface of the piezoelectric thin film, an elastic body layer disposed on a surface opposite to the piezoelectric thin film of the inorganic layer, and a support pasted to a surface opposite to the inorganic layer of the elastic body layer. In a membrane structure portion, the inorganic layer and the elastic body layer are disposed on the piezoelectric thin film through a gap layer. The elastic body layer reduces a stress caused by pasting the piezoelectric thin film including the inorganic layer and the support and has a certain elastic modulus. The inorganic layer is formed with a material having an elastic modulus higher than that of the elastic body layer and suppresses damping caused by disposing the elastic body layer.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: November 18, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Takashi Iwamoto
  • Patent number: 8816447
    Abstract: Devices such as transistors having an oxide layer that provide a depletion field in a conduction channel. A barrier layer is formed over the oxide layer. A gate electrode is formed over the barrier layer. The barrier layer and gate electrode are configured to reduce the width of the depletion field absent a voltage applied to the gate electrode.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: August 26, 2014
    Assignee: Round Rock Research, LLC
    Inventors: Shuang Meng, Garo J. Derderian, Gurtej S. Sandhu
  • Patent number: 8815654
    Abstract: A Silicon on Insulator (SOI) Integrated Circuit (IC) chip with devices such as a vertical Silicon Controlled Rectifier (SCR), vertical bipolar transistors, a vertical capacitor, a resistor and/or a vertical pinch resistor and method of making the device(s). The devices are formed in a seed hole through the SOI surface layer and insulator layer to the substrate. A buried diffusion, e.g., N-type, is formed through the seed hole in the substrate. A doped epitaxial layer is formed on the buried diffusion and may include multiple doped layers, e.g., a P-type layer and an N-type layer. Polysilicon, e.g., P-type, may be formed on the doped epitaxial layer. Contacts to the buried diffusion are formed in a contact liner.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Robert J. Gauthier, Jr., Junjun Li, Souvick Mitra, Mahmoud A Mousa, Christopher S. Putnam
  • Patent number: 8785980
    Abstract: A semiconductor memory device includes a memory cell array layer which includes a first wiring line, a memory cell stacked on the first wiring line, and a second wiring line formed on the memory cell so as to intersect the first wiring line, wherein a step is formed in the first wiring line so that the height of an upper surface of the first wiring line in the memory cell array region where the memory cell array is formed is higher than the height in a peripheral region around the memory cell array region.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: July 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoya Osaki, Naohito Morozumi
  • Patent number: 8748960
    Abstract: A multi-layer integrated circuit package includes a switched-mode power supply circuit including a plurality of transistors which form part of a main current loop of the switched-mode power supply circuit. The plurality of transistors are arranged in one or more layers of the integrated circuit package. The package further includes a conductive plate arranged in a different layer of the integrated circuit package than the plurality of transistors. The conductive plate is in close enough proximity to at least part of the main current loop so that a current can be electromagnetically induced in the conductive plate responsive to a change in current in the main current loop.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: June 10, 2014
    Assignee: Infineon Technologies AG
    Inventor: Jens Ejury
  • Patent number: 8735971
    Abstract: A SGT production method includes a step of forming first and second fin-shaped silicon layers, forming a first insulating film, and forming first and second pillar-shaped silicon layers; a step of forming diffusion layers by implanting an impurity into upper portions of the first and second pillar-shaped silicon layers, upper portions of the first and second fin-shaped silicon layers, and lower portions of the first and second pillar-shaped silicon layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers formed in the upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing and etching the first and second polysilicon gate electrodes, then depositing a metal, and forming first and second metal gate electrodes.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: May 27, 2014
    Assignee: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Publication number: 20140117511
    Abstract: A passivation layer and a method of making a passivation layer are disclosed. In one embodiment the method for manufacturing a passivation layer includes depositing a first silicon based dielectric layer on a workpiece, the first silicon based dielectric layer comprising nitrogen, and depositing in-situ a second silicon based dielectric layer on the first silicon based dielectric layer, the second dielectric layer comprising oxygen.
    Type: Application
    Filed: October 30, 2012
    Publication date: May 1, 2014
    Applicant: Infineon Technologies AG
    Inventors: Kurt Matoy, Hubert Maier, Christian Krenn, Elfriede Kraxner Wellenzohn, Helmut Schoenherr, Juergen Steinbrenner, Markus Kahn, Fister Schlemitz Silvana, Christoph Brunner, Herbert Gietler, Uwe Hoeckele
  • Publication number: 20140117502
    Abstract: A method for processing a semiconductor carrier is provided, the method including: providing a semiconductor carrier including a doped substrate region and a device region disposed over a first side of the doped substrate region, the device region including at least part of one or more electrical devices; and implanting ions into the doped substrate region to form a gettering region in the doped substrate region of the semiconductor carrier.
    Type: Application
    Filed: October 25, 2012
    Publication date: May 1, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Johannes Laven, Hans-Joachim Schulze
  • Patent number: 8698281
    Abstract: A nonvolatile memory device, a method of fabricating the nonvolatile memory device and a processing system including the nonvolatile memory device. The nonvolatile memory device may include a plurality of internal electrodes that extend in a direction substantially perpendicular to a face of a substrate, a plurality of first external electrodes that extend substantially in parallel with the face of the substrate, and a plurality of second external electrodes that also extend substantially in parallel with the face of the substrate. Each first external electrode is on a first side of a respective one of the internal electrodes, and each second external electrode is on a second side of a respective one of the internal electrodes. These devices also include a plurality of variable resistors that contact the internal electrodes, the first external electrodes and the second external electrodes.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: April 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-Gyu Baek, Hyun-Jun Sim, Jin-Shi Zhao, Eun-Kyung Yim
  • Patent number: 8686536
    Abstract: An embodiment is a fuse structure. In accordance with an embodiment, a fuse structure comprises an anode, a cathode, a fuse link interposed between the anode and the cathode, and cathode connectors coupled to the cathode. The cathode connectors are each equivalent to or larger than about two times a minimum feature size of a contact that couples to an active device.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: April 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shien-Yang Wu, Wei-Chan Kung
  • Publication number: 20140054699
    Abstract: An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one shallow trench isolation (STI) region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include an oxide layer lining a bottom portion of the sidewall surface, a nitride layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers.
    Type: Application
    Filed: August 21, 2012
    Publication date: February 27, 2014
    Applicants: STMicroelectronics, Inc., COMMISSARIATE A ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: QING LIU, PRASANNA KHARE, NICOLAS LOUBET, SHOM PONOTH, MAUD VINET, BRUCE DORIS
  • Patent number: 8648442
    Abstract: A semiconductor device having a transistor circuit and a bleeder resistance circuit is provided in which fluctuations in resistance value of a bleeder resistor are reduced. In the transistor circuit, a barrier metal film and a interconnect film are layered as a metal film on an interlayer insulating film above transistor structure. In the bleeder resistance circuit, the interconnect film is layered as a metal film on the interlayer insulating film above the bleeder resistor formed from polysilicon film. Alternatively, the metal film in the bleeder resistance circuit includes the barrier metal film only in a portion where the metal film is connected to the bleeder resistor. This reduces stress to the bleeder resistor formed from a polysilicon film, and the resistance value of the bleeder resistor accordingly fluctuates less. In addition, since the metal film used as interconnect of the transistor circuit includes the barrier metal film, interconnect reliability is not impaired.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: February 11, 2014
    Assignee: Seiko Instruments Inc.
    Inventor: Seiichi Hirabayashi
  • Patent number: 8647922
    Abstract: The present invention relates to a method of forming a wire bond-free conductive interconnect area on a semiconductor substrate. A semiconductor substrate with an electrically conductive protrusion, defining a bond pad, is provided as well as a plurality of carbon nanotubes. The plurality of carbon nanotubes is immobilized on the bond pad by allowing at least one random portion along the length of the carbon nanotubes to attach to the surface of the bond pad. Thus an aggregate of loops of carbon nanotubes is formed on the surface of the bond pad. Thereby a conductive interconnect area is formed on the electrically conductive protrusion without heat treatment.
    Type: Grant
    Filed: November 8, 2007
    Date of Patent: February 11, 2014
    Assignee: Nanyang Technological University
    Inventors: Jijie Zhou, Zhong Chen
  • Publication number: 20130328157
    Abstract: A method of forming improved spacer isolation in deep trench including recessing a node dielectric, a first conductive layer, and a second conductive layer each deposited within a deep trench formed in a silicon-on-insulator (SOI) substrate, to a level below a buried oxide layer of the SOI substrate, and creating an opening having a bottom surface in the deep trench. Further including depositing a spacer along a sidewall of the deep trench and the bottom surface of the opening, and removing the spacer from the bottom surface of the opening. Performing at least one of an ion implantation and an ion bombardment in one direction at an angle into an upper portion of the spacer. Removing the upper portion of the spacer from the sidewall of the deep trench. Depositing a third conductive layer within the opening.
    Type: Application
    Filed: June 6, 2012
    Publication date: December 12, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Joseph Ervin, Chengwen Pei, Ravi M. Todi, Geng Wang
  • Patent number: 8604618
    Abstract: A semiconductor device and a method of fabricating the same, includes vertically stacked layers on an insulator. Each of the layers includes a first dielectric insulator portion, a first metal conductor embedded within the first dielectric insulator portion, a first nitride cap covering the first metal conductor, a second dielectric insulator portion, a second metal conductor embedded within the second dielectric insulator portion, and a second nitride cap covering the second metal conductor. The first and second metal conductors form first vertically stacked conductor layers and second vertically stacked conductor layers. The first vertically stacked conductor layers are proximate the second vertically stacked conductor layers, and at least one air gap is positioned between the first vertically stacked conductor layers and the second vertically stacked conductor layers.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: December 10, 2013
    Assignee: International Business Machines Corporation
    Inventors: Edward C. Cooney, III, Jeffrey P. Gambino, Zhong-Xiang He, Xiao Hu Liu, Thomas L. McDevitt, Gary L. Milo, William J. Murphy
  • Patent number: 8604585
    Abstract: A fuse of a semiconductor device includes a plurality of first conductive patterns, and a plurality of second conductive patterns filling spaces between the first conductive patterns and formed of a material which has a greater specific resistance than the first conductive patterns.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: December 10, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Buem-Suck Kim
  • Patent number: 8604562
    Abstract: The embodiments of mechanisms described enables improved planarity of substrates, which is crucial for patterning and device yield improvement. Chemical-mechanical polishing (CMP) is used to remove film to planarize the substrate before the final thickness is reached or before all removal film is polished. The substrate is then measured for its topography and film thickness. The topography and thickness data are used by the gas cluster ion beam (GCIB) etch tool to determine how much film to remove on a particular location. GCIB etch enables removal of final layer to meet the requirements of substrate uniformity and thickness target. The mechanisms enable improved planarity to meet the requirement of advanced processing technologies.
    Type: Grant
    Filed: May 8, 2012
    Date of Patent: December 10, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Shiang-Bau Wang
  • Publication number: 20130320484
    Abstract: An apparatus of and method for making a semiconductor structure having a shallow trench isolation (STI) trench with a substantially v-shaped profile, that is the distance between top portions is greater than the distance between bottom portions of shallow trench isolation (STI) structure sidewalls adjacent to the trench, provides for substantially seamless and substantially void-free gate structures. The semiconductor structures are formed by implanting an implantation species into the sidewalls, which allows for the top portions of the sidewalls to be etched away at a greater rate than that of the bottom portions, resulting in the substantially v-shaped profile. And the substantially v-shaped profile allows for subsequent device layers to more easily and smoothly fill in the v-shaped trenches, due to a wider opening toward the tops of the trenches.
    Type: Application
    Filed: June 5, 2012
    Publication date: December 5, 2013
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: JUNG-YI GUO, CHUN-MIN CHENG
  • Patent number: 8581342
    Abstract: A semiconductor device with a field electrode and method. One embodiment provides a controllable semiconductor device including a control electrode for controlling the semiconductor device and a field electrode. The field electrode includes a number of longish segments which extend in a first lateral direction and which run substantially parallel to one another. The control electrode includes a number of longish segments extending in a second lateral direction and running substantially parallel to one another, wherein the first lateral direction is different from the second lateral direction.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: November 12, 2013
    Assignee: Infineon Technologies Austria AG
    Inventor: Oliver Haeberlen
  • Publication number: 20130292799
    Abstract: A semiconductor device comprises a substrate, a dielectric layer, an undoped silicon layer, and a silicon material. The substrate comprises a doped region. The dielectric layer is formed on the substrate and comprises a contact hole, and the contact hole corresponds to the doped region. The undoped silicon layer is formed on the doped region. The silicon material fills the contact hole from the undoped silicon layer.
    Type: Application
    Filed: May 3, 2012
    Publication date: November 7, 2013
    Inventors: Yi Jung CHEN, Kuo Hui Su, Chiang Hung Lin
  • Patent number: 8575678
    Abstract: To provide a semiconductor memory device having a floating gate which operates with a short channel. A high-work-function compound semiconductor having a work function of greater than or equal to 5.5 eV, such as indium nitride or zinc nitride, is used for the floating gate. Accordingly, the potential barrier of the floating gate insulating film between the substrate and the floating gate is higher than that of a conventional one, so that leakage of electric charge due to a tunnel effect can be reduced even if the thickness of the floating gate insulating film is made small. Since the thickness of the floating gate insulating film can be made small, the channel can be further shortened.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: November 5, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Publication number: 20130285211
    Abstract: Device structures, design structures, and fabrication methods for fin-type field-effect transistor integrated circuit technologies. First and second fins, which constitute electrodes of the device structure, are each comprised of a first semiconductor material. The second fin is formed adjacent to the first fin to define a gap separating the first and second fins. Positioned in the gap is a layer comprised of a second semiconductor material.
    Type: Application
    Filed: April 25, 2012
    Publication date: October 31, 2013
    Applicant: International Business Machines Corporation
    Inventors: Robert J. Gauthier, JR., Jeffrey B. Johnson, Junjun Li
  • Patent number: 8569864
    Abstract: A capacitor structure includes a lower electrode layer disposed on a substrate, an upper electrode layer and a crystalline zinc oxide-containing dielectric layer interposed between the electrode layers. The amorphous dielectric intermediate layer is interposed between the lower electrode layer and the crystalline zinc oxide-containing dielectric layer. A method for producing the aforementioned capacitor structure is also disclosed. The amorphous dielectric layer is adapted to produce during deposition of the zinc oxide an electrical field which is tipped in relation to the normal to the surface of the substrate surface or the lower electrode layer. The zinc oxide monocrystals grow at an angle, thereby providing a crystalline dielectric layer that can be induced to shear vibrations.
    Type: Grant
    Filed: August 2, 2005
    Date of Patent: October 29, 2013
    Assignee: Siemens Aktiengesellschaft
    Inventors: Reinhard Gabl, Mathias Link
  • Publication number: 20130277795
    Abstract: Line trenches are formed in a stack of a bulk semiconductor substrate and an oxygen-impermeable layer such that the depth of the trenches in the bulk semiconductor substrate is greater than the lateral spacing between a pair of adjacently located line trenches. Oxygen-impermeable spacers are formed on sidewalls of the line trenches. An isotropic etch, either alone or in combination with oxidation, removes a semiconductor material from below the oxygen-impermeable spacers to expand the lateral extent of expanded-bottom portions of the line trenches, and to reduce the lateral spacing between adjacent expanded-bottom portions. The semiconductor material around the bottom portions is oxidized to form a semiconductor oxide portion that underlies multiple oxygen-impermeable spacers. Semiconductor-on-insulator (SOI) portions are formed above the semiconductor oxide portion and within the bulk semiconductor substrate.
    Type: Application
    Filed: April 19, 2012
    Publication date: October 24, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Solomon Assefa, William M. J. Green, Marwan H. Khater, Yurii A. Vlasov
  • Publication number: 20130264683
    Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a base, a stacked structure and a doped layer. The stacked structure is formed on the base, wherein the stacked structure comprises a plurality of conductive strips and a plurality of insulating strips, one of the conductive strips is located between adjacent two insulating strips, the stacked structure has a first side wall, and a long edge of the first side wall is extended along a channel direction. The doped layer is formed in the first side wall, wherein the doped layer is formed by an ion implantation applied to the first side wall, and an acute angle is contained between an implantation direction of the ion implantation and the first side wall.
    Type: Application
    Filed: April 10, 2012
    Publication date: October 10, 2013
    Applicant: Macronix International Co., Ltd.
    Inventors: Shih-Hung Chen, Hang-Ting Lue, Kuang-Yeu Hsieh
  • Patent number: 8541775
    Abstract: A schottky diode, a resistive memory device including the schottky diode and a method of manufacturing the same. The resistive memory device includes a semiconductor substrate including a word line, a schottky diode formed on the word line, and a storage layer formed on the schottky diode. The schottky diode includes a first semiconductor layer, a conductive layer formed on the first semiconductor layer and having a lower work function than the first semiconductor layer, and a second semiconductor layer formed on the to conductive layer.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: September 24, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Seung Beom Baek, Young Ho Lee, Jin Ku Lee, Mi Ri Lee
  • Patent number: 8531007
    Abstract: A semiconductor device is disclosed which includes active section 100, edge termination section 110 having a voltage blocking structure and disposed around active section 100, and separation section 120 having a device separation structure and disposed around edge termination section 110. A surface device structure is formed on the first major surface of active section 100, trench 23 is formed in separation section 120 from the second major surface side, and p+-type separation region 24 is formed on the side wall of trench 23 such that p+-type separation region 24 is in contact with p-type channel stopper region 21 formed in the surface portion on the first major surface side and p-type collector layer 9 formed in the surface portion on the second major surface side. The semiconductor device and the method for manufacturing the semiconductor device according to the invention facilitate preventing the reverse blocking voltage from decreasing and shorten the manufacturing time of the semiconductor device.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: September 10, 2013
    Assignees: Octec, Inc., Fuji Electric Co., Ltd.
    Inventors: Katsuya Okumura, Hiroki Wakimoto, Kazuo Shimoyama, Tomoyuki Yamazaki
  • Patent number: 8502355
    Abstract: An overlay vernier mask pattern of a semiconductor device includes a first overlay vernier mask pattern having a first opening for exposing a first area of a layer to be etched on a substrate and a second opening for exposing a second area spaced apart from the first area, and a second overlay vernier mask pattern aligned on the first overlay vernier mask pattern and the layer to be etched, and having an opening for exposing the second opening while exposing a portion of the layer to be etched in the first area.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: August 6, 2013
    Assignee: SK Hynix Inc.
    Inventor: Joon Seuk Lee
  • Publication number: 20130181320
    Abstract: Some embodiments relate to a method for processing a workpiece. In the method, an anti-reflective coating layer is provided over the workpiece. A first patterned photoresist layer, which has a first photoresist tone, is provided over the anti-reflective coating layer. A second patterned photoresist layer, which has a second photoresist tone opposite the first photoresist tone, is provided over the first patterned photoresist layer. An opening extends through the first and second patterned photoresist layers to allow a treatment to be applied to the workpiece through the opening. Other embodiments are also disclosed.
    Type: Application
    Filed: January 13, 2012
    Publication date: July 18, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Chang Chen, Shih-Chi Fu, Wang-Pen Mo, Hung-Chang Hsieh
  • Patent number: 8476688
    Abstract: A semiconductor device that prevents the leaning of storage node when forming a capacitor having high capacitance includes a plurality of cylinder-shaped storage nodes formed over a semiconductor substrate; and support patterns formed to fix the storage nodes in the form of an ‘L’ or a ‘+’ when viewed from the top. This semiconductor device having support patterns in the form of an ‘L’ or a ‘+’ reduces stress on the storage nodes when subsequently forming a dielectric layer and plate nodes that prevents the capacitors from leaking.
    Type: Grant
    Filed: October 2, 2008
    Date of Patent: July 2, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ho Jin Cho, Cheol Hwan Park, Jae Wook Seo, Jong Kuk Kim
  • Publication number: 20130161798
    Abstract: Methods and structure are provided for utilizing a dielectric mask layer having a gradated density structure. The density of the dielectric mask layer is greatest at the interface of the dielectric mask layer and an underlying dielectric layer. The density of the dielectric mask layer is lowest at the interface of the dielectric mask layer and an overlaying hard mask. The lower density dielectric mask layer is more susceptible to removal than the higher density dielectric mask layer. The lower density dielectric mask layer is removed during at least one of an RIE etch or a post-RIE etch wet clean. Selective removal of the lower density dielectric mask layer creates a dielectric mask layer having a rounded profile. The dielectric mask layer comprises tetraethyl orthosilicate.
    Type: Application
    Filed: December 22, 2011
    Publication date: June 27, 2013
    Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
    Inventor: Hideyuki Tomizawa
  • Patent number: 8466044
    Abstract: Memory cells, and methods of forming such memory cells, are provided that include a carbon-based reversible resistivity switching material. In particular embodiments, methods in accordance with this invention form a memory cell by forming a carbon-based reversible resistance-switching material above a substrate, forming a carbon nitride layer above the carbon-based reversible resistance-switching material, and forming a barrier material above the carbon nitride layer using an atomic layer deposition process. Other aspects are also provided.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: June 18, 2013
    Assignee: SanDisk 3D LLC
    Inventor: Huiwen Xu
  • Publication number: 20130147067
    Abstract: A method of manufacturing a semiconductor structure includes varying local chemical mechanical polishing (CMP) abrading rates of an insulator film by selectively varying a carbon content of the insulator film.
    Type: Application
    Filed: December 12, 2011
    Publication date: June 13, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yoba AMOAH, Graham M. BATES, Jospeh P. HASSELBACH, Thomas L. MCDEVITT, Eva A. SHAH
  • Patent number: 8455985
    Abstract: An integrated circuit device includes a plurality of stacked circuit layers, at least one of the plurality of circuit layers including a composite interlayer insulation layer including laterally adjacent first and second insulating material regions having different mechanical strengths and dielectric properties and a plurality of circuit components disposed in the composite interlayer insulation layer. The first insulating material region may have a lower dielectric constant and a lower mechanical strength than the second insulating material region such that, for example, the first insulating material region may be positioned near signal lines or other circuit features to reduce capacitance while using the second insulating material region near a location that is susceptible to localized mechanical stress, such as a fuse location, an external connection bonding location or a scribe line location.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: June 4, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyu-hee Han, Sang-hoon Ahn, Eunkee Hong
  • Publication number: 20130113085
    Abstract: Provided are low temperature methods of depositing hafnium or zirconium containing films using a Hf(BH4)4 precursor, or Zr(BH4)4 precursor, respectively, as well as a co-reactant. The co-reactant can be selected to obtain certain film compositions. Co-reactants comprising an oxidant can be used to deposit oxygen into the film. Accordingly, also provided are films comprising a metal, boron and oxygen, wherein the metal comprises hafnium where a Hf(BH4)4 precursor is used, or zirconium, where a Zr(BH4)4 precursor is used.
    Type: Application
    Filed: November 4, 2011
    Publication date: May 9, 2013
    Applicant: Applied Materials, Inc.
    Inventors: Timothy Michaelson, Timothy W. Weidman, Paul Deaton
  • Patent number: 8436350
    Abstract: In forming a thin film transistor, an oxide semiconductor layer is used and a cluster containing a titanium compound whose electrical conductance is higher than that of the oxide semiconductor layer is formed between the oxide semiconductor layer and a gate insulating layer.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: May 7, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Hideyuki Kishida
  • Patent number: 8426842
    Abstract: A graphene substrate is doped with one or more functional groups to form an electronic device.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: April 23, 2013
    Assignee: The Invention Science Fund I, LLC
    Inventors: Jeffrey A. Bowers, Roderick A. Hyde, Muriel Y. Ishikawa, Jordin T. Kare, Clarence T. Tegreene, Tatsushi Toyokuni, Richard N. Zare
  • Publication number: 20130093064
    Abstract: A semiconductor process includes the following steps. A substrate is provided. A dielectric layer having a high dielectric constant is formed on the substrate, wherein the steps of forming the dielectric layer include: (a) a metallic oxide layer is formed; (b) an annealing process is performed to the metallic oxide layer; and the steps (a) and (b) are performed repeatedly. Otherwise, the present invention further provides a semiconductor structure formed by said semiconductor process.
    Type: Application
    Filed: October 12, 2011
    Publication date: April 18, 2013
    Inventors: Chien-Liang Lin, Shao-Wei Wang, Yu-Ren Wang, Ying-Wei Yen
  • Patent number: 8395243
    Abstract: A semiconductor device has a multilayer doping to provide improved passivation by quantum exclusion. The multilayer doping includes a plurality M of doped layers, where M is an integer greater than 1. The dopant sheet densities in the M doped layers need not be the same, but in principle can be selected to be the same sheet densities or to be different sheet densities. M?1 interleaved layers provided between the M doped layers are not deliberately doped (also referred to as “undoped layers”). Structures with M=2, M=3 and M=4 have been demonstrated and exhibit improved passivation.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: March 12, 2013
    Assignee: California Institute of Technology
    Inventor: Michael E. Hoenk
  • Patent number: 8362540
    Abstract: A multi-layer integrated circuit package includes a switched-mode power supply circuit including a plurality of transistors which form part of a main current loop of the switched-mode power supply circuit. The plurality of transistors are arranged in one or more layers of the integrated circuit package. The package further includes a conductive plate arranged in a different layer of the integrated circuit package than the plurality of transistors. The conductive plate is in close enough proximity to at least part of the main current loop so that a current can be electromagnetically induced in the conductive plate responsive to a change in current in the main current loop.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: January 29, 2013
    Assignee: Infineon Technologies AG
    Inventor: Jens Ejury
  • Publication number: 20130020684
    Abstract: The actinic ray-sensitive or radiation-sensitive resin composition according to the present invention includes a resin (A) which contains at least one type of repeating unit which is represented by the general formula (PG1), at least one type of repeating unit which is selected from the repeating units which are represented by the general formula (PG2) and the general formula (PG3), and at least one type of repeating unit which includes a lactone structure, a compound (B) which is a compound which is represented by the general formula (B1) and where the molecular weight of an anion moiety is 200 or less, and a solvent (C).
    Type: Application
    Filed: July 2, 2012
    Publication date: January 24, 2013
    Applicant: FUJIFILM CORPORATION
    Inventor: Kaoru IWATO
  • Publication number: 20120326277
    Abstract: A power semiconductor device and a manufacturing method thereof are provided. The method of manufacturing a power semiconductor device includes the steps: (a) forming a cell structure on a first conductivity type semiconductor substrate; (b) implanting second conductivity type ions onto the rear surface of the first conductivity type semiconductor substrate and activating to form an electrode region; and (c) implanting ions creating first conductivity type with a doping concentration higher than that of the semiconductor substrate and activating to form a high-concentration ion implanted region at a position below the cell structure and on the electrode region. Accordingly, it is possible to form a field stop layer regardless of conditions for forming an electrode region (for example, a P-type collector region) and thus to optimize stable breakdown voltage characteristics and device characteristics.
    Type: Application
    Filed: April 20, 2012
    Publication date: December 27, 2012
    Inventors: Seung-Chul LEE, Eun-Taek KIM