Abstract: Methods of forming buried bit lines in a non-volatile memory device can include forming impurity regions in a substrate of a non-volatile memory device to provide immediately neighboring buried bit lines for the device and then forming a shallow trench isolation region in the substrate between the immediately neighboring buried bit lines to substantially equalize lengths of the immediately neighboring buried bit lines.

Abstract: Described herein are methods of forming dielectric films comprising silicon, oxide, and optionally nitrogen, carbon, hydrogen, and boron. Also disclosed herein are the methods to form dielectric films or coatings on an object to be processed, such as, for example, a semiconductor wafer.

Abstract: In a method of manufacturing a double-implant NOR flash memory structure, a phosphorus ion implantation process is performed, so that a P-doped drain region is formed in a semiconductor substrate between two gate structures to overlap with a highly-doped drain (HDD) region and a lightly-doped drain (LDD) region. Therefore, the electric connection at a junction between the HDD region and the LDD region is enhanced and the carrier mobility in the memory is not lowered while the problems of short channel effect and punch-through of LDD region are solved.

Abstract: Measurement targets for use on substrates, and overlay targets are presented. The targets include an array of first regions alternating with second regions, wherein the first regions include structures oriented in a first direction and the second regions include structures oriented in a direction different from the first direction. The effective refractive index of the two sets of regions are thereby different when experienced by a polarized beam, which will act as a TM-polarized beam when reflected from the first set of regions, but as a TE-polarized beam when reflected from the second set of regions.

Abstract: A method of synthesizing a hyperbranched polymer by living radical polymerization of a monomer in the presence of a metal catalyst includes at least adding a compound or setting the amount of the monomer in the living radical polymerization. The compound added is at least a compound represented by R1-A or a compound represented by R2—B—R3, where R1 denotes hydrogen, an alkyl group (1-10 carbons), aryl group (1-10 carbons), or aralkyl group (7-10 carbons), A denotes a cyano group, hydroxyl group, or nitro group, R2 and R3 denote hydrogen, alkyl groups (1-10 carbons), aryl groups (6-10 carbons), aralkyl groups (7-10 carbons), or dialkylamino groups (2-10 carbons), and B denotes a carbonyl group or sulfonyl group. Setting of the monomer amount includes setting the amount of monomer to be mixed into a reaction system at one mixing to be less than the total monomer to be mixed with the reaction system.

Abstract: Methods and structures relating to the formation of mixed SAMs for preventing undesirable growth or nucleation on exposed surfaces inside a reactor are described. A mixed SAM can be formed on surfaces for which nucleation is not desired by introducing a first SAM precursor having molecules of a first length and a second SAM precursor having molecules of a second length shorter than the first. Examples of exposed surfaces for which a mixed SAM can be provided over include reactor surfaces and select surfaces of integrated circuit structures, such as insulator and dielectric layers.

Abstract: Techniques for forming a phase change memory cell. An example method includes forming a bottom electrode within a substrate. The method includes forming a phase change layer above the bottom electrode. The method includes forming a capping layer and an insulator layer. The method includes crystallizing the phase change material in the phase change layer so that the phase change layer is void free. The method further comprises heating the phase change material in the phase change layer from the bottom electrode and as a result the phase change layer is crystallized from the bottom to the top. In one embodiment, a rapid thermal anneal (RTA) is applied for crystallizing the phase change material.

Abstract: The invention includes a single chip having multiple different devices integrated thereon for a common purpose. The chip includes a substrate having a peripheral area, a mid-chip area, and a central area. A plurality of FETs are formed in the peripheral area with each FET having a layer of single crystal rare earth material in at least one of a conductive channel, a gate insulator, or a gate stack. A plurality of photonic devices including light emitting diodes or vertical cavity surface emitting lasers are formed in the mid-chip area with each photonic device having an active layer of single crystal rare earth material. A plurality of photo detectors are formed in the central area.

Abstract: A method of cleaning a substrate includes contacting a surface of a semiconductor substrate with a composition comprising a superacid. The semiconductor substrate may be a wafer.

Abstract: A semiconductor device, includes a lower layer side insulation film; a wiring pattern formed on the lower layer side insulation film; a base insulation film formed on the lower layer side insulation film and the wiring pattern; and a plurality of metal thin film resistance elements formed on the base insulation film; wherein a connection hole is formed in the base insulation film on the wiring pattern; the wiring pattern and the metal thin film resistance element are electrically connected in the connection hole; the metal thin film resistance element has a belt shape part arranged separately from the connection hole and a connection part continuously formed with the belt shape part and connected to the wiring pattern in the connection hole; and the connection parts of at least two of the metal thin film resistance element are formed in the single connection hole with a gap in between said connection parts.

Abstract: In one embodiment, a second metal line embedded in a second dielectric layer overlies a first metal line embedded in a first dielectric layer. A portion of the second dielectric layer overlying the first metal line is recessed employing a photoresist and the second metal line as an etch mask. A doped semiconductor spacer is formed within the recess to provide a resistive link between the first metal line and the second metal line. In another embodiment, a first metal line and a second metal line are embedded in a dielectric layer. An area of the dielectric layer laterally abutting the first and second metal lines is recessed employing a photoresist and the first and second metal lines as an etch mask. A doped semiconductor spacer is formed on sidewalls of the first and second metal lines, providing a resistive link between the first and second metal lines.

Abstract: The spin transistor in accordance with the present invention comprises a magnetoresistive element having a fixed layer, a free layer, and a semiconductor layer provided between the fixed layer and free layer; a source electrode layer electrically connected to one end face in a laminating direction of the magnetoresistive element; a drain electrode layer electrically connected to the other end face in the laminating direction of the magnetoresistive element; and a gate electrode layer laterally adjacent to the semiconductor layer through a gate insulating layer provided on a side face of the semiconductor layer.

Abstract: A semiconductor device includes a gate electrode having ends that overlap isolation regions, wherein the gate electrode is located over an active region located within a semiconductor substrate. A gate oxide is located between the gate electrode and the active regions, and source/drains are located adjacent the gate electrode and within the active region. An etch stop layer is located over the gate electrode and the gate electrode has at least one electrical contact that extends through the etch stop layer and contacts a portion of the gate electrode that in one embodiment overlies the active region, and in another embodiment is less than one alignment tolerance from the active region.

Abstract: The present invention discloses a method for fabricating a nanoscale thermoelectric device, which comprises steps: providing at least one template having a group of nanoscale pores; forming a substrate on the bottom of the template; injecting a molten semiconductor material into the nanoscale pores to form a group of semiconductor nanoscale wires; removing the substrate to obtain a semiconductor nanoscale wire array; and using metallic conductors to cascade at least two semiconductor nanoscale wire arrays to form a thermoelectric device having a higher thermoelectric conversion efficiency.

Abstract: A chip includes a number a plurality of functional areas of a layer and a number of dummy structures within the layer. The dummy structures are spaced from the functional areas. Each dummy structure has a size that is a function of the size and density of the functional areas.

Abstract: Polymers for extreme ultraviolet and 193 nm photoresists are disclosed. The polymers comprise a photoacid generator (PAG) residue, an acid cleavable residue and a diacid joined by ester linkages. The polymers include a photoacid generating diol, a diacid and an acid table diol.

Abstract: Subject matter disclosed herein relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a method of fabricating a phase change memory device.

Abstract: Improved complementary doping methods are described herein. The complementary doping methods generally involve inducing a first and second chemical reaction in at least a first and second portion, respectively, of a dopant source, which has been disposed on a thin film of a semiconductor or semimetal material. The chemical reactions result in the introduction of an n-type dopant, a p-type dopant, or both from the dopant source to each of the first and second portions of the thin film of the semiconductor or semimetal. Ultimately, the methods produce at least one n-type and at least one p-type region in the thin film of the semiconductor or semimetal.

Abstract: A nonvolatile memory device, a method of fabricating the nonvolatile memory device and a processing system including the nonvolatile memory device. The nonvolatile memory device may include a plurality of internal electrodes that extend in a direction substantially perpendicular to a face of a substrate, a plurality of first external electrodes that extend substantially in parallel with the face of the substrate, and a plurality of second external electrodes that also extend substantially in parallel with the face of the substrate. Each first external electrode is on a first side of a respective one of the internal electrodes, and each second external electrode is on a second side of a respective one of the internal electrodes. These devices also include a plurality of variable resistors that contact the internal electrodes, the first external electrodes and the second external electrodes.

Abstract: A fast recovery diode includes an n-doped base layer having a cathode side and an anode side opposite the cathode side. A p-doped anode layer is arranged on the anode side. The anode layer has a doping profile and includes at least two sublayers. A first one of the sublayers has a first maximum doping concentration, which is between 2*1016 cm?3 and 2*1017 cm?3 and which is higher than the maximum doping concentration of any other sublayer. A last one of the sublayers has a last sublayer depth, which is larger than any other sublayer depth. The last sublayer depth is between 90 to 120 ?m. The doping profile of the anode layer declines such that a doping concentration in a range of 5*1014 cm?3 and 1*1015 cm?3 is reached between a first depth, which is at least 20 ?m, and a second depth, which is at maximum 50 ?m. Such a profile of the doping concentration is achieved by using aluminium diffused layers as the at least two sublayers.

Abstract: In one embodiment, a back-end-of-line (BEOL) resistive structure comprises a second metal line embedded in a second dielectric layer and overlying a first metal line embedded in a first dielectric layer. A doped semiconductor spacer or plug laterally abutting sidewalls of the second metal line and vertically abutting a top surface of the first metal line provides a resistive link between the first and second metal lines. In another embodiment, another BEOL resistive structure comprises a first metal line and a second metal line are embedded in a dielectric layer. A doped semiconductor spacer or plug laterally abutting the sidewalls of the first and second metal lines provides a resistive link between the first and second metal lines.

Abstract: An object thereof is to provide a thermosetting die-bonding film that is capable of preventing warping of an adherend by suppressing curing contraction of the film after die bonding, and a dicing die-bonding film. The present invention relates to a thermosetting die-bonding film for adhering and fixing a semiconductor element onto an adherend, wherein the gel fraction in an organic component after thermal curing is performed by a heat treatment at 120° C. for 1 hour is 20% by weight or less, and the gel fraction in the organic component after thermal curing is performed by a heat treatment at 175° C. for 1 hour is in a range of 10 to 30% by weight.

Abstract: A semiconductor device includes an interlayer insulating film and an inductor. The inductor includes a first soft magnetic thin film pattern formed on the interlayer insulating film, the first soft magnetic film comprising a) at least one material selected from Fe, Co, Ni, or alloys thereof b) at least one element selected from Ti, Hf, or B, and c) N, a metal film pattern formed on the first soft magnetic thin film pattern and a second soft magnetic thin film pattern formed on the metal film pattern, the second soft magnetic thin film pattern comprising a) at least one material selected from Fe, Co, Ni, or alloys thereof; b) at least one element selected from Ti, Hf, or B; and c) N. Edges of the first soft magnetic thin film pattern, edges of the metal film pattern and edges of the second soft magnetic thin film pattern are vertically aligned.

Abstract: Example embodiments provide a complementary metal-oxide semiconductor (CMOS) semiconductor device and a method of fabricating the CMOS semiconductor device. The CMOS semiconductor device may include gates in the nMOS and pMOS areas, polycrystalline silicon (poly-Si) capping layers, metal nitride layers underneath the poly-Si capping layers, and a gate insulating layer underneath the gate. The metal nitride layers of the nMOS and pMOS areas may be formed of the same type of material and may have different work functions. Since a metal gate is formed of identical types of metal nitride layers, a process may be simplified, yield may be increased, and a higher-performance CMOS semiconductor device may be obtained.

Abstract: The present invention provides a film for a semiconductor device, which is capable of preventing interface delamination between each of the films, a film lifting phenomenon, and transfer of the adhesive film onto the cover film even during transportation or after long-term storage in a low temperature condition. The film for a semiconductor device of the present invention is a film in which an adhesive film and a cover film are sequentially laminated on a dicing film, in which a peel force F1 between the adhesive film and the cover film in a T type peeling test is within a range of 0.025 to 0.075 N/100 mm, a peel force F2 between the adhesive film and the dicing film is within a range of 0.08 to 10 N/100 mm, and F1 and F2 satisfy a relationship of F1<F2.

Abstract: A semiconductor device includes a semiconductor substrate and a metal-oxide semiconductor transistor. A first dielectric layer of the metal oxide semiconductor transistor overlaps source and drain electrodes and a channel region of the transistor. A first drain region is away from the channel region and the first dielectric layer. A second drain region is between the first drain region and the channel region. A gate electrode is on the first dielectric layer and connected to a gate wire, and includes first and second gate layers and a dielectric layer therebetween. The first gate layer has one edge laterally spaced from the first drain region and resting over the second drain region, and is isolated from the gate wire. The second gate layer is over the first gate layer and is connected to the gate wire.

Abstract: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

Abstract: A method of manufacturing a semiconductor device comprising: forming a p type region and an n type region in a main surface of a semiconductor substrate, the p type region and the n type region being insulated from each other with an element-isolation region; forming a first insulating film on the p type region and on the n type region, the first insulating film being made of any one of a silicon oxide film and a silicon oxynitride film; forming a lanthanum oxide film on the first insulating film on the p type region; forming a second insulating film both on the lanthanum oxide film on the p type region and on the first insulating film on the n type region, the second insulating film containing any one of hafnium and zirconium; and forming a titanium nitride film on the second insulating film, the titanium nitride film satisfying TixNy where x/y<1.

Abstract: A semiconductor device is formed by forming a second trench 120 at the base of a first trench 18, depositing insulator 124 at the base of the second trench 120, and then etching cavities 26 laterally from the sidewalls of the second trench, but not the base which is protected by insulator 124. The invention may in particular be used to form semiconductor devices with cavities under the active components, or by filling the cavities to form silicon on insulator or silicon on conductor devices.

Abstract: An integrated circuit having voltage isolation capabilities comprising a first galvanically isolated area of the integrated circuit containing a first group of functional circuitry for processing a data stream. The first group of functional circuitry located in a substrate of the integrated circuit. Capacitive isolation circuitry located in conductive layers of the integrated circuit provides a high voltage isolation link between the first group of functional circuitry and a second group of functional circuitry connected to the integrated circuit through the capacitive isolation circuitry. The capacitive isolation circuitry includes a differential transmitter for transmitting data in a differential signal to the second group of functional circuitry via the capacitive isolation circuitry. A differential receiver receives data within the differential signal from the second group of functional circuitry via the capacitive isolation circuitry.

Abstract: A method for generating a layout, use of a transistor layout, and semiconductor circuit is provided that includes a matching structure, which has a number of transistors, whose structure is similar to one another, metallization levels with geometrically formed traces, which are formed directly above the transistors, and vias (in via levels), which are formed between two of the metallization levels. Whereby, within one and the same metallization level, the geometry of the traces above each transistor is formed the same.

Abstract: A method for manufacturing a semiconductor body with a trench comprises the steps of etching the trench (11) in the semiconductor body (10) and forming a silicon oxide layer (12) on at least one side wall (14) of the trench (11) and on the bottom (15) of the trench (11) by means of thermal oxidation. Furthermore, the silicon oxide layer (12) on the bottom (15) of the trench (11) is removed and the trench (11) is filled with polysilicon that forms a polysilicon body (13).

Abstract: An integrated circuit (200) includes one of more transistors (210) on or in a substrate (10) having semiconductor surface layer, the surface layer having a top surface. At least one of the transistors are drain extended metal-oxide-semiconductor (DEMOS) transistor (210). The DEMOS transistor includes a drift region (14) in the surface layer having a first dopant type, a field dielectric (23) in or on a portion of said surface layer, and a body region of a second dopant type (16) within the drift region (14). The body region (16) has a body wall extending from the top surface of the surface layer downwards along at least a portion of a dielectric wall of an adjacent field dielectric region. A gate dielectric (21) is on at least a portion of the body wall. An electrically conductive gate electrode (22) is on the gate dielectric (21) on the body wall.

Abstract: A semiconductor device includes active areas which are insulatedly separated from each other by element-separation insulating films; a gate insulating film formed on each active area; a gate electrode which extends across the active area via the gate insulating film; a source area and a drain area formed in the active area so as to interpose the gate electrode; and a fin-channel structure in which at the intersection between the active area and the gate electrode, trenches are provided at both sides of the active area, and part of the gate electrode is embedded in each trench via the gate insulating film, so that the gate electrode extends across a fin which rises between the trenches. In the gate insulating film, the film thickness of a part which contacts the bottom surface of each trench is larger than that of a part which contacts the upper surface of the fin.

Abstract: Improved high quality gate dielectrics and methods of preparing such dielectrics are provided. Preferred dielectrics comprise a rare earth doped dielectric such as silicon dioxide or silicon oxynitride. In particular, cerium doped silicon dioxide shows an unexpectedly high charge-to-breakdown QBD, believed to be due to conversion of excess hot electron energy as photons, which reduces deleterious hot electron effects such as creation of traps or other damage. Rare earth doped dielectrics therefore have particular application as gate dielectrics or gate insulators for semiconductor devices such as floating gate MOSFETs, as used in as flash memories, which rely on electron injection and charge transfer and storage.

Abstract: A method for simultaneous recrystallisation and doping of semiconductor layers, in particular for the production of crystalline silicon thin layer solar cells. A substrate base layer 1 is produced, and subsequently, an intermediate layer system 2 which has at least one doped partial layer is deposited on the base layer. An absorber layer 3 which is undoped or likewise doped is deposited on the intermediate layer system 2, and in a recrystallisation step, the absorber layer 3 is heated, melted, cooled and tempered. Alternately, instead of an undoped capping layer, a capping layer system 4 which has at least one partial layer can also be applied on the absorber layer 3.

Abstract: Bidirectional switches are described. The bidirectional switches include first and a second III-N based high electron mobility transistor. In some embodiments, the source of the first transistor is in electrical contact with a source of the second transistor. In some embodiments, the drain of the first transistor is in electrical contact with a drain of the second transistor. In some embodiments, the two transistors share a drift region and the switch is free of a drain contact between the two transistors. Matrix converters can be formed from the bidirectional switches.

Abstract: An embedded flash memory device and a method for fabricating the same which reduces the size of a memory device using logic CMOS fabricating processes and enhancing a coupling ratio of the memory device. The flash memory device includes a coupling oxide layer on an active area of a semiconductor substrate, a first control gate formed on and/or over the coupling oxide layer and a second control gate formed on and/or over and enclosing lateral sidewalls of the coupling oxide layer and the first control gate.

Abstract: In a semiconductor device having element isolation made of a trench-type isolating oxide film 13, large and small dummy patterns 11 of two types, being an active region of a dummy, are located in an isolating region 10, the large dummy patterns 11b are arranged at a position apart from actual patterns 9, and the small dummy patterns 11a are regularly arranged in a gap at around a periphery of the actual patterns 9, whereby uniformity of an abrading rate is improved at a time of abrading an isolating oxide film 13a is improved, and surface flatness of the semiconductor device becomes preferable.

Abstract: A semiconductor device is provided with first and second silicon pillars formed substantially perpendicularly to a main surface of a substrate, a gate electrode covering side surfaces of the first and second silicon pillars via a gate insulation film, first and second diffusion layers provided on a lower part and an upper part of the first silicon pillar, respectively, a cap insulation film covering an upper part of the second silicon pillar, a gate contact connected to the gate electrode, and a protection insulation film in contact with the upper surfaces of the first and second silicon pillars. The gate contact is connected to an upper region of the gate electrode provided at the periphery of the cap insulation film. An opening is formed on the protection insulation film provided at the side of the first silicon pillar.

Abstract: An integrated switching device has a switching IGFET connected between a pair of main terminals, a protector IGFET connected between the drain and gate electrodes of the switching IGFET, and a gate resistor connected between a main control terminal and the gate electrode of the switching IGFET. The protector IGFET has its gate electrode connected to the source electrode of the switching IGFET. The protector IGFET turns on in response to an application of a verse voltage to the switching IGFET thereby protecting the same from a reverse current flow.

Abstract: The invention relates to a method for making a handle wafer (20?) for microelectronic functional wafers, including at least one transparent window (22, 24) for viewing through the thickness of the handle wafer, this method including: a) the making of at least one cavity (21, 23) in said handle wafer, b) the formation of at least one viewing window in said cavity on an alignment or receiving surface.

Abstract: A method of forming features on a target layer. The features have a critical dimension that is triple- or quadruple-reduced compared to the critical dimension of portions of a resist layer used as a mask. An intermediate layer is deposited over a target layer and the resist layer is formed over the intermediate layer. After patterning the resist layer, first spacers are formed on sidewalls of remaining portions of the resist layer, masking portions of the intermediate layer. Second spacers are formed on sidewalls of the portions of the intermediate layer. After removing the portions of the intermediate layer, the second spacers are used as a mask to foil the features on the target layer. A partially fabricated integrated circuit device is also disclosed.

Abstract: Disclosed herein are multilayer electronic devices comprising a high dielectric constant polymer composite layer that contains conductive components for embedded capacitor applications

Abstract: Disclosed are embodiments of an improved integrated circuit switching device that incorporates multiple sets of series connected field effect transistors with each set further connected in parallel between two nodes. The sets are arranged in a linear fashion with each set positioned such that it is in contact with and essentially symmetrical relative to an adjacent set. Arranging the sets in this manner allows adjacent diffusion regions of the same type (i.e., sources or drains) from adjacent sets to be merged. Merging of the diffusion regions provides several benefits, including but not limited to, reducing the device size, reducing the amount of required wiring for the device (i.e., reducing resistance) and reducing side capacitance between the now merged diffusion regions and the substrate. Also disclosed are embodiments of an associated design structure for the device and an associated method of forming the device.

Abstract: A method for opening a carbon-based hardmask layer formed on an etch layer over a substrate is provided. The hardmask layer is disposed below a patterned mask. The substrate is placed in a plasma processing chamber. The hardmask layer is opened by flowing a hardmask opening gas including a COS component into the plasma chamber, forming a plasma from the hardmask opening gas, and stopping the flow of the hardmask opening gas. The hardmask layer may be made of amorphous carbon, or made of spun-on carbon, and the hardmask opening gas may further include O2.

Abstract: An IC device (100) includes an IC body (106) having a base layer (108) and first and second upper layers (114, 116) on the base layer. The IC body includes a cavity region (104) extending through said base and first upper layers and at least a portion of said second upper layer. In the IC device, a portion of said second upper layer in the cavity region comprises a planar inductive element (102) having first and second contacting ends (140, 142). In the IC device, at least one support member (128, 130, 132) extends at least partially into said cavity region from said IC body in at least a first direction parallel to said base layer and intersects at least a portion of said planar inductive element.

Abstract: Provided herein, according to some embodiments of the invention, are organosilane polymers prepared by reacting organosilane compounds including (a) at least one compound of Formula I Si(OR1)(OR2)(OR3)R4??(I) wherein R1, R2 and R3 may each independently be an alkyl group, and R4 may be —(CH2)nR5, wherein R5 may be an aryl or a substituted aryl, and n may be 0 or a positive integer; and (b) at least one compound of Formula II Si(OR6)(OR7)(OR8)R9??(II) wherein R6, R7 and R8 may each independently an alkyl group or an aryl group; and R9 may be an alkyl group. Also provided are hardmask compositions including an organosilane compound according to an embodiment of the invention, or a hydrolysis product thereof. Methods of producing semiconductor devices using a hardmask compostion according to an embodiment of the invention, and semiconductor devices produced therefrom, are also provided.

Abstract: An electronic circuit device comprises a silicon substrate having front and rear surfaces, a semiconductor element formed on the front surface, and at least one through-hole penetrating through the front surface and the rear surface. At least one passive element is supported by the silicon substrate. At least one connecting element is disposed in the through-hole of the silicon substrate for electrically connecting the semiconductor element to the passive element.

Abstract: A semiconductor device comprising source and drain regions and insulating region and a plate structure. The source and drain regions are on or in a semiconductor substrate. The insulating region is on or in the semiconductor substrate and located between the source and drain regions. The insulating region has a thin layer and a thick layer. The thick layer includes a plurality of insulating stripes that are separated from each other and that extend across a length between the source and the drain regions. The plate structure is located between the source and the drain regions, wherein the plate structure is located on the thin layer and portions of the thick layer, the plate structure having one or more conductive bands that are directly over individual ones of the plurality of insulating stripes.