With Layered Structures With Quantum Effects In Vertical Direction (epo) Patents (Class 257/E29.076)
  • Patent number: 8633092
    Abstract: An apparatus includes a primary planar quantum well and a planar distribution of dopant atoms. The primary planar quantum well is formed by a lower barrier layer, a central well layer on the lower barrier layer, and an upper barrier layer on the central well layer. Each of the layers is a semiconductor layer. One of the barrier layers has a secondary planar quantum well and is located between the planar distribution of dopant atoms and the central well layer. The primary planar quantum well may be undoped or substantially undoped, e.g., intrinsic semiconductor.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: January 21, 2014
    Assignee: Alcatel Lucent
    Inventors: Kirk William Baldwin, Loren N. Pfeiffer, Kenneth William West
  • Patent number: 8471268
    Abstract: There is provided a light emitting device of a simpler structure, capable of ensuring a broad light emitting area and a high light emitting efficiency, while manufactured in a simplified and economically efficient process. The light emitting device including: a semiconductor layer; an active layer formed on the semiconductor layer, the active layer comprising at least one of a quantum well structure, a quantum dot and a quantum line; an insulating layer formed on the active layer; and a metal layer formed on the insulating layer.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: June 25, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won Ha Moon, Chang Hwan Choi, Dong Woohn Kim, Hyun Jun Kim
  • Patent number: 8421058
    Abstract: A light emitting diode structure and a method of forming a light emitting diode structure are provided. The structure includes a superlattice comprising, a first barrier layer; a first quantum well layer comprising a first metal-nitride based material formed on the first barrier layer; a second barrier layer formed on the first quantum well layer; and a second quantum well layer including the first metal-nitride based material formed on the second barrier layer; and wherein a difference between conduction band energy of the first quantum well layer and conduction band energy of the second quantum well layer is matched to a single or multiple longitudinal optical phonon energy for reducing electron kinetic energy in the superlattice.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: April 16, 2013
    Assignee: Agency for Science, Technology and Research
    Inventors: Wei Liu, Chew Beng Soh, Soo Jin Chua, Jing Hua Teng
  • Patent number: 8362461
    Abstract: An apparatus includes a primary planar quantum well and a planar distribution of dopant atoms. The primary planar quantum well is formed by a lower barrier layer, a central well layer on the lower barrier layer, and an upper barrier layer on the central well layer. Each of the layers is a semiconductor layer. One of the barrier layers has a secondary planar quantum well and is located between the planar distribution of dopant atoms and the central well layer. The primary planar quantum well may be undoped or substantially undoped, e.g., intrinsic semiconductor.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: January 29, 2013
    Assignee: Alcatel Lucent
    Inventors: Kirk William Baldwin, Loren N. Pfeiffer, Kenneth William West
  • Patent number: 8247793
    Abstract: Provided are a ZnO-based thin film and a ZnO-based semiconductor device which allow: reduction in a burden on a manufacturing apparatus; improvement of controllability and reproducibility of doping; and obtaining p-type conduction without changing a crystalline structure. In order to be formed into a p-type ZnO-based thin film, a ZnO-based thin film is formed by employing as a basic structure a superlattice structure of a MgZnO/ZnO super lattice layer 3. This superlattice component is formed with a laminated structure which includes acceptor-doped MgZnO layers 3b and acceptor-doped ZnO layers 3a. Hence, it is possible to improve controllability and reproducibility of the doping, and to prevent a change in a crystalline structure due to a doping material.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: August 21, 2012
    Assignee: Rohm Co., Ltd.
    Inventors: Ken Nakahara, Shunsuke Akasaka, Masashi Kawasaki, Akira Ohtomo, Atsushi Tsukazaki
  • Patent number: 8202436
    Abstract: Methods for preparing one or more conductive nanostructures are provided. In accordance with one embodiment, a method for preparing one or more conductive nanostructures may include providing a composite of nanoparticles and block copolymer including one or more first microdomains and one or more second microdomains, where conductive nanoparticles are selectively distributed in the one or more first microdomains, removing the first microdomains while leaving the conductive nanoparticles in the composite, forming one or more conductive nanostructures on the conductive nanoparticles, and removing the second microdomains.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: June 19, 2012
    Assignee: Korea University Research and Business Foundation
    Inventor: Kwangyeol Lee
  • Patent number: 8076701
    Abstract: A method of making nanostructures using a self-assembled monolayer of organic spheres is disclosed. The nanostructures include bowl-shaped structures and patterned elongated nanostructures. A bowl-shaped nanostructure with a nanorod grown from a conductive substrate through the bowl-shaped nanostructure may be configured as a field emitter or a vertical field effect transistor. A method of separating nanoparticles of a desired size employs an array of bowl-shaped structures.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: December 13, 2011
    Assignee: Georgia Tech Research Corporation
    Inventors: Zhong L. Wang, Christopher J. Summers, Xudong Wang, Elton D Graugnard, Jeffrey King
  • Patent number: 8076740
    Abstract: A photo detector is provided with a plurality of quantum dot layers and first conductive type contact layers provided at both sides of the plurality of quantum dot layers so as to sandwich them; a second conductive type impurity is doped in a first semiconductor layer formed between one first conductive type contact layer and a first quantum dot layer which is closest to the one first conductive type contact layer so that it results in a barrier against a carrier positioned at the one first conductive contact layer.
    Type: Grant
    Filed: June 14, 2006
    Date of Patent: December 13, 2011
    Assignee: Fujitsu Limited
    Inventors: Yasuhito Uchiyama, Hironori Nishino
  • Patent number: 8030664
    Abstract: There is provided a light emitting device of a simpler structure, capable of ensuring a broad light emitting area and a high light emitting efficiency, while manufactured in a simplified and economically efficient process. The light emitting device including: a semiconductor layer; an active layer formed on the semiconductor layer, the active layer comprising at least one of a quantum well structure, a quantum dot and a quantum line; an insulating layer formed on the active layer; and a metal layer formed on the insulating layer.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: October 4, 2011
    Assignee: Samsung LED Co., Ltd.
    Inventors: Won Ha Moon, Chang Hwan Choi, Dong Woohn Kim, Hyun Jun Kim
  • Patent number: 7977666
    Abstract: The present invention is disclosed that a device capable of normal incident detection of infrared light to efficiently convert infrared light into electric signals. The device includes a substrate, a first contact layer formed on the substrate, an active layer formed on the first contact layer, a barrier layer formed on the active layer and a second contact layer formed on the barrier layer, wherein the active layer includes multiple quantum dot layers.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: July 12, 2011
    Assignee: Academia Sinica
    Inventors: Shiang-Yu Wang, Hong-Shi Ling, Ming-Cheng Lo, Chien-Ping Lee
  • Patent number: 7875876
    Abstract: Described is a scalable quantum computer that includes at least two classical to quantum interface devices, with each being connected to a distinct quantum processing unit (QPU). An Einstein-Podolsky-Rosen pair generator (EPRPG) is included for generating an entangled Einstein-Podolsky-Rosen pair that is sent to the QPUs. Each QPU is quantumly connected with the EPRPG and is configured to receive a mobile qubit from the EPRPG and perform a sequence of operations such that the mobile qubit interacts with a source qubit when a teleportation algorithm is initiated, leaving a second mobile qubit in the original quantum state of the source qubit.
    Type: Grant
    Filed: June 15, 2006
    Date of Patent: January 25, 2011
    Assignee: HRL Laboratories, LLC
    Inventors: Stephen Wandzura, Mark F. Gyure, Bryan Ho Lim Fong
  • Patent number: 7820998
    Abstract: A device and method for manipulating a direction of motion of current carriers are presented. The device comprises a structure containing a two-dimensional gas of current carriers configured to define at least one region of inhomogeneity which is characterized by a substantially varying value of at least one parameter from the following: a spin-orbit coupling constant, density of the spin carriers, and a mobility of the gas. The device may be configured and operable to perform spin manipulation of a flux of the spin carrying current carriers to provide at least one of the following types of deviation of said spin-carrying current carriers: spin dependent refraction, spin dependent reflection and spin dependent diffraction on desired deviation angles of a direction of motion of the spin-carrying current carriers being incident on said at least one region of inhomogeneity.
    Type: Grant
    Filed: January 9, 2005
    Date of Patent: October 26, 2010
    Assignee: Yeda Research and Development Ltd.
    Inventors: Alexander Finkelstein, Maxim Khodas, Arcadi Shehter
  • Patent number: 7781754
    Abstract: The Bell-state analyzer includes a semiconductor device having quantum dots formed therein and adapted to support Fermions in a spin-up and/or spin-down states. Different Zeeman splittings in one or more of the quantum dots allows resonant quantum tunneling only for antiparallel spin states. This converts spin parity into charge information via a projective measurement. The measurement of spin parity allows for the determination of part of the states of the Fermions, which provides the states of the qubits, while keeping the undetermined part of the state coherent. The ability to know the parity of qubit states allows for logic operations to be performed on the qubits, i.e., allows for the formation of (two-qubit) quantum gates, which like classical logic gates, are the building blocks of a quantum computer. Quantum computers that perform a parity gate and a CNOT gate using the Bell-state analyzer of the invention are disclosed.
    Type: Grant
    Filed: July 9, 2007
    Date of Patent: August 24, 2010
    Assignee: MagiQ Technologies, Inc.
    Inventors: Daniel Loss, Hans-Andreas Engel
  • Patent number: 7700936
    Abstract: In one embodiment, a method of producing an optoelectronic nanostructure includes preparing a substrate; providing a quantum well layer on the substrate; etching a volume of the substrate to produce a photonic crystal. The quantum dots are produced at multiple intersections of the quantum well layer within the photonic crystal. Multiple quantum well layers may also be provided so as to form multiple vertically aligned quantum dots. In another embodiment, an optoelectronic nanostructure includes a photonic crystal having a plurality of voids and interconnecting veins; a plurality of quantum dots arranged between the plurality of voids, wherein an electrical connection is provided to one or more of the plurality of quantum dots through an associated interconnecting vein.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: April 20, 2010
    Assignee: University of Delaware
    Inventors: Janusz Murakowski, Garrett Schneider, Dennis W. Prather
  • Patent number: 7696536
    Abstract: A method for enhancing operation of a bipolar light-emitting transistor includes the following steps: providing a bipolar light-emitting transistor having emitter, base, and collector regions; providing electrodes for coupling electrical signals with the emitter, base, and collector regions; and adapting the base region to promote carrier transport from the emitter region toward the collector region by providing, in the base region, several spaced apart quantum size regions of different thicknesses, with the thicknesses of the quantum size regions being graded from thickest near the collector to thinnest near the emitter.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: April 13, 2010
    Assignee: The Board of Trustees of The University of Illinois
    Inventors: Milton Feng, Nick Holonyak, Jr.
  • Patent number: 7692180
    Abstract: Quantum dots are positioned within a layered composite film to produce a plurality of real-time programmable dopants within the film. Charge carriers are driven into the quantum dots by energy in connected control paths. The charge carriers are trapped in the quantum dots through quantum confinement, such that the charge carriers form artificial atoms, which serve as dopants for the surrounding materials. The atomic number of each artificial atom is adjusted through precise variations in the voltage across the quantum dot that confines it. The change in atomic number alters the doping characteristics of the artificial atoms. The layered composite film is also configured as a shift register.
    Type: Grant
    Filed: June 3, 2005
    Date of Patent: April 6, 2010
    Assignee: RavenBrick LLC
    Inventors: Gary E. Snyder, Wil McCarthy
  • Publication number: 20100051904
    Abstract: A method of fabricating a device includes: providing a substrate having a patterned surface, depositing a first-level self-assembled material on at least a portion of the patterned surface, wherein the position and/or orientation of the first-level self-assembled material is directed by the patterned surface, to form a first nanostructure pattern, and depositing a second-level self-assembled material on at least a portion of the first nanostructure pattern to form an array of nanostructures of the second-level self-assembled material. An apparatus fabricated using the method is also provided.
    Type: Application
    Filed: September 4, 2008
    Publication date: March 4, 2010
    Applicant: Seagate Technology LLC
    Inventors: Shuaigang Xiao, Xiaomin Yang
  • Patent number: 7662659
    Abstract: The invention is a method of producing an array, or multiple arrays of quantum dots. Single dots, as well as two or three-dimensional groupings may be created. The invention involves the transfer of quantum dots from a receptor site on a substrate where they are originally created to a separate substrate or layer, with a repetition of the process and a variation in the original pattern to create different structures.
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: February 16, 2010
    Assignee: Banpil Photonics, Inc.
    Inventors: Nobuhiko P. Kobayashi, Achyut Kumar Dutta
  • Patent number: 7501649
    Abstract: A sensor chip includes a layer-shaped base body, which has a plurality of fine holes formed in one surface, and fine metal particles, each of which is loaded in one of the fine holes of the base body. At least a part of each of the fine metal particles is exposed to a side of the layer-shaped base body, which side is more outward than the one surface of the layer-shaped base body. The layer-shaped base body may be constituted of anodic oxidation alumina. The sensor chip constitutes a sensor utilizing localized plasmon resonance, with which a state of binding of a sensing medium with a specific substance is capable of being detected quickly and with a high sensitivity.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: March 10, 2009
    Assignee: FUJIFILM Corporation
    Inventors: Masayuki Naya, Atsushi Mukai
  • Publication number: 20080298415
    Abstract: A semiconductor device having high reliability, a long lifetime and superior light emitting characteristics by applying a novel material to a p-type cladding layer is provided. A semiconductor device includes a p-type semiconductor layer on an InP substrate, in which the p-type semiconductor layer has a laminate structure formed by alternately laminating a first semiconductor layer mainly including Bex1Mgx2Znx3Te (0<x1<1, 0<x2<1, 0<x3<1, x1+x2+x3=1) and a second semiconductor layer mainly including Bex4Mgx5Znx6Te (0<x4<1, 0<x5<1, 0<x6<1, x4+x5+x6=1).
    Type: Application
    Filed: June 3, 2008
    Publication date: December 4, 2008
    Applicants: SONY CORPORATION, HITACHI, LTD, SOPHIA SCHOOL CORPORATION
    Inventors: Katsumi Kishino, Ichiro Nomura, Koshi Tamamura, Kunihiko Tasai, Tsunenori Asatsuma, Hitoshi Nakamura, Sumiko Fujisaki, Takeshi Kikawa
  • Publication number: 20080283823
    Abstract: A gallium-nitride-based semiconductor stacked structure includes a sapphire substrate; a low temperature-deposited buffer layer which is composed of a Group III nitride material of AlxGayN (0.5<Y?1, X+Y=1) containing gallium (Ga) in a predominant amount with respect to aluminum (Al), which has been grown at low temperature and which is provided in a junction area thereof joined to a (0001) plane (c-plane) of the sapphire substrate with a single crystal in an as-grown state; and a gallium-nitride (GaN)-based semiconductor layer formed on the low-temperature-deposited buffer layer. The low-temperature-deposited buffer layer is predominantly composed of an as-grown single crystal which has a [1.0.-1.0.] orientation parallel to a [2.-1.1.0.] direction of a lattice forming a (0001) basal plane of the sapphire substrate.
    Type: Application
    Filed: June 9, 2005
    Publication date: November 20, 2008
    Applicant: SHOWA DENKO K.K.
    Inventor: Takashi Udagawa
  • Publication number: 20080258134
    Abstract: A semiconductor device may include a semiconductor substrate having a surface, a shallow trench isolation (STI) region in the semiconductor substrate and extending above the surface thereof, and a superlattice layer adjacent the surface of the semiconductor substrate and comprising a plurality of stacked groups of layers. More particularly, each group of layers of the superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Moreover, at least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.
    Type: Application
    Filed: April 14, 2008
    Publication date: October 23, 2008
    Applicant: MEARS Technologies, Inc.
    Inventors: Robert J. Mears, Kalipatnam Vivek Rao
  • Publication number: 20080203382
    Abstract: A main semiconductor region of semiconducting nitrides is formed on a silicon substrate via a buffer region of semiconducting nitrides to provide devices such as HEMTs, MESFETs and LEDs. In order to render the wafer proof against warping, the buffer region is divided into a first and a second multilayered buffer subregion. The first buffer subregion comprises multiple alterations of a multi-sublayered first buffer layer and a non-sublayered second buffer layer. Each multi-sublayered first buffer layer of the first buffer subregion comprises multiple alternations of a first and a second buffer sublayer. The second buffer sublayers of each multi-sublayered first buffer layer either do not contain aluminum or do contain it in a higher proportion than do the first buffer sublayers. The second multilayered buffer subregion comprises multiple alternations of a first and a second buffer layer.
    Type: Application
    Filed: February 27, 2008
    Publication date: August 28, 2008
    Applicant: SANKEN ELECTRIC CO., LTD.
    Inventor: Masataka Yanagihara
  • Publication number: 20080191195
    Abstract: According to the nitride semiconductor device with the active layer made of the multiple quantum well structure of the present invention, the performance of the multiple quantum well structure can be brought out to intensify the luminous output thereof thereby contributing an expanded application of the nitride semiconductor device.
    Type: Application
    Filed: March 12, 2008
    Publication date: August 14, 2008
    Applicant: NICHIA CORPORATION
    Inventors: Koji TANIZAWA, Tomotsugu MITANI, Yoshinori NAKAGAWA, Hironori TAKAGI, Hiromitsu MARUI, Yoshikatsu FUKUDA, Takeshi IKEGAMI
  • Patent number: 7405422
    Abstract: A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitaxial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon <1020 cm?3, the as-grown p- or n-type dopant profile can withstand furnace anneals to temperatures of 850° C. and rapid thermal anneal temperatures to 1000° C.
    Type: Grant
    Filed: December 30, 2006
    Date of Patent: July 29, 2008
    Assignee: International Business Machines Corporation
    Inventors: Jack O. Chu, Basanth Jaqannathan, Alfred Grill, Bernard S. Meyerson, John A Ott
  • Publication number: 20080025360
    Abstract: The semiconductor layer structure comprises a superlattice (9) composed of alternately stacked layers (9a, 9b) of III-V semiconductor compounds of a first composition (a) and at least one second composition (b). The layers (9a, 9b) of the superlattice (9) contain dopants in predetermined concentrations, with regard to which the concentrations of the dopants are different at least two layers of a same composition in the superlattice (9), the concentration of the dopants is graded within at least one layer (9a, 9b) of the superlattice (9), and the superlattice (9) comprises layers that are doped with different dopants or comprise at least one layer (9a, 9b) that is undoped. The electrical and optical properties of the superlattice (9) can be adapted to given requirements in the best possible manner in this way.
    Type: Application
    Filed: July 20, 2007
    Publication date: January 31, 2008
    Inventors: Christoph Eichler, Alfred Lell
  • Patent number: 7183602
    Abstract: Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (CFE) from hydrogen diffusion in semiconductor devices (102), wherein nitrided aluminum oxide (N—AlOx) is formed over a ferroelectric capacitor (CFE), and one or more silicon nitride layers (112, 117) are formed over the nitrided aluminum oxide (N—AlOx). Hydrogen barriers are also provided in which an aluminum oxide (AlOx, N—AlOx) is formed over the ferroelectric capacitors (CFE), with two or more silicon nitride layers (112, 117) formed over the aluminum oxide (AlOx, N—AlOx), wherein the second silicon nitride layer (112) comprises a low silicon-hydrogen SiN material.
    Type: Grant
    Filed: January 11, 2005
    Date of Patent: February 27, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: K. R. Udayakumar, Theodore S. Moise, Scott R. Summerfelt
  • Patent number: RE41427
    Abstract: Hybrid crystalline organic-inorganic quantum confined systems are disclosed, which contain alternating layers of a bifunctional organic ligand and a II-VI semiconducting chalcogenide, wherein the semiconducting chalcogenide layers contain chalcogenides have the formula MQ, in which M is independently selected from II-VI semiconductor cationic species and Q is independently selected from S, Se and Te; and the bifunctional organic ligands of each organic ligand layer are bonded by a first functional group to an element M of an adjacent II-VI semiconducting chalcogenide layer and by a second functional group to an element M from the adjacent opposing II-VI semiconducting chalcogenide layer, so that the adjacent opposing II-VI semiconducting chalcogenide layers are linked by the bifunctional organic ligands of the organic ligand layers. Optical absorption experiments show that these systems produce a significant blue shift in their optical absorption edges, 1.2-1.5 eV, compared to a shift of 1.
    Type: Grant
    Filed: May 13, 2005
    Date of Patent: July 13, 2010
    Assignee: Rutgers, The State University
    Inventors: Jing Li, Xiaoying Huang