Abstract: Semiconductor materials including a gallium nitride material region and methods associated with such structures are provided. The semiconductor structures include a strain-absorbing layer formed within the structure. The strain-absorbing layer may be formed between the substrate (e.g., a silicon substrate) and an overlying layer. It may be preferable for the strain-absorbing layer to be very thin, have an amorphous structure and be formed of a silicon nitride-based material. The strain-absorbing layer may reduce the number of misfit dislocations formed in the overlying layer (e.g., a nitride-based material layer) which limits formation of other types of defects in other overlying layers (e.g., gallium nitride material region), amongst other advantages. Thus, the presence of the strain-absorbing layer may improve the quality of the gallium nitride material region which can lead to improved device performance.

Abstract: Aspects of the disclosure provide a method of inhibiting crack propagation in a silicon wafer. In one embodiment, a method of repairing an imperfection on a surface of a semiconductor device is disclosed. The method includes: screening for imperfections on a surface of a silicon wafer of a semiconductor device; and in response to at least one imperfection on the surface of the silicon wafer, depositing a material on the surface of the silicon wafer.

Abstract: The invention relates to a method for texturing the surface of a gaseous phase silicon substrate, and to a textured silicon substrate for a solar cell. The method includes at least a step a) of exposing the surface to an SF6/O2 radiofrequency plasma for a duration of 2 to 30 minutes in order to produce a silicon substrate having a textured surface having pyramidal structures, the SF6/O2 ratio being 2 to 10. During step a) the power density generated using the radiofrequency plasma is greater than or equal to 2500 mW/cm2, and the SF6/O2 pressure in the reaction chamber is lower than or equal to 100 mTorrs, so as to produce a silicon substrate having a textured surface having inverted pyramidal structures.

Abstract: A semiconductor device includes CMP dummy tiles (36) that are converted to active tiles by forming well regions (42) at a top surface of the dummy tiles, forming silicide (52) on top of the well regions, and forming a metal interconnect structure (72, 82) in contact with the silicided well tie regions for electrically connecting the dummy tiles to a predetermined supply voltage to provide latch-up protection.

Abstract: The invention includes a dielectric mode from ALD-type methods in which two or more different precursors are utilized with one or more reactants to form the dielectric material. In particular aspects, the precursors are aluminum and hafnium and/or zirconium for materials made from a hafnium precursor, the hafnium oxide is predominantly in a tetragonal crystalline phase.

Abstract: Various methods and apparatuses involving salt-based compounds and related doping are provided. In accordance with one or more embodiments, a salt-based material is introduced to a semiconductor material, is heated to generate a neutral compound that dopes the semiconductor material. Other embodiments are directed to semiconductor materials with such a neutral compound as an impurity that affects electrical characteristics therein.

Abstract: There is provided a thermal treatment method of a silicon wafer. The method includes the successive steps of: (a) terminating silicon atoms existing on an active surface of the silicon wafer with hydrogen, wherein the active surface is mirror-polished, and a semiconductor device is to be formed on the active surface; (b) terminating the silicon atoms existing on the active surface of the silicon wafer with fluorine; (c) rapidly heating the silicon wafer to a first temperature under an inert gas atmosphere or a reducing gas atmosphere, wherein the first temperature is in a range of 1300° C. to 1400° C.; (d) holding the silicon wafer at the first temperature for a certain time; and (e) rapidly cooling the silicon wafer.

Abstract: A method for manufacturing a solar cell from a semiconductor substrate (1) of a first conductivity type, the semiconductor substrate having a front surface (2) and a back surface (3). The method includes in a sequence: texturing (102) the front surface to create a textured front surface (2a); creating (103) by diffusion of a dopant of the first conductivity type a first conductivity-type doped layer (2c) in the textured front surface and a back surface field layer (4) of the first conductivity type in the back surface; removing (105; 104a) the first conductivity-type doped layer from the textured front surface by an etching process adapted for retaining texture of the textured front surface; creating (106) a layer of a second conductivity type (6) on the textured front surface by diffusion of a dopant of the second conductivity type into the textured front surface.

Abstract: The invention relates to a method for texturing the surface of a gaseous phase silicon substrate, and to a textured silicon substrate for a solar cell. The method includes at least a step a) of exposing the surface to an SF6/O2 radiofrequency plasma for a duration of 2 to 30 minutes in order to produce a silicon substrate having a textured surface having pyramidal structures, the SF6/O2 ratio being 2 to 10. During step a) the power density generated using the radiofrequency plasma is greater than or equal to 2500 mW/cm2, and the SF6/O2 pressure in the reaction chamber is lower than or equal to 100 mTorrs, so as to produce a silicon substrate having a textured surface having inverted pyramidal structures.

Abstract: A method for fabricating semiconductor components includes the steps of providing a semiconductor substrate having a circuit side, a back side and integrated circuits and circuitry on the circuit side; thinning the substrate from the back side to a selected thickness; laser processing the back side of the thinned substrate to form at least one lasered feature on the back side; and dicing the substrate into a plurality of components having the lasered feature. The lasered feature can cover the entire back side or only selected areas of the back side, and can be configured to change electrical properties, mechanical properties or gettering properties of the substrate. A semiconductor component includes a thinned semiconductor substrate having a back side and a circuit side containing integrated circuits and associated circuitry. The semiconductor component also includes at least one lasered feature on the back side configured to provide selected electrical or physical characteristics for the substrate.

Abstract: The invention relates to a new method of texturing silicon surfaces suited for antireflection based on ion implantation of hydrogen and heavy ions or heavy elements combined with thermal annealing or thermal annealing and oxidation. The addition of the heavy ions or heavy elements allows for a more effective anti-reflective surface than is found when only hydrogen implantation is utilized. The methods used are also time- and cost-effective, as they can utilize already existing semiconductor ion implantation fabrication equipment and reduce the number of necessary steps. The antireflective surfaces are useful for silicon-based solar cells.

Abstract: This invention is to provide a method of polishing a silicon wafer wherein a high flatness can be attained likewise the conventional polishing method and further the occurrence of defects due to the remaining of substances included in the polishing solution on the surface of the wafer can be suppressed as well as a polished silicon wafer. The method of polishing a silicon wafer by supplying a polishing solution containing abrasive grains onto a surface of a polishing pad and then relatively sliding the polishing pad to a silicon wafer to polish the surface of the silicon wafer, is characterized in that the number of abrasive grains included in the polishing solution is controlled to not more than 5×1013 grains/cm3.

Abstract: A method of manufacturing a semiconductor device includes steps of providing a substrate including a semiconductor portion, a non-porous semiconductor layer, and a porous semiconductor layer arranged between the semiconductor portion and the non-porous semiconductor layer, forming a porous oxide layer by oxidizing the porous semiconductor layer, forming a bonded substrate by bonding a supporting substrate to a surface, on a side of the non-porous semiconductor layer, of the substrate on which the porous oxide layer is formed, and separating the semiconductor portion from the bonded substrate by utilizing the porous oxide layer.

Abstract: A semiconductor epitaxial substrate includes: a single crystal substrate; an AlN layer epitaxially grown on the single crystal substrate; and a nitride semiconductor layer epitaxially grown on the AN layer, wherein an interface between the AlN layer and nitride semiconductor layer has a larger roughness than an interface between the single crystal substrate and AlN layer, and a skewness of the upper surface of the AlN layer is positive.

Abstract: A method is provided that allows for maintaining a desired equivalent oxide thickness (EOT) by reducing the thickness of an interfacial layer in a gate structure. An interfacial layer is formed on a substrate, a gate dielectric layer such as, a high-k gate dielectric, is formed on the interfacial layer. A gettering layer is formed on the substrate overlying the interfacial layer. The gettering layer may function to getter oxygen from the interfacial layer such that the interfacial layer thickness is decreased and/or restricted from growth.

Abstract: A polishing method for a heterostructure of at least one relaxed superficial heteroepitaxial layer on a substrate made of a different material. The method includes a first chemical mechanical polishing step of the surface of the heteroepitaxial layer performed with a polishing cloth having a first compressibility ratio and with a polishing solution having a first silica particle concentration. The first chemical mechanical polishing step is followed by a second chemical mechanical polishing step of the surface of the heteroepitaxial layer, with the second step being performed with a polishing cloth having a second compressibility ratio, higher than the first compressibility ratio, and with a polishing solution having a second silica particle concentration, lower than the first concentration. By this method, improved surface roughness is achieved.

Abstract: The present invention generally provides semiconductor substrates having submicron-sized surface features generated by irradiating the surface with ultra short laser pulses. In one aspect, a method of processing a semiconductor substrate is disclosed that includes placing at least a portion of a surface of the substrate in contact with a fluid, and exposing that surface portion to one or more femtosecond pulses so as to modify the topography of that portion. The modification can include, e.g., generating a plurality of submicron-sized spikes in an upper layer of the surface.

Abstract: The invention relates to a design structure, and more particularly, to a design structure for a conductive liner for rad hard total dose immunity and a structure thereof. The structure includes at least one shallow trench isolation structure having oxide material and formed in an SOI. A dielectric liner is formed at an interface of the SOI within the at least one shallow trench isolation structure. A metal or metal alloy layer is formed in the at least one shallow trench isolation structure and between the dielectric liner and the oxide material.

Abstract: A method for fabricating semiconductor components includes the steps of providing a semiconductor substrate having a circuit side, a back side and integrated circuits and circuitry on the circuit side; thinning the substrate from the back side to a selected thickness; laser processing the back side of the thinned substrate to form at least one lasered feature on the back side; and dicing the substrate into a plurality of components having the lasered feature. The lasered feature can cover the entire back side or only selected areas of the back side, and can be configured to change electrical properties, mechanical properties or gettering properties of the substrate. A semiconductor component includes a thinned semiconductor substrate having a back side and a circuit side containing integrated circuits and associated circuitry. The semiconductor component also includes at least one lasered feature on the back side configured to provide selected electrical or physical characteristics for the substrate.

Abstract: Methods of forming microelectronic device wafers include fabricating a plurality of semiconductor dies at an active side of a semiconductor wafer, depositing a mask on the semiconductor wafer, removing a central portion of the mask and the semiconductor wafer, and etching. The semiconductor wafer has an outer perimeter edge and a backside that is spaced from the active side by a first thickness. The mask is deposited on the backside of the semiconductor wafer and has a face that is spaced from the backside by a mask thickness. The thinned portion has a thinned surface that is spaced from the active side by a second thickness that is less than the first thickness, and the thinned surface is etched.

Abstract: In one embodiment, a multi-layer extrinsic gettering structure includes plurality of polycrystalline semiconductor layers each separated by a dielectric layer.

Abstract: The present invention provides a final polishing method for a silicon single crystal wafer that performs final polishing with a polishing rate being set to 10 nm/min or below at a final polishing step as a final step among a plurality of polishing steps for polishing the silicon single crystal wafer with a polishing slurry being interposed between the silicon single crystal wafer and a polishing pad, and a silicon single crystal wafer subjected to final polishing by this method. Hereby, there can be provided the final polishing method that can obtain a silicon single crystal wafer with less PIDs (Polishing Induced Defects) and the silicon single crystal wafer subjected to final polishing by this method.

Abstract: The present invention provides a manufacturing method of a high performance active matrix substrate at a high throughput with a less expensive apparatus, and an image display device using the active matrix substrate. On a stage moving in the short axis direction X and long axis direction Y on a rail, a glass substrate is carried, which has an amorphous silicon semiconductor film formed. Polycrystallized and large grain silicon film may be obtained by intensity modulating the pulsed laser beam in a line beam shape by means of a phase shift mask with a periodicity in the long axis direction Y of the laser beam, moving the laser beam randomly in the modulation direction of the amorphous silicon semiconductor film formed on the glass substrate to expose to crystallize the film. The image display device may incorporate an active matrix substrate having active elements such as thin film transistors formed by this silicon film.

Abstract: A device and a device manufacturing process. First, a gettering layer is formed on the bottom surface of a silicon substrate. Gates having a MOS structure are then formed on the principal surface of the silicon substrate, and the gettering layer is removed. According to this manufacturing method, the formation of the gates having a MOS structure is performed such that the gettering layer getters dissolved oxygen present in the silicon substrate. This reduces the concentration of dissolved oxygen in the silicon substrate, resulting in improved device characteristics.

Abstract: A method of manufacturing a thin silicon wafer by slicing a silicon single crystal includes: a thinning step S3 of polishing a rear surface of the silicon wafer to reduce the thickness of the silicon wafer after a device structure is formed on a front surface of the silicon wafer; a mirror surface forming step S4 of processing the rear surface of the silicon wafer into a mirror surface using a chemical mechanical polishing method; and a modifying step S5 of dispersing abrasive grains that are harder than those used to form the mirror surface in the mirror surface forming process and forming a damaged layer, serving as a gettering sink for heavy metal, on the rear surface of the silicon wafer using the chemical mechanical polishing method. The thickness T5b of the damaged layer W5b in a wafer depth direction is set by the chemical mechanical polishing method in the modifying step S5 to control the gettering capability of the damaged layer.

Abstract: A method of manufacturing an ultra thin integrated circuit comprises providing a substrate having a front side, a back side, and an edge extending from the front side to the back side; creating a defect layer in the substrate; forming semiconductor devices proximate the front side after creating the defect layer; and cleaving proximate the defect layer after forming the semiconductor devices. Other methods and apparatus are also provided.

Abstract: A method for manufacturing a device includes mapping extreme vertical boundary conditions of a mask layer based on vertical edges of a deposited first layer and a second layer. The mask layer is deposited over portions of the second layer based on the mapping step. The exposed area of the second layer is etched to form a smooth boundary between the first layer and the second layer. The resist layer is stripped. The resulting device is an improved PFET device and NFET device with a smooth boundary between the first and second layers such that a contact can be formed at the smooth boundary without over etching other areas of the device.

Abstract: A wafer, in which a plurality of rectangular regions are defined on the face of the wafer by streets arranged in a lattice pattern, and a semiconductor memory element is disposed in each of the rectangular regions, is divided along the streets to separate the rectangular regions individually, thereby forming a plurality of semiconductor devices. Before the wafer is divided along the streets, a strained layer having a thickness of 0.20 ?m or less, especially 0.05 to 0.20 ?m, is formed in the back of the wafer. The strained layer is formed by grinding the back of the semiconductor wafer by a grinding member formed by bonding diamond abrasive grains having a grain size of 4 ?m or less by a bonding material.

Abstract: The present invention provides a semiconductor structure that includes a high performance field effect transistor (FET) on a semiconductor-on-insulator (SOI) in which the insulator thereof is a stress-inducing material of a preselected geometry. Such a structure achieves performance enhancement from uniaxial stress, and the stress in the channel is not dependent on the layout design of the local contacts. In broad terms, the present invention relates to a semiconductor structure that comprises an upper semiconductor layer and a bottom semiconductor layer, wherein said upper semiconductor layer is separated from said bottom semiconductor layer in at least one region by a stress-inducing insulator having a preselected geometric shape, said stress-inducing insulator exerting a strain on the upper semiconductor layer.

Abstract: A method of preventing the formation of cracks on the backside of a silicon (Si) semiconductor chip or wafer during the processing thereof. Also provided is a method for inhibiting the propagation of cracks, which have already formed in the backside of a silicon chip during the processing thereof and prior to the joining thereto of a substrate during the fabrication of an electronic package. The methods entail either treating the backside with a wet etch, or alternatively, applying a protective film layer thereon prior to forming an electronic package incorporating the chip or wafer.