Characterized By Relative Position Of Source Or Drain Electrode And Gate Electrode (epo) Patents (Class 257/E29.122)
  • Patent number: 7332754
    Abstract: In the semiconductor switch of the present invention, the gate electrode, source electrode and drain electrode are formed such that the distance between the gate and the drain of an MESFET, assuming a shunt FET, is longer than the distance between the gate and the drain of an MESFET, assuming a through FET, so that the gate breakdown voltage of the MESFET, assuming a shunt FET, is increased without changing the gate breakdown voltage of the MESFET, assuming a through FET.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: February 19, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takashi Uno, Manabu Yanagihara, Hidetoshi Ishida, Tsuyoshi Tanaka
  • Patent number: 7298011
    Abstract: A semiconductor device with a recessed L-shaped spacer and a method for fabricating the same. A recessed L-shaped spacer includes a vertical portion and a horizontal portion. The vertical portion is disposed on lower sidewalls of a conductor pattern, exposing upper sidewalls thereof. A top spacer is on the L-shaped spacer, wherein a width ratio of the vertical portion of the L-shaped spacer to the top spacer is at least about 2:1.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: November 20, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kong-Beng Thei, Chung-Long Cheng, Harry Chuang
  • Publication number: 20070200184
    Abstract: A power metal-oxide-semiconductor field effect transistor (MOSFET) (100) incorporates a stepped drift region including a shallow trench insulator (STI) (112) partially overlapped by the gate (114) and which extends a portion of the distance to a drain region (122). A silicide block extends from and partially overlaps STI (112) and drain region (122). The STI (112) has a width that is approximately 50% to 75% of the drift region.
    Type: Application
    Filed: February 24, 2006
    Publication date: August 30, 2007
    Inventors: Ronghua Zhu, Amitava Bose, Vishnu Khemka, Todd Roggenbauer
  • Patent number: 7229892
    Abstract: A method of manufacturing a semiconductor device, includes preparing a semiconductor substrate, bonding a first semiconductor layer onto a part of the semiconductor substrate with a first insulating layer interposed therebetween, forming a second insulating layer on a side of the first semiconductor layer, epitaxially growing a second semiconductor layer in a region on the semiconductor substrate other than a region formed with the first insulating layer, forming a first semiconductor element in the first semiconductor layer on the first insulating layer, and forming a second semiconductor element in the second semiconductor layer on the second insulating layer.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: June 12, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Usuda, Shinichi Takagi
  • Publication number: 20060170066
    Abstract: A semiconductor device (51) is provided herein. The semiconductor device comprises (a) a substrate (57), a semiconductor layer (53) disposed on said substrate and comprising a horizontal region (54) and a fin which extends above, and is disposed adjacent to, said horizontal region, and (c) at least one channel region (63) defined in said fin and in said horizontal region.
    Type: Application
    Filed: January 31, 2005
    Publication date: August 3, 2006
    Inventors: Leo Mathew, Jerry Fossum