Abstract: Provided is a semiconductor device in which on-resistance is largely reduced. The semiconductor device includes an n type epitaxial layer in which each region between neighboring trenches becomes a channel, and a plurality of embedded electrodes each of which is formed on an inner surface of each trench via a silicon oxide film. By blocking each region between neighboring trenches with every depletion layer formed around each of trenches, current flowing through each region between the neighboring trenches is interrupted. By deleting every depletion layer formed around each of the trenches, current can flow through each region between the neighboring trenches.

Abstract: Provided is a semiconductor device including a substrate, and a first wiring layer, a second wiring layer, and a switch via formed on the substrate. The first wiring layer has first wiring formed therein and the second wiring layer has second wiring formed therein. The switch via connects the first wiring and the second wiring. The switch via includes at least at its bottom a switch element including a resistance change layer. A resistance value of the resistance change layer changes according to a history of an electric field applied thereto.

Abstract: A stepwise capacitor structure includes at least one stepwise conductive layer. The stepwise capacitor represents a feature of multiple capacitors. When currents flow through the stepwise capacitor, different current paths are presented in between an upper conductor and a bottom conductor of the stepwise capacitor in response to different current frequency; different inductor is induced in each path and decoupled by a stepwise capacitor structure as disclosed herein.

Abstract: An electrical device includes a substrate; first and second active areas; first and second word lines disposed in a first plane; first and second bit lines in a second plane and in electrical communication with first and second active areas; and a reference line disposed in a third plane. A nanotube element disposed in a fourth plane is in electrical communication with first and second active areas and the reference line via electrical connections at a first surface of the nanotube element. The nanotube element includes first and second regions having resistance states that are independently adjustable in response to electrical stimuli, wherein the first and second regions nonvolatilely retain the resistance states. Arrays of such electrical devices can be formed as nonvolatile memory devices. Methods for fabricating such devices are also disclosed.

Abstract: A process is provided for fabricating rounded three-dimensional germanium active channels for transistors and sensors. For forming sensors, the process comprises providing a crystalline silicon substrate; depositing an oxide mask on the crystalline silicon substrate; patterning the oxide mask with trenches to expose linear regions of the silicon substrate; epitaxially grow germanium selectively in the trenches, seeded from the silicon wafer; optionally etching the SiO2 mask partially, so that the cross section resembles a trapezoid on a stem; and annealing at an elevated temperature. The annealing process forms the rounded channel. For forming transistors, the process further comprises depositing and patterning a gate oxide and gate electrode onto this structure to form the gate stack of a MOSFET device; and after patterning the gate, implanting dopants into the source and drain located on the parts of the germanium cylinder on either side of the gate line.

Abstract: The invention provides a multilayer electronic device having electrodes, formed on a laterally extending first layer, the lateral position of each of at least two adjacent electrodes being defined by a channel in the first layer. Each channel is adjacent a deposition region, the material which forms each electrode substantially covering the deposition region to form a continuous conductive structure.

Abstract: A nonvolatile semiconductor memory device includes floating gates, source areas, drain areas, word lines, diffusion layers, source lines and shield wires. The source area is shared by the floating gates adjacent to each other in a column direction. The drain area faces the source area in the column direction with the floating gate. The drain area is wider than the source area in the column direction. The diffusion layer is formed on an inner wall of a trench made between the source areas adjacent to each other in the same row direction and electrically connects the adjacent source areas together. The source line is formed of the source area and diffusion layer on the same row. The shield wire is disposed on and along the source line. A top surface of the shield wire is lower than that of the floating gate adjacent to the shield wire.

Abstract: An insulated gate bipolar transistor includes a first main electrode on a first main surface and in contact with a base region of an insulated gate transistor at the first main surface, a first semiconductor layer of a first conductivity type on a second main surface, a second semiconductor layer of a second conductivity type on the second main surface and vertically aligned with a region of the first main electrode in contact with the base region, and a second main electrode formed on the first and second semiconductor layers. An interface between the second main electrode and each of the first and second semiconductor layers is parallel to the first main surface, a distance between the first main surface and the interface is equal to 200 ?m or smaller, and a thickness of each of the first and second semiconductor layers is equal to 2 ?m or smaller.

Abstract: A semiconductor device with a field ring in an edge pattern of a semiconductor body with a central cell area and with field plate discharge pattern. The edge pattern exhibits at least one horizontal field plate which is arranged with one end over the field ring and with its other end on insulating layers towards the edge of the semiconductor body. A first ring-shaped area of a type of conduction doped complementary to a drift section material exhibits a field ring effect. A second highly doped ring-shaped area which contacts the one end of the horizontal field plate and forms a pn junction with the first ring-shaped area and which is arranged within the first area exhibits a locally limited punch-through effect or a resistive contact to the drift section material.

Abstract: The present invention provides structures for an integrated antifuse that incorporates an integrated sensing transistor with an integrated heater. Two terminals connected to the upper plate allow the heating of the upper plate, accelerating the breakdown of the antifuse dielectric at a lower bias voltage. Part of the upper plate also serves as the gate of the integrated sensing transistor. The antifuse dielectric serves as the gate dielectric of the integrated transistor. The lower plate comprises a channel, a drain, and a source of a transistor. While intact, the integrated sensing transistor allows a passage of transistor current through the drain. When programmed, the antifuse dielectric, which is the gate of the integrated transistor, is subjected to a gate breakdown, shorting the gate to the channel and resulting in a decreased drain current. The integrated antifuse structure can also be wired in an array to provide a compact OTP memory array.

Abstract: Embodiments of the invention provide memory devices and methods for forming memory devices. In one embodiment, a memory device is provided which includes a floating gate polysilicon layer disposed over source/drain regions of a substrate, a silicon oxynitride layer disposed over the floating gate polysilicon layer, a first aluminum oxide layer disposed over the silicon oxynitride layer, a hafnium silicon oxynitride layer disposed over the first aluminum oxide layer, a second aluminum oxide layer disposed over the hafnium silicon oxynitride layer, and a control gate polysilicon layer disposed over the second aluminum oxide layer. In another embodiment, a memory device is provided which includes a control gate polysilicon layer disposed over an inter-poly dielectric stack disposed over a silicon oxide layer disposed over the floating gate polysilicon layer. The inter-poly dielectric stack contains two silicon oxynitride layers separated by a silicon nitride layer.

Abstract: In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefore for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool.

Abstract: An embodiment of an embedded cache memory in an image sensor comprises a memory cell array wherein the memory cells are substantially isolated from laterally adjacent memory. The memory cell array includes a plurality of memory cells. Each of the memory cells is formed in a standard CMOS image sensor process without the need for SOI processes. Each cell includes first and second n-type and p-type regions arranged around a vertically integrated gate. Data is written to a cell by causing carriers to accumulate in the body of the device through carrier generation mechanisms that may include impact ionization, band-to-band tunneling and/or channel-initiated secondary hot electrons.

Abstract: A thin film transistor for driving a gate line and a liquid crystal display having the same are provided. The thin film transistor for driving a gate line includes a gate electrode, a semiconductor layer formed on the gate electrode, a drain electrode formed on the semiconductor layer, a source electrode formed on the semiconductor layer and separated from the drain electrode and being coupled to the gate line, and a ripple-prevention electrode formed on the drain electrode which overlaps at least a part of the drain electrode.

Abstract: A diode device can include an enhancement mode gallium nitride transistor having a gate, a drain and a source, wherein the gate is connected to the drain to enable the device to perform as a diode. In some embodiments, an integrated switching-diode is described that includes a substrate, a gallium nitride switching transistor on the substrate and a free wheeling diode on the substrate and coupled to the switching transistor.

Abstract: A semiconductor device with a field ring in an edge pattern of a semiconductor body with a central cell area and with field plate discharge pattern. The edge pattern exhibits at least one horizontal field plate which is arranged with one end over the field ring and with its other end on insulating layers towards the edge of the semiconductor body. A first ring-shaped area of a type of conduction doped complementary to a drift section material exhibits a field ring effect. A second highly doped ring-shaped area which contacts the one end of the horizontal field plate and forms a pn junction with the first ring-shaped area and which is arranged within the first area exhibits a locally limited punch-through effect or a resistive contact to the drift section material.

Abstract: This invention discloses semiconductor device that includes a top region and a bottom region with an intermediate region disposed between said top region and said bottom region with a controllable current path traversing through the intermediate region. The semiconductor device further includes a trench with padded with insulation layer on sidewalls extended from the top region through the intermediate region toward the bottom region wherein the trench includes randomly and substantially uniformly distributed nano-nodules as charge-islands in contact with a drain region below the trench for electrically coupling with the intermediate region for continuously and uniformly distributing a voltage drop through the current path.

Abstract: The present invention provides structures for an integrated antifuse that incorporates an integrated sensing transistor with an integrated heater. Two terminals connected to the upper plate allow the heating of the upper plate, accelerating the breakdown of the antifuse dielectric at a lower bias voltage. Part of the upper plate also serves as the gate of the integrated sensing transistor. The antifuse dielectric serves as the gate dielectric of the integrated transistor. The lower plate comprises a channel, a drain, and a source of a transistor. While intact, the integrated sensing transistor allows a passage of transistor current through the drain. When programmed, the antifuse dielectric, which is the gate of the integrated transistor, is subjected to a gate breakdown, shorting the gate to the channel and resulting in a decreased drain current. The integrated antifuse structure can also be wired in an array to provide a compact OTP memory array.

Abstract: A method for making dual pre-doped gate stacks used in semiconductor applications such as complementary metal oxide semiconductor (CMOS) devices and metal oxide semiconductor field effect transistors (MOSFETs) is provided. The method involves providing at least one pre-doped conductive layer, such as poly silicon (poly-Si), on a gate stack and etching by exposing the conductive layer to an etching composition comprising at least one carbon containing gas. The carbon containing gas can be selected from gases having the general formula CxHy, such as, for example, CH4, C2H2, C2H4, and C2H6. The carbon containing gas can further be selected from gases having the general formula CxHyA, wherein A can represent one or more additional substituents selected from O, N, P, S, F, Cl, Br, and I. The processes can result in dual pre-doped gate stacks having essentially vertical sidewalls and further having a width of at least about 3 nm, such as from about 5 nm to about 150 nm.