Abstract: Memory cells and arrays have reduced bit line resistance. An element conductor is disposed on the top of the bit line to reduce the resistance of the bit line while maintaining a shallow bit line junction so that 200 Ohm/square or lower sheet resistances are achieved with the bit line junctions typically 20 nanometers or shallower while the doping levels in the junctions are below about 5×1019 atoms/cm3.

Abstract: One or more embodiments relate to a method for forming a memory device, the memory device including a control gate, a charge storage structure and a select gate, the method comprising: forming a gate tower, the gate tower including the control gate over the charge storage structure; forming a dummy tower laterally spaced apart from the gate tower; and forming a select gate between the gate tower and the dummy tower.

Abstract: Etch stop structures for floating gate devices are generally described.

Abstract: A semiconductor device includes an insulating layer and an undoped polysilicon layer that are stacked over a semiconductor substrate. The semiconductor substrate is exposed by removing the portions of the undoped polysilicon layer and the insulating layer. The trenches are formed by etching the exposed semiconductor substrate. Isolation layers are formed in the trenches, and a doped polysilicon layer is formed by implanting impurities into the undoped polysilicon layer.

Abstract: A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer. An interface layer pattern may be provided on the charge storage pattern, and a blocking insulation pattern may be provided on the interface layer pattern. Moreover, the block insulation pattern may include a high-k dielectric material, and the interface layer pattern and the blocking insulation pattern may include different materials. A control gate electrode may be provided on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode. Related methods are also discussed.

Abstract: A write and erase method of a semiconductor memory device includes a floating gate type transistor having a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a floating gate electrode formed on the gate insulating film, and a control gate electrode opposing the floating gate electrode with a hollow portion being sandwiched therebetween. A capacitance between the semiconductor substrate and the control gate electrode is controlled by one of an operation of forming, in the hollow portion, an electrical path which electrically connects the floating gate electrode and the control gate electrode, and an operation of eliminating the electrical path.

Abstract: A desired property for a metal gate electrode layer is that it can cover a three-dimensional semiconductor structure having a microstructure with high step coverage. Another desired property for the metal gate electrode layer is that the surface of a deposited electrode layer is flat on a nanometer scale, enables a dielectric layer for electrical insulation to be coated without performing special planization after deposition of the electrode layer. Furthermore, another desired property for the metal gate electrode layer is that it has the similar etching workability to materials used in an ordinary semiconductor manufacturing process. Furthermore, another desired property for the metal gate electrode layer is that it has a structure in which diffusion of impurity is suppressed due to homogeneity thereof and the absence of grain boundaries.

Abstract: A method for fabricating metal gate transistor is disclosed. First, a substrate having a first transistor region and a second transistor region is provided. Next, a stacked film is formed on the substrate, in which the stacked film includes at least one high-k dielectric layer and a first metal layer. The stacked film is patterned to form a plurality of gates in the first transistor region and the second transistor region, a dielectric layer is formed on the gates, and a portion of the dielectric layer is planarized until reaching the top of each gates. The first metal layer is removed from the gate of the second transistor region, and a second metal layer is formed over the surface of the dielectric layer and each gate for forming a plurality of metal gates in the first transistor region and the second transistor region.

Abstract: Embodiments of an apparatus and methods for providing improved flash memory cell characteristics are generally described herein. Other embodiments may be described and claimed.

Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, a select gate formed above the semiconductor substrate, a floating gate formed above the semiconductor substrate and an erase gate positioned lower than an upper surface of the floating gate, and opposite an edge of a lower surface of the floating gate.

Abstract: A non-volatile semiconductor storage device includes: a semiconductor substrate; a source region and a drain region formed in the semiconductor substrate so as to be separated from each other; a first insulating film formed between the source region and the drain region, on the semiconductor substrate; a floating electrode formed on the first insulating film and including a semiconductor conductive material layer having extension strain; a second insulating film formed on the floating electrode; and a control electrode formed on the second insulating film. The extension strain of the floating electrode becomes gradually small as the location advances from the second insulating film toward the first insulating film, and the floating electrode has extension strain of 0.01% or more at an interface between the floating electrode and the second insulating film, and has extension strain less than 0.01% at an interface between the floating electrode and the first insulating film.

Abstract: A memory cell array of a NOR type flash memory is constructed by arranging memory cell transistors in a matrix, each of the memory cell transistors includes a contact connecting a semiconductor substrate to an overlayer wire. Columns of the memory cell transistors are isolated from one another by shallow trench isolations. The height of top surface of a filling oxide film in the shallow trench isolation which is adjacent to each drain contact is equal to that of top surface of the drain region. The top surface of a filling oxide film in the shallow trench isolation which is adjacent to each channel region is higher than a top surface of the semiconductor substrate in the channel region.

Abstract: Disclosed herein is a flash memory device in which the distribution of threshold voltage is significantly reduced and the durability is improved even though a floating gate has a micro- or nano-size length. It comprises a tunneling insulation film formed on a semiconductor substrate; a multilayer floating gate structure comprising a first thin storage electrode, a second thick storage electrode, and a third thin storage electrode, defined in that order on the tunneling insulation film; an interelectrode insulation film and a control electrode formed in that order on the floating gate structure; and a source/drain provided in the semiconductor substrate below the opposite sidewalls of the floating gate structure. The novel flash memory device can be readily fabricated at a high yield through a process compatible with a conventional one.

Abstract: The present invention provides a semiconductor device including a semiconductor substrate provided with a trench section; a tunnel insulating film covering an inner surface of the trench section; a trap layer provided in contact with the tunnel insulating film on an inner surface of an upper portion of the trench section; a top insulating film provided in contact with the trap layer; a gate electrode embedded in the trench section, and provided in contact with the tunnel insulating film at a lower portion of the trench section and in contact with the top insulating film at the upper portion of the trench section, in which the trap layer and the top insulating film, in between the lower portion of the trench section and the upper portion of the trench section, extend and protrude from both sides of the trench section so as to be embedded in the gate electrode, and a method for manufacturing thereof.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a charge storage structure and a gate. The charge storage structure is formed on a substrate. The gate is formed on the charge storage structure. The gate includes a lower portion formed of silicon and an upper portion formed of metal silicide. The upper portion of the gate has a width greater than that of the lower portion of the gate.

Abstract: A nonvolatile semiconductor memory device includes a gate insulating film formed on a semiconductor substrate, a first gate electrode corresponding to a memory cell transistor and a second gate electrode. The first gate electrode includes a floating gate electrode film, a first interelectrode insulating film and a control gate electrode film. The floating gate electrode film has a polycrystalline silicon film and the control gate electrode film having a silicide film. The second gate electrode includes a lower electrode film, a second interelectrode insulating film and an upper electrode film. The second interelectrode insulating film includes an opening. The lower electrode film includes a void below the opening of the second interelectrode insulating film. The upper electrode film includes a silicide film. The lower electrode film includes a polycrystalline silicon film and a silicide film which is located between the opening and the void.

Abstract: According to an aspect of the present invention, there is provided a semiconductor memory device including: a semiconductor substrate having: first device regions divided by first isolation films and second device regions divided by second isolation films a gate insulating film formed on the semiconductor substrate; a first element including: a first gate formed on the gate insulating film in the first device regions, a first inter-electrode insulating film formed on the first gate and on the first isolation films, and a second gate formed on the first inter-electrode insulating film; and a second element including: a third gate formed on the gate insulating film in the second device regions, and a fourth gate formed on the third gate and on the second isolation films; wherein a thickness of the third gate is larger than a thickness of the first gate.

Abstract: A method of making a non-volatile MOS semiconductor memory device includes a formation phase, in a semiconductor material substrate, of isolation regions filled by field oxide and of memory cells separated each other by said isolation regions The memory cells include an electrically active region surmounted by a gate electrode electrically isolated from the semiconductor material substrate by a first dielectric layer; the gate electrode includes a floating gate defined simultaneously to the active electrically region. A formation phase of said floating gate exhibiting a substantially saddle shape including a concavity is proposed.

Abstract: A method for fabricating a semiconductor device includes forming a first conductive layer over a substrate, forming an intermediate structure over the first conductive layer, the intermediate structure formed in a stack structure comprising at least a first metal layer and a nitrogen containing metal silicide layer, and forming a second conductive layer over the intermediate structure.

Abstract: Disclosed is a semiconductor storage device having a trench around a bit-line diffusion region in an area of a p-well, which constitutes a memory cell area, that is not covered by a word line and a select gate that intersects the word line. An insulating film is buried in the trench.

Abstract: A non-volatile storage device is disclosed that includes a set of connected non-volatile storage elements formed on a well, a bit line contact positioned in the well, a source line contact positioned in the well, a bit line that is connected to the bit line contact, and a source line that is connected to the source line contact and the well.

Abstract: A nonvolatile semiconductor memory device includes a first insulating film on a channel, a floating gate electrode on the first insulating film, a second insulating film on the floating gate electrode, and a control gate electrode on the second insulating film. Each of the first and second insulating films comprises at least two layers, one layer directly in contact with the floating gate electrode is formed by an insulating material (A) including a metal element having a d orbital, and the other at least one layer is formed by an insulating material (B) chiefly including one of a metal element without the d orbital, and a semiconductor element.

Abstract: The channel of each nonvolatile semiconductor memory element has a plate-like shape, and a charge accumulating layer is formed on one face of the channel region, with an insulating film being interposed in between. A control gate electrode is then formed on the charge accumulating layer, with another insulating film being interposed in between. Another control gate electrode is formed on the other face of the channel region, with yet another insulating film being interposed in between. The plate-like semiconductor region is designed to have a thickness smaller than twice the largest depletion layer thickness determined by the impurity concentration. In this manner, variations of the threshold voltages varying with the voltage of the control gate electrodes can be made smaller than the minimum value in conventional elements.

Abstract: A semiconductor memory device comprises: a plurality of transistors having a stacked-gate structure, each transistor including a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an upper gate formed and silicided on the lower gate with the intergate insulator interposed. A portion of the transistors has an aperture formed through the intergate insulator to connect the lower gate with the upper gate and further includes a silicide suppression region between the aperture and the gate insulator to suppress diffusion of metal atoms from the silicided upper gate.

Abstract: Non-volatile memory devices are provided including a control gate electrode on a substrate; a charge storage insulation layer between the control gate electrode and the substrate; a tunnel insulation layer between the charge storage insulation layer and the substrate; a blocking insulation layer between the charge storage insulation layer and the control gate electrode; and a material layer between the tunnel insulation layer and the blocking insulation layer, the material layer having an energy level constituting a bottom of a potential well.

Abstract: A method of manufacturing a nonvolatile memory device is provided. The method includes forming an isolation layer in a semiconductor substrate defining an active region and forming a molding pattern on the isolation layer. A first conductive layer is formed on a sidewall and a top surface of the molding pattern and on the semiconductor substrate. The first conductive layer on the top surface of the molding pattern is selectively removed forming a conductive pattern. The conductive pattern includes a body plate disposed on the active region and a protrusion which extends from an edge of the body plate onto the sidewall of the molding pattern. The molding pattern is then removed. An inter-gate dielectric layer is formed on the isolation layer and the conductive pattern. Nonvolatile memory devices manufactured using the method are also provided.

Abstract: A semiconductor memory device includes a source region, a drain region, a channel region, a charge storage layer, and a control gate electrode. The source region and drain region are formed separately from each other in a surface of a semiconductor substrate. The channel region is formed in the semiconductor substrate and located between the source region and the drain region. The charge storage layer is formed on the channel region with a first insulating film interposed therebetween. The control gate electrode is formed on the charge storage layer with a second insulating film interposed therebetween. The control gate has an upper corner portion rounded with a radius of curvature of 5 nm or more.

Abstract: A semiconductor device includes transistors with a vertical gate electrode. In a transistor structure, a semiconductor pattern has first and second sides facing in a transverse direction, and third and fourth sides facing in a longitudinal direction. Gate patterns are disposed adjacent to the first and second sides of the semiconductor pattern. Impurity patterns directly contact the third and fourth sides of the semiconductor pattern. A gate insulating pattern is interposed between the gate patterns and the semiconductor pattern.

Abstract: A nonvolatile semiconductor memory device having high charge retention characteristics and capable of improving leakage characteristics of a dielectric film disposed between a charge storage layer and a control gate electrode, and manufacturing method thereof is disclosed. According to one aspect, there is provided a semiconductor memory device comprising a first electrode disposed on a first insulator on a semiconductor substrate, a second insulator disposed on the first electrode, a second electrode disposed on the second insulator, and diffusion layers disposed in the semiconductor substrate, wherein the second insulator including a silicon-rich silicon nitride film containing more silicon than that in a stoichiometric silicon nitride film, and a silicon oxide film formed on the silicon-rich silicon nitride film, and wherein the silicon-rich silicon nitride film has a ratio of a silicon concentration and a nitrogen concentration set to 1:0.9 to 1:1.2.

Abstract: Embodiments of non-volatile semiconductor devices include a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure containing nano-crystals located above the channel region. The gate structure comprises a gate dielectric substantially in contact with the channel region, spaced-apart nano-crystals disposed in the gate dielectric, one or more impurity blocking layers overlying the gate dielectric, and a gate conductor layer overlying the one more impurity blocking layers. The blocking layer nearest the gate conductor can be used to adjust the threshold voltage of the device and/or retard dopant out-diffusion from the gate conductor layer.

Abstract: A semiconductor memory device has: a substrate; a memory cell transistor of a split-gate type formed on the substrate; and a reference transistor formed on the substrate and used for generating a reference current that is used in sensing data stored in the memory cell transistor. The memory cell transistor has a floating gate and a control gate, while the reference transistor is a MIS (Metal Insulator Semiconductor) transistor having a single gate electrode.

Abstract: An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.

Abstract: A nonvolatile memory device with a blocking layer controlling the transfer of electric charges in a charge storage layer includes the blocking layer having a first blocking layer in contact with the charge storage layer and a second blocking layer over the first blocking layer, wherein the first blocking layer has a greater energy band gap than the second blocking layer and the second blocking layer has a greater permittivity than the first blocking layer.

Abstract: A non-volatile memory device includes a memory cell region which is formed on a semiconductor substrate to store predetermined information, and a peripheral circuit region which is formed on the semiconductor substrate. The memory cell region includes a gate electrode; and a charge storage layer, the charge storage layer being formed to be a notch or wedge shape having an edge extending into both sides of a bottom end of the gate electrode. The peripheral circuit region includes no charge storage layer therein.

Abstract: A memory system is disclosed that includes a set of non-volatile storage elements. A given memory cell has a dielectric cap above the floating gate. In one embodiment, the dielectric cap resides between the floating gate and a conformal IPD layer. The dielectric cap reduces the leakage current between the floating gate and a control gate. The dielectric cap achieves this reduction by reducing the strength of the electric field at the top of the floating gate, which is where the electric field would be strongest without the dielectric cap for a floating gate having a narrow stem.

Abstract: A non-volatile storage system in which a sidewall insulating layer of a floating gate is significantly thinner than a thickness of a bottom insulating layer, and in which raised source/drain regions are provided. During programming or erasing, tunneling occurs predominantly via the sidewall insulating layer and the raised source/drain regions instead of via the bottom insulating layer. The floating gate may have a uniform width or an inverted T shape. The raised source/drain regions may be epitaxially grown from the substrate, and may include a doped region above an undoped region so that the channel length is effectively extended from beneath the floating gate and up into the undoped regions, so that short channel effects are reduced. The ratio of the thicknesses of the sidewall insulating layer to the bottom insulating layer may be about 0.3 to 0.67.

Abstract: Conventional fabrication of sidewall oxide around an ONO-type memory cell stack usually produces Bird's Beak because prior to the fabrication, there is an exposed sidewall of the ONO-type memory cell stack that exposes side parts of a plurality of material layers respectively composed of different materials. Certain materials in the stack such as silicon nitrides are more difficult to oxidize than other materials in the stack such polysilicon. As a result oxidation does not proceed uniformly along the multi-layered height of the sidewall. The present disclosure shows how radical-based fabrication of sidewall dielectric can help to reduce the Bird's Beak formation. More specifically, it is indicated that short-lived oxidizing agents (e.g.

Abstract: An embodiment of a process is disclosed herein for fabricating a memory device integrated on a semiconductor substrate and comprising at least a nanocrystal memory cell and CMOS transistors respectively formed in a memory area and in a circuitry area. According to an embodiment, a process includes forming a nitride layer having an initial thickness, placed above a nanocrystal layer, in the memory area and the formation in the circuitry area of at least one submicron gate oxide. The process also provides that the initial thickness is such as to allow a complete transformation of the nitride layer into an oxide layer at upon formation of said at least one submicron gate oxide.

Abstract: A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures.

Abstract: The disclosed systems and methods relate to floating gate non-volatile memory cells, with a floating gate comprising at least two layers constructed in different conductive or semiconductive materials. At least two of the layers of the floating gate are separated by an intermediate dielectric layer having a predetermined thickness enabling direct tunneling current between the layers.

Abstract: An edgeless one-transistor flash memory array includes transistors that have two polysilicon gate layers that overlay an active region. The bottom polysilicon gate layer is electrically isolated. The memory is configured such that current passes from drain to source under the bottom polysilicon layer, such that it does not approach a field oxide region. An edgeless two-transistor programmable memory includes memory cells that have two active devices. Two polysilicon gate layers overlay two active regions and are shared between the two active devices. One of the devices is used to program and erase the cell while the other used as a programmable switch in a programmable logic device. The bottom polysilicon gate layer is electrically isolated. The memory is configured such that current passes from drain to source under the bottom polysilicon layer, such that it does not approach a field oxide region.

Abstract: A nonvolatile semiconductor memory device includes: a tunneling insulating film; a floating gate electrode; an inter-electrode insulating film, in which an interface facing the floating gate electrode and an interface facing a control gate electrode are defined as the first interface and the second interface, respectively; and a control gate electrode. The inter-electrode insulating film includes one or more first elements selected from rare earth elements, one or more second elements selected from Al, Ti, Zr, Hf, Ta, Mg, Ca, Sr and Ba, and oxygen. A composition ratio of the first element, which is defined as the number of atoms of the first element divided by that of the second element, is changed between the first interface and the second interface, and the composition ratio in the vicinity of the first interface is lower than that in the vicinity of the second interface.

Abstract: A semiconductor device includes a first conductive layer, a first intermediate structure over the first conductive layer, a second intermediate structure over the first intermediate structure, and a second conductive layer over the second intermediate structure. The first intermediate structure includes a metal silicide layer and a nitrogen containing metal layer. The second intermediate structure includes at least a nitrogen containing metal silicide layer.

Abstract: Embodiments relate to a manufacturing method of a flash memory device which improves electrical characteristics by reducing or preventing void generation. A manufacturing method of a flash memory device according to embodiments includes forming a plurality of gate patterns over a semiconductor substrate including a tunnel oxide layer, a floating gate, a dielectric layer, and a control gate. A spacer layer may be formed as a compound insulating layer structure over the side wall of the gate pattern. A source/drain area may be formed over the semiconductor substrate at both sides of the control gate. An insulating layer located at the outermost of the spacer layer may be removed. A contact hole may be formed between the gate patterns by forming and patterning the interlayer insulating layer. A contact plug may be formed in the contact hole.

Abstract: An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.

Abstract: The invention relates to a flash memory device and its method of fabrication. The method includes the steps of: forming gate protection patterns over a peripheral region of a semiconductor substrate; forming a tunnel insulating film over the semiconductor substrate; forming a first conductive film over the tunnel insulating film between adjacent gate protection patterns; forming a dielectric film over the first conductive film and the gate protection patterns; etching a portion of the dielectric film in the peripheral region to expose a portion of the first conductive film between adjacent gate protection patterns; forming a second conductive film over the dielectric film and the first conductive film; and etching the second conductive film, the dielectric film, the first conductive film, the tunnel insulating film and the gate protection patterns to form a gate, wherein the gate protection patterns remain on the sidewalls of the first conductive film and the tunnel insulating film in the peripheral region.

Abstract: A polysilicon layer provided for a polysilicon electrode (8) is patterned by means of a resist mask (5) and an auxiliary layer (4) made of a material that is suitable as an antireflection layer, the auxiliary layer (4) being provided with lateral hollowed-out recesses in such a way that the polysilicon electrode is formed with rounded edges (7) during etching. The auxiliary layer is preferably produced from a soluble material and with a thickness of 70 nm to 80 nm. A base layer (2) may be provided as a gate dielectric of memory cell transistors and additionally as an etching stop layer.

Abstract: A flash memory is provided. The flash memory features of having the select gate transistors to include two different channel structures, which are a recessed channel structure and a horizontal channel. Because of the design of the recessed channel structure, the space between the gate conductor lines, which are for interconnecting the select gates of the select gate transistors arranged on the same column, can be shortened. Therefore, the integration of the flash memory can be increased; and the process window of the STI process can be increased as well. In addition, at least one depletion-mode select gate transistor is at one side of the memory cell string. The select gate transistor of the depletion-mode is always turned on.

Abstract: A semiconductor device includes a device isolation layer in a semiconductor substrate, an active region defined by the device isolation layer, the active region including a main surface and a recess region including a bottom surface that is lower than the main surface, and a gate electrode formed over the recess region, wherein a top surface of the device isolation layer adjacent to the recess region is lower than the bottom surface of the recess region.

Abstract: A nonvolatile memory device includes a semiconductor substrate and a device isolation layer on the semiconductor substrate. A fin-shaped active region is formed between portions of the device isolation layer. A sidewall protection layer is formed on the sidewall of the fin-shaped active region where source and drain regions are formed. Thus, it may be possible to reduce the likelihood of an undesirable connection between an interconnection layer connected to the source and drain regions and a lower sidewall of the active region so that charge leakage from the interconnection layer to a substrate can be prevented or reduced. The sidewall protection layer may be formed using the device isolation layer. Alternatively, an insulating layer having an etch selectivity with respect to an interlayer insulating layer may be formed on the device isolation layer so as to cover the sidewall of the active region.