Gate Electrodes For Nonplanar Mosfet (epo) Patents (Class 257/E29.13)
  • Patent number: 10121791
    Abstract: A semiconductor device includes a substrate, first through fourth gate electrodes, and first through fifth fin active pattern. A first recess which is formed in the substrate between the first and second gate electrodes intersecting the second fin active pattern, is filled with a first source/drain region, and has a first depth in a third direction perpendicular to the first and second directions. A second recess which is formed in the substrate between the third and fourth gate electrodes intersecting the second fin active pattern, is filled with a second source/drain region, and has a second depth in the third direction. A third recess which is formed in the substrate between the second and third gate electrodes intersecting the second fin active pattern, is filled with a third source/drain region, and has a third depth in the third direction. The third depth is greater than the first and second depths.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: November 6, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun Kwan Yu, Hyo Jin Kim, Dong Suk Shin, Ji Hye Yi, Ryong Ha
  • Patent number: 10103175
    Abstract: A method of forming a fin-shaped structure includes the following steps. A substrate having at least a fin structure thereon is provided. A liner is formed on sidewalls of the fin structure. An oxide layer is formed between the fin structure and the substrate. The fin structure is removed until a bottom layer of the fin structure is reserved, to form a recess between the liner. A buffer epitaxial layer and an epitaxial layer are sequentially formed in the recess. A top part of the liner is removed until sidewalls of the epitaxial layer are exposed. Moreover, a fin-shaped structure formed by said method is also provided.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: October 16, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Yu-Hsiang Hung, Ssu-I Fu, Jyh-Shyang Jenq
  • Patent number: 9799664
    Abstract: The present application provides a flash memory device. The flash memory device includes a semiconductor substrate; and a plurality of tunnel oxide layers formed on a surface of the semiconductor substrate. The flash memory device also includes a floating gate having a first portion with a width smaller than a width of the tunnel oxide layer and a second portion with a width greater than the width of the first portion formed on the first portion formed on each of the floating silicon oxide layers. Further, the flash memory device includes a plurality of shallow trench isolation structures formed in the surface of the semiconductor substrate between adjacent floating gates and the tunnel oxide layers; and liner oxide layers formed on side surfaces of the first portion of the floating gates.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: October 24, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Xinpeng Wang
  • Patent number: 9006829
    Abstract: Among other things, a semiconductor device comprising an aligned gate and a method for forming the semiconductor device are provided. The semiconductor device comprises a gate formed according to a multi-gate structure, such as a gate-all-around structure. A first gate portion of the gate is formed above a first channel of the semiconductor device. A second gate portion of the gate is formed below the first channel, and is aligned with the first gate portion. In an example of forming the gate, a cavity is etched within a semiconductor layer formed above a substrate. A dielectric layer is formed around at least some of the cavity to define a region of the cavity within which the second gate portion is to be formed in a self-aligned manner with the first gate portion. In this way, the semiconductor device comprises a first gate portion aligned with a second gate portion.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jean-Pierre Colinge, Kuo-Cheng Ching, Zhiqiang Wu
  • Patent number: 8901659
    Abstract: Non-planar semiconductor devices including at least one semiconductor nanowire having a tapered profile which widens from the source side of the device towards the drain side of the device are provided which have reduced gate to drain coupling and therefore reduced gate induced drain tunneling currents.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey W. Sleight, Sarunya Bangsaruntip
  • Patent number: 8901667
    Abstract: A non-planar semiconductor transistor device includes a substrate layer. Conductive channels extend between corresponding source and drain electrodes. A gate stack extending in a direction perpendicular to the conductive channels crosses over the plurality of conductive channels. The gate stack includes a dielectric layer running along the substrate and the plurality of conductive channels and arranged with a substantially uniform layer thickness, a work-function electrode layer covers the dielectric layer and is arranged with a substantially uniform layer thickness, and a metal layer, distinct from the work-function electrode layer, covers the work-function electrode layer and is arranged with a substantially uniform height with respect to the substrate such that the metal layer fills a gap between proximate conductive channels of the plurality of conductive channels.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Hemanth Jagannathan, Sivananda Kanakasabapathy
  • Patent number: 8871575
    Abstract: A method of fabricating a field effect transistor with a fin structure is described. At least a fin structure is formed on a substrate. A planar insulation layer covering the fin structure is formed. A trench is formed in the insulation layer and intersects the fin structure both lengthwise. The trench is disposed over portions of the fin structure, and a lengthwise direction of the trench intersects a lengthwise direction of the fin structure, and thereby an upper portion of the fin structure is exposed to the trench. The exposed upper portion of the fin structure will serve as a gate channel region. A gate structure covering the upper portion is formed within the trench. The upper portion of the fin structure may be further trimmed.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: October 28, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Jung Wang, Tong-Yu Chen
  • Patent number: 8847295
    Abstract: A structure and method of forming a semiconductor device with a fin is provided. In an embodiment a hard mask is utilized to pattern a gate electrode layer and is then removed. After the hard mask has been removed, the gate electrode layer may be separated into individual gate electrodes.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Feng Shieh, Chih-Hao Yu, Chang-Yun Chang
  • Patent number: 8836019
    Abstract: A recessed channel transistor, a semiconductor device including a transistor and methods of manufacturing the same are provided, the recessed channel transistor includes a gate structure, a second impurity region and a first impurity region. The gate structure may be formed on a substrate and filling a recess. The first impurity region, including first impurities, may be formed at a first upper portion of the substrate adjacent to the gate structure. The second impurity region, including second impurities, may be formed at a second upper portion of the substrate contacting the gate structure. The first impurity region may surround the second impurity region. The first impurities have a conductive type different from that of the second impurities.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: September 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-Hee Lim, Hyuck-Chai Jung
  • Patent number: 8766367
    Abstract: A textured thin film transistor is comprised of an insulator sandwiched between a textured gate electrode and a semi-conductor. A source electrode and drain electrode are fabricated on a surface of the semi-conductor. The textured gate electrode is fabricated such that a surface is modified in its texture and/or geometry, such modifications affecting the transistor current.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: July 1, 2014
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Sanjiv Sambandan, Robert A. Street
  • Patent number: 8698215
    Abstract: A thin film transistor (TFT) and a method of manufacturing the same such that an ohmic contact can be formed between a semiconductor layer and a source electrode or between the semiconductor layer and a drain electrode, wherein the TFT can be applied to a plastic substrate. The TFT includes: a substrate; an active layer formed of ZnO, InZnO, ZnSnO, and/or ZnInGaO on the substrate and including a channel region, a source region, and a drain region; a gate electrode insulated from the active layer; and source and drain electrodes insulated from the gate electrode and electrically connected to the source region and the drain region, respectively, wherein the source region and the drain region of the active layer include hydrogen.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: April 15, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jae-Kyeong Jeong, Hyun-Soo Shin, Yeon-Gon Mo
  • Patent number: 8692320
    Abstract: Recessed access transistor devices used with semiconductor devices may include gate electrodes having materials with multiple work functions, materials that are electrically isolated from each other and supplied with two or more voltage supplies, or materials that create a diode junction within the gate electrode.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: April 8, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Jasper S. Gibbons, Darren V. Young, Kunal R. Parekh, Casey Smith
  • Patent number: 8674420
    Abstract: A semiconductor device, including a semiconductor substrate including isolations defining active regions of the semiconductor substrate, a plurality of buried gate electrodes extending below an upper surface of the semiconductor device, and a plurality of bit lines extending along a first direction over the semiconductor substrate, wherein the plurality of bit lines are connected to corresponding ones of the active regions of the semiconductor substrate, and at least a portion of the bit lines extend along a same and/or substantially same plane as an upper surface of the corresponding active region to which it is connected.
    Type: Grant
    Filed: October 5, 2009
    Date of Patent: March 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kye-Hee Yeom
  • Patent number: 8664713
    Abstract: A power device integrated on a semiconductor substrate and having a plurality of conductive bridges within a trench gate structure. In an embodiment, a semiconductor substrate includes a trench having sidewalls and a bottom, the walls and bottom are covered with a first insulating coating layer which then also includes a conductive gate structure. An embodiment provides the formation of the conductive gate structure with covering at least the sidewalls with a second conductive coating layer of a first conductive material. This results in a conductive central region of a second conductive material having a different resistivity than the first conductive material forming a plurality of conductive bridges between said second conductive coating layer and said conductive central region.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: March 4, 2014
    Assignee: STMicroelectronics S.R.L.
    Inventors: Angelo Magri, Antonino Sebastiano Alessandria, Stefania Fortuna, Leonardo Fragapane
  • Patent number: 8653610
    Abstract: A non-planar semiconductor transistor device includes a substrate layer. Conductive channels extend between corresponding source and drain electrodes. A gate stack extending in a direction perpendicular to the conductive channels crosses over the plurality of conductive channels. The gate stack includes a dielectric layer running along the substrate and the plurality of conductive channels and arranged with a substantially uniform layer thickness, a work-function electrode layer covers the dielectric layer and is arranged with a substantially uniform layer thickness, and a metal layer, distinct from the work-function electrode layer, covers the work-function electrode layer and is arranged with a substantially uniform height with respect to the substrate such that the metal layer fills a gap between proximate conductive channels of the plurality of conductive channels.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: February 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Hemanth Jagannathan, Sivananda Kanakasabapathy
  • Patent number: 8653565
    Abstract: Various aspects of the technology includes a quad semiconductor power and/or switching FET comprising a pair of control/sync FET devices. Current may be distributed in parallel along source and drain fingers. Gate fingers and pads may be arranged in a serpentine configuration for applying gate signals to both ends of gate fingers. A single continuous ohmic metal finger includes both source and drain regions and functions as a source-drain node. A set of electrodes for distributing the current may be arrayed along the width of the source and/or drain fingers and oriented to cross the fingers along the length of the source and drain fingers. Current may be conducted from the electrodes to the source and drain fingers through vias disposed along the surface of the fingers. Heat developed in the source, drain, and gate fingers may be conducted through the vias to the electrodes and out of the device.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: February 18, 2014
    Assignee: Sarda Technologies, Inc.
    Inventor: James L. Vorhaus
  • Patent number: 8637375
    Abstract: A method of manufacturing a tunnel field effect transistor is disclosed. The method comprises forming a two-step profile in a silicon substrate (100) using a patterned hard mask (104) covering the higher steps of said profile; forming a gate stack (114, 116) against the side wall of the higher step; forming spacers (122) on either side of the gate stack (118); and implanting a first type impurity (124) in the higher step and an opposite type impurity in the neighboring lower step (120), wherein at least the first type impurity is implanted using an angled implanting step after removing the patterned hard mask (104). In a preferred embodiment, the method further comprises forming a sacrificial spacer (108) against a side wall of a higher step and the side wall of the hard mask (104); further etching the lower step (106, 110) next to said spacer (108) and subsequently growing a further semiconductor portion (112) on said lower step and removing the spacer (108) prior to forming the gate stack.
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: January 28, 2014
    Assignee: NXP B.V.
    Inventors: Gilberto Curatola, Marcus J. H. Van Dal
  • Patent number: 8618604
    Abstract: A semiconductor wafer has a main surface. A main chip region is formed on the main surface. A sub-chip region is smaller in area than the main chip region, and positioned on an edge side of the semiconductor wafer relative to the main chip region. The sub-chip region is identical to the main chip region in design pattern. Accordingly, a semiconductor device in which occurrence of a pattern failure at the edge of the wafer can be prevented when chips are arranged in the surface of the semiconductor wafer and a method of manufacturing the same can be obtained.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: December 31, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventor: Atsushi Narazaki
  • Patent number: 8618600
    Abstract: Integrated circuits including a buried wiring lien. One embodiment provides a field effect transistor including a first active area and a gate electrode buried below a main surface of a semiconductor substrate. A gate wiring line may be buried below the main surface and a section of the gate wiring line may form the gate electrode. Above the gate wiring line, a buried contact structure is formed that is adjacent to and in direct contact with the first or a second active area.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: December 31, 2013
    Assignee: Qimonda AG
    Inventor: Stafan Slesazeck
  • Patent number: 8536644
    Abstract: A semiconductor device including a buried gate and a method for forming the same are disclosed. The semiconductor device includes a buffer layer formed on a surface of a trench in a semiconductor substrate, and a gate electrode configured to partially bury the trench and formed of the same material as in the buffer layer.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: September 17, 2013
    Assignee: SK Hynix Inc.
    Inventor: Hae Il Song
  • Patent number: 8461004
    Abstract: This invention discloses semiconductor device that includes a top region and a bottom region with an intermediate region disposed between said top region and said bottom region with a controllable current path traversing through the intermediate region. The semiconductor device further includes a trench with padded with insulation layer on sidewalls extended from the top region through the intermediate region toward the bottom region wherein the trench includes randomly and substantially uniformly distributed nano-nodules as charge-islands in contact with a drain region below the trench for electrically coupling with the intermediate region for continuously and uniformly distributing a voltage drop through the current path.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: June 11, 2013
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: François Hébert, Tao Feng
  • Patent number: 8455307
    Abstract: FINFET ICs and methods for their fabrication are provided. In accordance with one embodiment a FINFET IC is fabricated by forming in a substrate a region doped with an impurity of a first doping type. The substrate region is etched to form a recess defining a fin having a height and sidewalls and the recess adjacent the fin is filled with an insulator having a thickness less than the height. Spacers are formed on the sidewalls and a portion of the insulator is etched to expose a portion of the sidewalls. The exposed portion of the sidewalls is doped with an impurity of the first doping type, the exposed sidewalls are oxidized, and the sidewall spacers are removed. A gate insulator and gate electrode are formed overlying the fin, and end portions of the fin are doped with an impurity of a second doping type to form source and drain regions.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: June 4, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventor: Jin Cho
  • Patent number: 8455956
    Abstract: An embodiment of a semiconductor power device provided with: a structural body made of semiconductor material with a first conductivity, having an active area housing one or more elementary electronic components and an edge area delimiting externally the active area; and charge-balance structures, constituted by regions doped with a second conductivity opposite to the first conductivity, extending through the structural body both in the active area and in the edge area in order to create a substantial charge balance. The charge-balance structures are columnar walls extending in strips parallel to one another, without any mutual intersections, in the active area and in the edge area.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: June 4, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe Saggio, Alfio Guarnera
  • Patent number: 8390034
    Abstract: Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: March 5, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Luan C. Tran
  • Patent number: 8372714
    Abstract: A semiconductor device can be manufactured by a method that includes forming a structure that includes a plurality of layers of semiconductor material. One or more etching processes are performed on the multi-layered semiconductor structure, and then an Ar/O2 treatment is performed on the multi-layered semiconductor structure. The Ar/O2 treatment includes exposure of the structure to Ar ion bombardment and O2 molecular oxidation. The Ar/O2 treatment can be used to create a bottle-shaped structure.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: February 12, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Kuo Liang Wei, Hong-Ji Lee
  • Patent number: 8357970
    Abstract: Methods of fabricating charge storage transistors are described, along with apparatus and systems that include them. In one such method, a pillar of epitaxial silicon is formed. At least first and second charge storage nodes (e.g., floating gates) are formed around the pillar of epitaxial silicon at different levels. A control gate is formed around each of the charge storage nodes. Additional embodiments are also described.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: January 22, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Nirmal Ramaswamy
  • Patent number: 8309417
    Abstract: In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: November 13, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Hoon Son, Jong-Wook Lee, Jong-Hyuk Kang
  • Patent number: 8269288
    Abstract: An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.
    Type: Grant
    Filed: October 17, 2008
    Date of Patent: September 18, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiaki Iwamatsu, Takashi Terada, Hirofumi Shinohara, Kozo Ishikawa, Ryuta Tsuchiya, Kiyoshi Hayashi
  • Patent number: 8269287
    Abstract: Methods and apparatus for increasing the coupling coefficient of a floating gate memory device includes an MOS capacitors with self-aligning gate structures that provide increased capacitance per unit area over conventional MOS capacitors.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: September 18, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventor: Fredrick Jenne
  • Patent number: 8237220
    Abstract: In a high speed vertical channel transistor, a pillar structure is formed over a substrate, a gate electrode surrounds an outer wall of a lower portion of the pillar structure; and a word line extends in a direction to partially contact an outer wall of the gate electrode. The word line shifts toward a side of the pillar structure resulting in increased transistor speed.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: August 7, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Min-Gyu Sung, Heung-Jae Cho, Yong-Soo Kim, Kwan-Yong Lim, Se-Aug Jang
  • Patent number: 8217441
    Abstract: The invention includes methods for utilizing partial silicon-on-insulator (SOI) technology in combination with fin field effect transistor (finFET) technology to form transistors particularly suitable for utilization in dynamic random access memory (DRAM) arrays. The invention also includes DRAM arrays having low rates of refresh. Additionally, the invention includes semiconductor constructions containing transistors with horizontally-opposing source/drain regions and channel regions between the source/drain regions. The transistors can include gates that encircle at least three-fourths of at least portions of the channel regions, and in some aspects can include gates that encircle substantially an entirety of at least portions of the channel regions.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: July 10, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Mark Fischer
  • Patent number: 8212311
    Abstract: In a vertical transistor comprising a pillar-shaped semiconductor layer and a gate electrode formed around the pillar-shaped semiconductor layer, it is difficult to form a transistor having a gate length greater than that of the vertical transistor. The present invention provides a semiconductor device which comprises two vertical transistors comprising first and second pillar-shaped semiconductor layers each formed on a first diffusion layer on a substrate. The vertical transistors have a common gate electrode. A first upper diffusion layer formed on a top of the first pillar-shaped semiconductor layer is connected to a source electrode, and a second upper diffusion layer formed on a top of the second pillar-shaped semiconductor layer is connected to a drain electrode. The vertical transistors are connected in series to operate as a composite transistor having a gate length two times greater than that of each of the vertical transistors.
    Type: Grant
    Filed: April 15, 2010
    Date of Patent: July 3, 2012
    Assignee: Unisantis Electronics Singapore PTE Ltd.
    Inventors: Fujio Masuoka, Shintaro Arai
  • Patent number: 8183116
    Abstract: A planar double-gate transistor is manufactured wherein crystallisation inhibitors are implanted into the channel region (16) of a semiconductor wafer (10), said wafer having a laminate structure comprising an initial crystalline semiconductor layer (14) adjacent an amorphous semiconductor layer (12). Upon heating, partial re-growth of the amorphous semiconductor layer is restricted in the channel area thus allowing for the thickness of the source/drain extension regions to be increased whilst maintaining a thin channel. Any remaining amorphous material is selectively removed leaving a cavity to allow for the forming of gate electrodes (30,32) on opposing sides of the channel region. The invention can be exploited to a greater extent by providing an amorphous layer on both sides of the initial crystalline semiconductor layer thus providing for re-growth limitation in two directions.
    Type: Grant
    Filed: August 1, 2007
    Date of Patent: May 22, 2012
    Assignee: NXP B.V.
    Inventor: Bartlomiej J. Pawlak
  • Patent number: 8154075
    Abstract: A split gate type nonvolatile semiconductor memory device having a FinFET structure includes a semiconductor substrate, parallel trenches on a surface of the semiconductor substrate, and select and memory gate electrodes perpendicular to the trenches. While either the select or the memory gate electrodes are formed prior to the other gate electrodes, each remaining gate electrode is formed adjacent to a side wall of each of the gate electrodes. The semiconductor memory device includes source/drain regions each formed between each pair of the select gate electrodes and between each pair of the memory gate electrodes in protruding portions between each pair of the trenches. A difference between heights of the select gate electrodes and the memory gate electrodes is equal to or greater than a difference between heights of insulation layers formed on the bottom of each of the trenches and the source/drain regions.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: April 10, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Kenichiro Nakagawa
  • Patent number: 8084865
    Abstract: An anchoring structure for a metal structure of a semiconductor device includes an anchoring recess structure having at least one overhanging side wall, the metal structure being at least partly arranged within the anchoring recess structure.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: December 27, 2011
    Assignee: Infineon Technologies AG
    Inventors: Franz Hirler, Walter Rieger, Uwe Schmalzbauer, Rudolf Zelsacher, Markus Zundel
  • Patent number: 8049286
    Abstract: In the present invention, there is provided a semiconductor device including: element isolation regions formed in a state of being buried in a semiconductor substrate such that an element formation region of the semiconductor substrate is interposed between the element isolation regions; a gate electrode formed on the element formation region with an gate insulating film interposed between the gate electrode and the element formation region, the gate electrode being formed so as to cross the element formation region; and source-drain regions formed in the element formation region on both sides of the gate electrode, wherein a channel region made of the element formation region under the gate electrode is formed so as to project from the element isolation regions, and the source-drain regions are formed to a position deeper than surfaces of the element isolation regions.
    Type: Grant
    Filed: May 6, 2008
    Date of Patent: November 1, 2011
    Assignee: Sony Corporation
    Inventor: Yasushi Tateshita
  • Patent number: 7986002
    Abstract: A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.
    Type: Grant
    Filed: March 19, 2004
    Date of Patent: July 26, 2011
    Assignee: Panasonic Corporation
    Inventors: Junko Iwanaga, Takeshi Takagi, Yoshihiko Kanzawa, Haruyuki Sorada, Tohru Saitoh, Takahiro Kawashima
  • Patent number: 7977740
    Abstract: This invention discloses semiconductor device that includes a top region and a bottom region with an intermediate region disposed between said top region and said bottom region with a controllable current path traversing through the intermediate region. The semiconductor device further includes a trench with padded with insulation layer on sidewalls extended from the top region through the intermediate region toward the bottom region wherein the trench includes randomly and substantially uniformly distributed nano-nodules as charge-islands in contact with a drain region below the trench for electrically coupling with the intermediate region for continuously and uniformly distributing a voltage drop through the current path.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: July 12, 2011
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: François Hébert, Tao Feng
  • Patent number: 7919822
    Abstract: A semiconductor device that suppresses variation and a drop in the breakdown voltage of transistors. In the semiconductor device in which a logic transistor and a high-breakdown-voltage transistor are formed on one Si substrate, an insulating film which has an opening region and which is thick around the opening region is formed on a low concentration drain region formed in the Si substrate on one side of a gate electrode of the high-breakdown-voltage transistor. The insulating film around the opening region has a two-layer structure including a gate insulating film and a sidewall insulating film. When ion implantation is performed on the low concentration drain region beneath the opening region to form a high concentration drain region, the insulating film around the opening region prevents impurities from passing through.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: April 5, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hitoshi Asada
  • Patent number: 7902027
    Abstract: A semiconductor device includes a recessed-channel-array MOSFET including a gate electrode having a portion received in a recess. The gate insulting film has a first portion made of silicon oxide in contact with the sidewall of the recess and a second portion made of silicon oxynitride in contact with the bottom of the recess. The first portion has an equivalent oxide thickness larger than the equivalent oxide thickness of the second portion to reduce the parasitic capacitance of the gate electrode.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: March 8, 2011
    Assignee: Elpida Memory, Inc.
    Inventor: Hirohisa Yamamoto
  • Patent number: 7898041
    Abstract: A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: March 1, 2011
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Amlan Majumdar, Brian S. Doyle, Jack Kavalieros, Mark L. Doczy, Justin K. Brask, Uday Shah, Suman Datta, Robert S. Chau
  • Patent number: 7888743
    Abstract: Disclosed is a tri-gate field effect transistor with a back gate and the associated methods of forming the transistor. Specifically, a back gate is incorporated into a lower portion of a fin. A tri-gate structure is formed on the fin and is electrically isolated from the back gate. The back gate can be used to control the threshold voltage of the FET. In one embodiment the back gate extends to an n-well in a p-type silicon substrate. A contact to the n-well allows electrical voltage to be applied to the back gate. A diode created between the n-well and p-substrate isolates the current flowing through the n-well from other devices on the substrate so that the back gate can be independently biased. In another embodiment the back gate extends to n-type polysilicon layer on an insulator layer on a p-type silicon substrate. A contact to the n-type polysilicon layer allows electrical voltage to be applied to the back gate.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: February 15, 2011
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Matthew J. Breitwisch, Edward J. Nowak
  • Patent number: 7842977
    Abstract: A gate electrode structure comprises at least one bi-layer, wherein each bi-layer comprises a plating film and a stress amplifier film. The plating film includes a poly-crystalline material. The stress amplifier film determines the crystallization result of the poly-crystalline material, wherein a mechanical stress induced through the plating layer is amplified. Tensile or compressive strain may be induced in a crystalline substrate. Electron or hole mobility may be increased and on-resistance characteristics of a MOS field effect transistor may be improved.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: November 30, 2010
    Assignee: Qimonda AG
    Inventors: Stefan Jakschik, Thomas Hecht
  • Patent number: 7838915
    Abstract: Provided are a semiconductor device having a mesa-type active region including a plurality of slabs and a method of manufacturing the semiconductor device. The semiconductor device includes a first active region and a second active region. The first active region is formed in a line-and-space pattern on a substrate and includes the slabs, each slab having a first surface, a second surface facing a direction opposite to the first side, and a top surface. The first active region and the second active region are composed of identical or different materials. The second active region contacts at least one end of each of the slabs on the substrate to connect the slabs to one another. The method includes forming a first active region in a line-and-space pattern on the substrate and forming the second active region.
    Type: Grant
    Filed: February 5, 2005
    Date of Patent: November 23, 2010
    Assignee: Samsung Electronics Co.. Ltd.
    Inventors: Jung-a Choi, Jeong-hawan Yang, You-scung Jin
  • Patent number: 7838401
    Abstract: A semiconductor device comprises a field-effect transistor arranged in a semiconductor substrate, which transistor has a gate electrode, source/drain impurity diffusion regions, and carbon layers surrounding the source/drain impurity diffusion regions. Each of the carbon layers is provided at an associated of the source/drain impurity diffusion regions and positioned so as to be offset from the front edge of a source/drain extension in direction away from the gate electrode and to surround as profile the associated source/drain impurity diffusion region.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: November 23, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hiroyuki Ohta, Kenichi Okabe
  • Patent number: 7834395
    Abstract: A field-effect transistor includes a source region, a drain region and a channel region between the source and the drain region. A gate electrode is also arranged between them, where a lower edge of the gate electrode is formed below a lower edge of at least one of the source and drain regions. A first insulator structure is provided between the gate electrode and the source region. A second insulator structure is provided between the gate electrode and the drain region. The first and the second insulator structures are formed asymmetric and may be adapted to different requirements. The asymmetric approach may provide longer transistor channels, a lower resistance of the gate electrode and smaller footprints for 3D-channel-transistors of, for example, array and support transistors in memory cells or power applications.
    Type: Grant
    Filed: February 13, 2007
    Date of Patent: November 16, 2010
    Assignee: Qimonda AG
    Inventors: Dietmar Temmler, Alexander Sieck
  • Patent number: 7772058
    Abstract: A MOS type SiC semiconductor device having high reliability and a longer lifespan against TDDB of a gate oxide film is disclosed. The semiconductor device includes a MOS (metal-oxide-semiconductor) structure having a silicon carbide (SiC) substrate, a polycrystalline Si gate electrode, a gate oxide film interposed between the SiC substrate and the polycrystalline Si gate electrode and formed by thermally oxidizing a surface of the SiC substrate, and an ohmic contact electrically contacted with the SiC substrate. The semiconductor device further includes a polycrystalline Si thermally-oxidized film formed by oxidizing a surface of the polycrystalline Si gate electrode. The gate oxide film has a thickness of 20 nm or less, preferably 15 nm or less.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: August 10, 2010
    Assignee: Nissan Motor Co., Ltd.
    Inventor: Satoshi Tanimoto
  • Patent number: 7749878
    Abstract: Embodiments relate to a method for manufacturing a semiconductor device that may be capable of obtaining a stable device characteristic by securing an optimal CD of a gate. In embodiments, a method may include forming a gate oxide layer on a semiconductor substrate, forming a photoresist pattern at a first region of an upper portion of the gate oxide layer, forming an insulating layer on the substrate of a second region except for the photoresist pattern, removing the photoresist pattern after a formation of the insulating layer, forming a polysilicon on the substrate from which the photoresist pattern is removed, planarizing the polysilicon to expose the insulating layer in order to form a gate, forming sidewalls at both sides of the gate: and implanting ions in a resulting object using the sidewalls as a mask to form source/drain.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: July 6, 2010
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Eui Kyu Ryou
  • Patent number: 7723768
    Abstract: Disclosed are an asymmetric recessed gate MOSFET, and a method for manufacturing the same. The asymmetric recessed gate MOSFET comprises: recess regions formed at a predetermined depth in a semiconductor; recessed gate electrodes formed at a predetermined height on a semiconductor substrate by gap-filling the recess regions, and misaligned with the recess region corresponding to one of the source/drain regions; spacers formed on sides of the recessed gate electrodes; and source/drain regions implanted with a dopant formed in the semiconductor substrate exposed between the spacers. The overlap between the gate electrodes and the source/drain regions can be reduced by having one of the source/drain regions misaligned with the recess regions in the recessed gate structure, and abnormal leakage current caused by consistency between an electron field max point A and a stress max pint B can be sharply reduced by changing the profile of the source/drain regions.
    Type: Grant
    Filed: May 16, 2005
    Date of Patent: May 25, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Moon Sik Suh
  • Patent number: 7701018
    Abstract: A semiconductor device comprising a first semiconductor region and a second semiconductor region, (a) wherein a field effect transistor is comprised of the first semiconductor region comprising at least one semiconductor layer(s) protruding upward from a substrate, a gate electrode(s) formed via an insulating film such that the gate electrode(s) strides over the semiconductor layer(s) and source/drain regions provided in the semiconductor layer(s) on both sides of the gate electrode(s), whereby a channel region is formed in at least both sides of the semiconductor layer(s), (b) wherein the second semiconductor region comprises semiconductor layers protruding upward from the substrate and placed, at least opposing the first semiconductor region at both ends in the direction perpendicular to a channel current direction and the side surface of the semiconductor layers facing the first semiconductor region is parallel to the channel current direction.
    Type: Grant
    Filed: March 22, 2005
    Date of Patent: April 20, 2010
    Assignee: NEC Corporation
    Inventors: Shigeharu Yamagami, Hitoshi Wakabayashi, Kiyoshi Takeuchi, Atsushi Ogura, Masayasu Tanaka, Masahiro Nomura, Koichi Takeda, Toru Tatsumi, Koji Watanabe, Koichi Terashima