Characterized By Configuration Of Gate Stack Of Thin Film Fets (epo) Patents (Class 257/E29.137)
  • Patent number: 10727352
    Abstract: A method of forming a long-channel fin field effect device is provided. The method includes forming a trench in a substrate, forming a pedestal in the trench, wherein the pedestal extends above the surface of the substrate, forming a sacrificial pillar on the pedestal, forming a rounded top surface on the sacrificial pillar to form a sacrificial support structure, forming a fin material layer on the exposed surface of the sacrificial support structure, and removing the sacrificial support structure to leave a free-standing inverted U-shaped fin.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: July 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Peng Xu, Juntao Li
  • Patent number: 10090304
    Abstract: An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area. In further embodiments, the impurity source film may provide a source of dopant that renders the sub-fin region complementarily doped relative to a region of the substrate forming a P/N junction that is at least part of an isolation structure electrically isolating the active fin region from a region of the substrate.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: October 2, 2018
    Assignee: Intel Corporation
    Inventors: Walid M. Hafez, Chia-Hong Jan, Jeng-Ya D. Yeh, Hsu-Yu Chang, Neville Dias, Chanaka Munasinghe
  • Patent number: 9716177
    Abstract: The device disclosed herein includes, among other things, a substrate made of a first semiconductor material, at least one layer of insulating material positioned above the substrate, a fin structure positioned above the layer of insulating material and the substrate, the fin structure including first, second and third layers of semiconductor material, wherein the semiconductor materials of the first, second and third layers are different than the first semiconductor material, and a gate structure around a portion of the fin structure includes the first, second and third layers of semiconductor material.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: July 25, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Bartlomiej Jan Pawlak, Behtash Behin-Aein, Mehdi Salmani-Jelodar
  • Patent number: 9379110
    Abstract: Disclosed is a process to prepare extremely thin semiconductor on insulator complementary metal-oxide-semiconductor devices having n-type and p-type metal oxide semiconductor field-effect transistors. The pFET and nFET devices of different strain, size, and geometry are prepared on the same chip without the requirement for an extra mask step.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: June 28, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li
  • Patent number: 9222170
    Abstract: Anisotropic materials, such as rutile TiO2, can exhibit dielectric constant of 170 along the tetragonal axis of (001) direction, and dielectric constant of 86 along directions perpendicular to the tetragonal axis. Layer of anisotropic material nanorods, such as TiO2 nanorods, can form a seed layer to grow a dielectric layer that can exhibit the higher dielectric constant value in a direction parallel to the substrate surface. The anisotropic layer can then be patterned to expose a surface normal to the high dielectric constant direction. A conductive material can be formed in contact with the exposed surface to create an electrode/dielectric stack along the direction of high dielectric constant.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: December 29, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Sergey Barabash, Dipankar Pramanik
  • Patent number: 9006803
    Abstract: An insulating layer is provided with a projecting structural body, and a channel formation region of an oxide semiconductor layer is provided in contact with the projecting structural body, whereby the channel formation region is extended in a three dimensional direction (a direction perpendicular to a substrate). Thus, it is possible to miniaturize a transistor and to extend an effective channel length of the transistor. Further, an upper end corner portion of the projecting structural body, where a top surface and a side surface of the projecting structural body intersect with each other, is curved, and the oxide semiconductor layer is formed to include a crystal having a c-axis perpendicular to the curved surface.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: April 14, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Toshinari Sasaki, Shinya Sasagawa, Akihiro Ishizuka
  • Patent number: 9000523
    Abstract: An organic light-emitting display device including a TFT comprising an active layer, a gate electrode comprising a lower gate electrode and an upper gate electrode, and source and drain electrodes insulated from the gate electrode and contacting the active layer; an organic light-emitting device electrically connected to the TFT and comprising a pixel electrode formed in the same layer as where the lower gate electrode is formed; and a pad electrode electrically coupled to the TFT or the organic light emitting device and comprising a first pad electrode formed in the same layer as in which the lower gate electrode is formed, a second pad electrode formed in the same layer as in which the upper gate electrode is formed, and a third pad electrode comprising a transparent conductive oxide, the first, second, and third pad electrodes being sequentially stacked.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: April 7, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jong-Hyun Choi, Jae-Hwan Oh
  • Patent number: 8987828
    Abstract: A finFET block architecture uses end-to-end finFET blocks in which the fin lengths are at least twice the contact pitch, whereby there is enough space for interlayer connectors to be placed on the proximal end and the distal end of a given semiconductor fin, and on the gate element on the given semiconductor fin. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. Interlayer connectors can be aligned over corresponding semiconductor fins which connect to gate elements.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: March 24, 2015
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Deepak D. Sherlekar
  • Patent number: 8987836
    Abstract: Field effect transistors including a source region and a drain region on a substrate, a fin base protruding from a top surface of the substrate, a plurality of fin portions extending upward from the fin base and connecting the source region with the drain region, a gate electrode on the fin portions, and a gate dielectric between the fin portions and the gate electrode may be provided. A top surface of the substrate may include a plurality of grooves (e.g., a plurality of convex portions and a plurality of concave portions). Further, a device isolation layer may be provided to expose upper portions of the plurality of fin portions and to cover top surfaces of the plurality of grooves.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: March 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myeong-cheol Kim, Cheol Kim, Jaehun Seo, YooJung Lee, Kisoo Chang, Siyoung Choi
  • Patent number: 8957424
    Abstract: Disclosed is an electroluminescence device having a substrate, a thin film transistor over the substrate, an insulating film over the thin film transistor, an electroluminescence element over the insulating film, a passivation film over the electroluminescence element, and a counter substrate over the passivation film. The electroluminescence element is configured to emit light through the counter substrate, and a space between the substrate and the counter substrate is filled with a filler. The electroluminescence device is featured by the tapered side surface of a gate electrode of the thin film transistor.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: February 17, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koji Ono, Hideomi Suzawa, Tatsuya Arao
  • Patent number: 8936965
    Abstract: A normally-off transistor having an oxide semiconductor layer in a channel formation layer is provided. The transistor comprises: a first oxide semiconductor layer functioning as a channel formation region; a source electrode layer and a drain electrode layer which overlap with the first oxide semiconductor layer; a gate insulating layer which is provided over and in contact with the first oxide semiconductor layer, the source electrode layer, and the drain electrode layer; a second oxide semiconductor layer which is provided over and in contact with the gate insulating layer and overlaps with the first oxide semiconductor layer; and a gate electrode layer provided over the second oxide semiconductor layer. A manufacturing method thereof is also disclosed.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: January 20, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuki Imoto, Yuji Asano, Tetsunori Maruyama
  • Patent number: 8927983
    Abstract: Disclosed herein is a thin film transistor array substrate. The thin film transistor array substrate includes a display area and a non-display area. The non-display area includes a signal line, a connecting line and a metal contact. The connecting line is formed in a first patterned metal layer. The signal line and the metal contact are formed in a second patterned metal layer. The connecting line is connected to the signal line by a first through-hole, and the connecting line is connected to the metal contact by a second through-hole. Furthermore, a method of fabricating the thin film transistor array substrate is also disclosed.
    Type: Grant
    Filed: August 19, 2012
    Date of Patent: January 6, 2015
    Assignee: E Ink Holdings Inc.
    Inventors: Wen-Chung Tang, Fang-An Shu, Yao-Chou Tsai, Ted-Hong Shinn
  • Patent number: 8878303
    Abstract: A method of optimizing a layout of an integrated circuit formed using fin-based cells of a standard cell library is provided. The method includes arranging cell rows of different track heights having standard cells. For each cell row, each of the standard cells includes sub-cell rows with sub-cells of one or more types. The sub-cells are interchangeable with one another to modify a device characteristic of the standard cell. The method also includes evaluating the integrated circuit to determine whether a performance metric of the integrated circuit has been satisfied. The method also includes identifying one or more standard cells to modify a device characteristic of the standard cell for satisfying the performance metric of the integrated circuit. The method further includes modifying the one or more standard cells until the performance metric of the integrated circuit is satisfied.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: November 4, 2014
    Assignee: Broadcom Corporation
    Inventors: Mehdi Hatamian, Paul Penzes
  • Patent number: 8847226
    Abstract: A transistor includes a substrate. A first electrically conductive material layer is positioned on the substrate. A second electrically conductive material layer is in contact with and positioned on the first electrically conductive material layer. The second electrically conductive material layer includes a reentrant profile. The second electrically conductive material layer also overhangs the first electrically conductive material layer.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: September 30, 2014
    Assignee: Eastman Kodak Company
    Inventors: Lee W. Tutt, Shelby F. Nelson
  • Patent number: 8779426
    Abstract: A thin film transistor for increasing the conductivity of a channel region and suppressing the leakage current of a back channel region, and a display device including the thin film transistor, are discussed. According to an embodiment, the thin film transistor includes a gate electrode arranged on a substrate, a source electrode and a drain electrode spaced from each other on the substrate, a gate insulating film to insulate the gate electrode from the source electrode and the drain electrode, and a semiconductor layer insulated from the gate electrode through the gate insulating film, the semiconductor layer including a channel region and a back channel region, the semiconductor layer made of (In2O3)x(Ga2O3)y(ZnO)z(0?x?5, 0?y?5, 0?z?5), wherein X or Z is greater than Y in the channel region of the semiconductor layer, and Y is greater than X and Z in the back channel region of the semiconductor layer.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: July 15, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Jae-Seok Heo, Ji-Yeon Seo
  • Patent number: 8766367
    Abstract: A textured thin film transistor is comprised of an insulator sandwiched between a textured gate electrode and a semi-conductor. A source electrode and drain electrode are fabricated on a surface of the semi-conductor. The textured gate electrode is fabricated such that a surface is modified in its texture and/or geometry, such modifications affecting the transistor current.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: July 1, 2014
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Sanjiv Sambandan, Robert A. Street
  • Patent number: 8742421
    Abstract: An object of the present invention is to provide a display device which can be manufactured with usability of a material improved and with a manufacturing step simplified and to provide a manufacturing technique thereof. One feature of a display device of the present invention is to comprise an insulating layer having an opening, a first conductive layer formed in the opening, and a second conductive layer formed over the insulating layer and the first conductive layer, wherein the first conductive layer is wider and thicker than the second conductive layer, and the second conductive layer is formed by spraying a droplet including a conductive material.
    Type: Grant
    Filed: November 29, 2004
    Date of Patent: June 3, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideaki Kuwabara, Shinji Maekawa, Gen Fujii, Toshiyuki Isa
  • Patent number: 8729557
    Abstract: Disclosed is an electroluminescence device having a substrate, a thin film transistor over the substrate, an insulating film over the thin film transistor, an electroluminescence element over the insulating film, a passivation film over the electroluminescence element, and a counter substrate over the passivation film. The electroluminescence element is configured to emit light through the counter substrate, and a space between the substrate and the counter substrate is filled with a filler. The electroluminescence device is featured by the tapered side surface of a gate electrode of the thin film transistor.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: May 20, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koji Ono, Hideomi Suzawa, Tatsuya Arao
  • Patent number: 8723268
    Abstract: A finFET block architecture uses end-to-end finFET blocks in which the fin lengths are at least twice the contact pitch, whereby there is enough space for interlayer connectors to be placed on the proximal end and the distal end of a given semiconductor fin, and on the gate element on the given semiconductor fin. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. Interlayer connectors can be aligned over corresponding semiconductor fins which connect to gate elements.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: May 13, 2014
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Deepak D. Sherlekar
  • Patent number: 8653565
    Abstract: Various aspects of the technology includes a quad semiconductor power and/or switching FET comprising a pair of control/sync FET devices. Current may be distributed in parallel along source and drain fingers. Gate fingers and pads may be arranged in a serpentine configuration for applying gate signals to both ends of gate fingers. A single continuous ohmic metal finger includes both source and drain regions and functions as a source-drain node. A set of electrodes for distributing the current may be arrayed along the width of the source and/or drain fingers and oriented to cross the fingers along the length of the source and drain fingers. Current may be conducted from the electrodes to the source and drain fingers through vias disposed along the surface of the fingers. Heat developed in the source, drain, and gate fingers may be conducted through the vias to the electrodes and out of the device.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: February 18, 2014
    Assignee: Sarda Technologies, Inc.
    Inventor: James L. Vorhaus
  • Patent number: 8643106
    Abstract: A transistor capable of adjusting a threshold value is obtained by adjusting an impurity concentration of a silicon substrate supporting an SOI layer and by controlling a thickness of a buried insulating layer formed on a surface of the silicon substrate in contact with the SOI layer.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: February 4, 2014
    Assignees: National University Corporation Tohoku University, Foundation for Advancement of International Science
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Cheng Weitao
  • Patent number: 8643021
    Abstract: A semiconductor display device is formed including an interlayer insulating. Specifically, a TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is formed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does. Thereafter, the gate insulating film and the two layers of the nitrogen-containing inorganic insulating films are partially etched away in the opening of the organic resin film to expose the active layer of the TFT.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: February 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Murakami, Masahiko Hayakawa, Kiyoshi Kato, Mitsuaki Osame, Takashi Hirosure, Saishi Fujikawa
  • Patent number: 8629500
    Abstract: An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric (GD1) in comparison with other transistors (T2) on the same integrated circuit arrangement (10). As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions (D1, S1) of the tunnel field effect transistor.
    Type: Grant
    Filed: December 9, 2005
    Date of Patent: January 14, 2014
    Assignee: Infineon Technologies AG
    Inventors: Juergen Holz, Ronald Kakoschke, Thomas Nirschl, Christian Pacha, Klaus Schruefer, Thomas Schulz, Doris Schmitt-Landsiedel
  • Patent number: 8629512
    Abstract: The description relates to a gate stack of a fin field effect transistor (FinFET). An exemplary structure for a FinFET includes a substrate including a first surface and an insulation region covering a portion of the first surface, where a top of the insulation region defines a second surface. The FinFET further includes a fin disposed through an opening in the insulation region to a first height above the second surface, where a base of an upper portion of the fin is broader than a top of the upper portion, wherein the upper portion has first tapered sidewalls and a third surface. The FinFET further includes a gate dielectric covering the first tapered sidewalls and the third surface and a conductive gate strip traversing over the gate dielectric, where the conductive gate strip has second tapered sidewalls along a longitudinal direction of the fin.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 8609522
    Abstract: A process for producing a conducting electrode on a substrate, including: depositing a layer made of a dielectric; depositing a protective layer made of the nitride of a metal on the dielectric layer; depositing a functionalization layer made of a material including a chemical species, such that the free enthalpy of formation of the nitride of the species is less, in absolute value, than the free enthalpy of formation of the nitride of the metal of the protective layer over the temperature range between 0° C. and 1200° C.; and annealing the assembly including the protective layer and the funtionalization layer so that the species diffuse from the functionalization layer into the protective layer and the nitrogen atoms migrate from the protective layer into the functionalization layer.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: December 17, 2013
    Assignee: Commissariat à l'énergie atomique et aux ènergies alternatives
    Inventors: Remy Gassilloud, François Martin
  • Patent number: 8569767
    Abstract: Disclosed is an electroluminescence device having a substrate, a thin film transistor over the substrate, an insulating film over the thin film transistor, an electroluminescence element over the insulating film, a passivation film over the electroluminescence element, and a counter substrate over the passivation film. The electroluminescence element is configured to emit light through the counter substrate, and a space between the substrate and the counter substrate is filled with a filler. The electroluminescence device is featured by the tapered side surface of a gate electrode of the thin film transistor.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: October 29, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koji Ono, Hideomi Suzawa, Tatsuya Arao
  • Patent number: 8551822
    Abstract: A method for manufacturing a substrate for a flat panel display device is disclosed. The present method uses photolithography with four masks to manufacture a TFT-LCD. After the third half-tone mask is used, the manufacturing of the TFTs and the defining of the pixel area of the substrate can be completed. The present method can avoid the alignment deviation and the generation of parasitic capacitance happened on the substrate made through the conventional photolithography with five masks. Therefore, the present method can reduce the costs and increase the yield. Moreover, the substrate for the TFT-LCD made by the present method can define a channel region in the semiconductor layer after the second half-tone mask. Hence, the subsequent manufacturing for forming a transparent conductive layer, a source, and a drain can be achieved by wet etching to effectively reduce the non-homogeneous etching for the channel region in the semiconductor layer.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: October 8, 2013
    Assignee: Quanta Display Inc.
    Inventor: Chun-Hao Tung
  • Patent number: 8536579
    Abstract: The invention relates to an electronic device including a sequence of a first thin film transistor (TFT) and a second TFT, the first TFT including a first set of electrodes separated by a first insulator, the second TFT comprising a second set of electrodes separated by a second insulator, wherein the first set of electrodes and the second set of electrodes are formed from a first shared conductive layer and a second shared conductive layer, the first insulator and the second insulator being formed by a shared dielectric layer. The invention further relates to a method of manufacturing an electronic device.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: September 17, 2013
    Assignee: Creator Technology B.V.
    Inventors: Christoph Wilhelm Sele, Monica Johanna Beenhakkers, Gerwin Hermanus Gelinck, Nicolaas Aldegonda Jan Maria Van Aerle, Hjalmar Edzer Ayco Huitema
  • Patent number: 8536660
    Abstract: A semiconductor structure includes a first MOS device including a first gate, and a second MOS device including a second gate. The first gate includes a first high-k dielectric over a semiconductor substrate; a second high-k dielectric over the first high-k dielectric; a first metal layer over the second high-k dielectric, wherein the first metal layer dominates a work-function of the first MOS device; and a second metal layer over the first metal layer. The second gate includes a third high-k dielectric over the semiconductor substrate, wherein the first and the third high-k dielectrics are formed of same materials, and have substantially a same thickness; a third metal layer over the third high-k dielectric, wherein the third metal layer and the second metal layer are formed of same materials, and have substantially a same thickness; and a fourth metal layer over the third metal layer.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: September 17, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Peng-Fu Hsu, Yong-Tian Hou, Ssu-Yi Li, Kuo-Tai Huang, Mong Song Liang
  • Patent number: 8536651
    Abstract: A multi-gate transistor having a plurality of sidewall contacts and a fabrication method that includes forming a semiconductor fin on a semiconductor substrate and etching a trench within the semiconductor fin, depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench; and forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer. The method further includes removing exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer, forming a high-k material liner along sidewalls of the channel region in the semiconductor fin, forming a metal gate stack within the etched trench, and forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: September 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Dechao Guo, Shu-Jen Han, Chung-Hsun Lin
  • Patent number: 8525342
    Abstract: A stacked integrated circuit (IC) may be manufactured with a second tier wafer bonded to a double-sided first tier wafer. The double-sided first tier wafer includes back-end-of-line (BEOL) layers on a front and a back side of the wafer. Extended contacts within the first tier wafer connect the front side and the back side BEOL layers. The extended contact extends through a junction of the first tier wafer. The second tier wafer couples to the front side of the first tier wafer through the extended contacts. Additional contacts couple devices within the first tier wafer to the front side BEOL layers. When double-sided wafers are used in stacked ICs, the height of the stacked ICs may be reduced. The stacked ICs may include wafers of identical functions or wafers of different functions.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: September 3, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Arvind Chandrasekaran, Brian Henderson
  • Patent number: 8525183
    Abstract: A semiconductor display device is formed including an interlayer insulating. Specifically, a TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is formed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does. Thereafter, the gate insulating film and the two layers of the nitrogen-containing inorganic insulating films are partially etched away in the opening of the organic resin film to expose the active layer of the TFT.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: September 3, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Murakami, Masahiko Hayakawa, Kiyoshi Kato, Mitsuaki Osame, Takashi Hirosure, Saishi Fujikawa
  • Patent number: 8497511
    Abstract: An array substrate includes scan lines and data lines defining pixel structures. Each pixel structure includes a first TFT, a second TFT and a pixel electrode. The first TFT includes a first gate connected to the scan line, a first source disposed above and partially overlapping the first gate, and a first drain disposed above the first gate. An end of the first source is connected to the data line. The first drain has at least one first concavity in which the first source is disposed partially. The second TFT includes a second gate connected to the scan line, a second source disposed above the second gate and connected to the first drain, and a second drain disposed above and partially overlapping the second gate. The second source has at least one second concavity in which the second drain is disposed partially. The pixel electrode connects to the second drain.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: July 30, 2013
    Assignee: E Ink Holdings Inc.
    Inventors: Chuan-Feng Liu, Chi-Ming Wu, Chia-Jen Chang
  • Patent number: 8470647
    Abstract: There has been a problem that the manufacturing process is complicated and the number of processes is increased when a TFT with an LDD structure or a TFT with a GOLD structure is formed. In a method of manufacturing a semiconductor device, after low concentration impurity regions (24, 25) are formed in a second doping process, a width of the low concentration impurity region which is overlapped with the third electrode (18c) and a width of the low concentration impurity region which is not overlapped with the third electrode can be freely controlled by a fourth etching process. Thus, in a region overlapped with the third electrode, a relaxation of electric field concentration is achieved and then a hot carrier injection can be prevented. And, in the region which is not overlapped with the third electrode, the off-current value can be suppressed.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: June 25, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Koji Ono, Toru Takayama, Tatsuya Arao, Shunpei Yamazaki
  • Patent number: 8466465
    Abstract: Disclosed is a thin film transistor which has an oxide semiconductor as an activation layer, a method of manufacturing the same and a flat panel display device having the same. The thin film transistor includes an oxide semiconductor layer formed on a substrate and including a channel region, a source region and a drain region, a gate electrode insulated from the oxide semiconductor layer by a gate insulating film, and source electrode and drain electrode which are coupled to the source region and the drain region, respectively. The oxide semiconductor layer includes a first layer portion and a second layer portion. The first layer portion has a first thickness and a first carrier concentration, and the second layer portion has a second thickness and a second carrier concentration. The second carrier concentration is lower than the first carrier concentration.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: June 18, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jong-Han Jeong, Tae-Kyung Ahn, Jae-Kyeong Jeong, Jin-Sung Park, Hun-Jung Lee, Hyun-Soo Shin, Yeon-Gon Mo
  • Patent number: 8461596
    Abstract: The present invention has an object to provide an active-matrix liquid crystal display device that realizes the improvement in productivity as well as in yield. In the present invention, a laminate film comprising the conductive film comprising metallic material and the second amorphous semiconductor film containing an impurity element of one conductivity type and the amorphous semiconductor film is selectively etched with the same etching gas to form a side edge of the first amorphous semiconductor film 1001 into a taper shape. Thereby, a coverage problem of a pixel electrode 1003 can be solved and an inverse stagger type TFT can be completed with three photomask.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: June 11, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Yoshihiro Kusuyama, Shunpei Yamazaki
  • Patent number: 8445935
    Abstract: A semiconductor apparatus includes a substrate having at least one terminal, a thin semiconductor film including at least one semiconductor device, the thin semiconductor film being disposed and bonded on the substrate; and an individual interconnecting line formed as a thin conductive film extending from the semiconductor device in the thin semiconductor film to the terminal in the substrate, electrically connecting the semiconductor device to the terminal. Compared with conventional semiconductor apparatus, the invented apparatus is smaller and has a reduced material cost.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: May 21, 2013
    Assignee: Oki Data Corporation
    Inventors: Mitsuhiko Ogihara, Hiroyuki Fujiwara, Masaaki Sakuta, Ichimatsu Abiko
  • Patent number: 8405081
    Abstract: An organic thin field transistor is disclosed. The organic thin field transistor includes a first and a second insulting layers, a metal structure and an organic layer serving as an active layer. Materials of the first and the second insulting layers are different, and by performing an etching process, a surface of the metal structure and a surface of the second insulting layer are effectively aligned. Because of the high flatness of the surface of the metal structure and the second insulting layer, a continuous film-forming property and crystallinity of the active layer of the organic thin field transistor are improved, so as to achieve a better the electrical characteristic.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: March 26, 2013
    Assignee: National Taiwan University of Science and Technology
    Inventors: Ching-Lin Fan, Yu-Zuo Lin, Chao-Hung Huang
  • Patent number: 8338256
    Abstract: A multi-gate transistor having a plurality of sidewall contacts and a fabrication method that includes forming a semiconductor fin on a semiconductor substrate and etching a trench within the semiconductor fin, depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench; and forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer. The method further includes removing exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer, forming a high-k material liner along sidewalls of the channel region in the semiconductor fin, forming a metal gate stack within the etched trench, and forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: December 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Dechao Guo, Shu-Jen Han, Chung-Hsun Lin
  • Patent number: 8329520
    Abstract: An island-shaped single crystal semiconductor layer whose top surface has a plane within ±10° from a {211} plane is formed on an insulating surface; a non-single-crystal semiconductor layer is formed in contact with the top surface and a side surface of the single crystal semiconductor layer and on the insulating surface; the non-single-crystal semiconductor layer is irradiated with laser light to melt the non-single-crystal semiconductor layer, and to crystallize the non-single-crystal semiconductor layer formed on the insulating surface with use of the single crystal semiconductor layer as a seed crystal, so that a crystalline semiconductor layer is formed. A semiconductor device having an n-channel transistor and a p-channel transistor formed with use of the crystalline semiconductor layer is provided.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: December 11, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Masahiro Takahashi, Takuya Hirohashi
  • Patent number: 8269221
    Abstract: Provided is a thin film device and an associated method of making a thin film device. For example, a thin film transistor with nano-gaps in the gate electrode. The method involves providing a substrate. Upon the substrate are then provided a plurality of parallel spaced electrically conductive strips. A plurality of thin film device layers are then deposited upon the conductive strips. A 3D structure is provided upon the plurality of thin film device layers, the structure having a plurality of different heights. The 3D structure and the plurality of thin film device layers are then etched to define a thin film device, such as for example a thin film transistor that is disposed above at least a portion of the conductive strips.
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: September 18, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Ping Mei, Albert Jeans, Carl Taussig
  • Patent number: 8263451
    Abstract: A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: September 11, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Chang Su, Tsz-Mei Kwok, Hsien-Hsin Lin, Hsueh-Chang Sung, Yi-Fang Pai, Kuan-Yu Chen
  • Patent number: 8188472
    Abstract: A thin film transistor (TFT), a method of manufacturing the TFT, and a flat panel display comprising the TFT are provided. The TFT includes a gate, a gate insulating layer that contacts the gate, a channel layer that contacts the gate insulating layer and faces the gate with the gate insulating layer therebetween, a source that contacts an end of the channel layer; and a drain that contacts an other end of the channel layer, wherein the channel layer is an amorphous oxide semiconductor layer, and each of the source and the drain is a conductive oxide layer comprising an oxide semiconductor layer having a conductive impurity in the oxide semiconductor layer. A low resistance metal layer can further be included on the source and drain. A driving circuit of a unit pixel of a flat panel display includes the TFT.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: May 29, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-chul Park, Chang-jung Kim, Sun-il Kim, I-hun Song, Young-soo Park
  • Patent number: 8174012
    Abstract: An organic light emitting diode display device (OLED display device) having uniform electrical characteristics and a method of manufacturing the same.
    Type: Grant
    Filed: November 6, 2007
    Date of Patent: May 8, 2012
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventors: Jong-Hyun Choi, Kyung-Jin Yoo
  • Patent number: 8148724
    Abstract: A liquid crystal display device includes a gate line and a data line on a substrate crossing each other to define a pixel region; a thin film transistor in the pixel region and connected to the gate line and the data line; a pixel electrode in the pixel region and connected to the thin film transistor; and a gate pad at an end of the gate line and a data pad at an end of the data line, at least one of the gate pad and the data pad including: a pad electrode including at least one pad contact hole therein along with a passivation layer, the passivation layer on the pad electrode, at least one side of the pad contact hole having an uneven shape in plane; and a pad electrode terminal contacting inner side surfaces of the pad electrode surrounding the pad contact hole.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: April 3, 2012
    Assignee: LG Display Co., Ltd.
    Inventors: Chang-Deok Lee, Hyung-Beom Shin, Seok Kim
  • Patent number: 8138544
    Abstract: A castellated-gate MOSFET tetrode device capable of fully depleted operation is disclosed. The device includes a semiconductor substrate region having an upper portion with a top surface and a lower portion with a bottom surface. A source region and a drain region are formed in the semiconductor substrate region, with adjoined primary and secondary channel-forming regions also disposed therein between the source and drain regions, thereby forming an integrated cascade structure. Trench isolation insulator islands, having upper and lower surfaces, surround the source and drain regions as well as the channel-forming regions. Both the primary and secondary channel-forming regions include pluralities of thin, spaced, vertically-orientated semiconductor channel elements that span longitudinally along the device between the source and drain regions.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: March 20, 2012
    Inventor: John James Seliskar
  • Patent number: 8129721
    Abstract: The invention primarily provides gate electrodes and gate wirings permitting large-sized screens for active matrix-type display devices, wherein, in order to achieve this object, the construction of the invention is a semiconductor device having, on the same substrate, a pixel TFT provided in a display region and a driver circuit TFT provided around the display region, wherein the gate electrodes of the pixel TFT and the driver circuit TFT are formed from a first conductive layer, the gate electrodes are in electrical contact through connectors with gate wirings formed from a second conductive layer, and the connectors are provided outside the channel-forming regions of the pixel TFT and the driver circuit TFT.
    Type: Grant
    Filed: April 3, 2006
    Date of Patent: March 6, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Toru Takayama, Toshiji Hamatani
  • Patent number: 8120039
    Abstract: In a semiconductor device, typically an active matrix display device, the structure of TFTs arranged in the respective circuits are made suitable in accordance with the function of the circuit, and along with improving the operating characteristics and the reliability of the semiconductor device, the manufacturing cost is reduced and the yield is increased by reducing the number of process steps.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: February 21, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koji Ono, Hideomi Suzawa, Tatsuya Arao
  • Patent number: 8093585
    Abstract: Each TFT for driving each of a plurality of pixels arranged in a matrix-like configuration is configured using a stagger-type polycrystalline-Si TFT. A gate electrode, which is composed of a high-heat-resistant material capable of resisting high temperature at the time of polycrystalline-Si film formation, is disposed at a lower layer as compared with the polycrystalline-Si layer that forms a channel of each TFT. A gate line, which is composed of a low-resistance material, is disposed at an upper layer as compared with the polycrystalline-Si layer. The gate electrode and the gate line are connected to each other via a through-hole bored in a gate insulation film. Respective configuration components of each organic electro-luminescent element are partially co-used at the time of the line formation, thereby suppressing an increase in the steps, processes, and configuration components.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: January 10, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Etsuko Nishimura, Masatoshi Wakagi, Kenichi Onisawa, Mieko Matsumura
  • Patent number: 8049218
    Abstract: A TFT LCD array substrate and a manufacturing method thereof. The TFT LCD array substrate comprises a substrate. A gate line and a gate electrode that is formed integrally with the gate line are formed on the substrate. A first insulating layer and a semiconductor layer are formed sequentially on the gate line and the gate electrode. A second insulting layer covers sidewalls of the gate line and the gate electrode, the first insulating layer, and the semiconductor layer. An etching stop layer is formed on the semiconductor layer and exposes a part of the semiconductor layer on both sides of the etching stop layer. The TFT LCD of the present invention can be manufactured with a four-mask process.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: November 1, 2011
    Assignee: Beijing Boe Optoelectronics Technology Co., Ltd.
    Inventors: Zhangtao Wang, Haijun Qiu, Tae Yup Min, Seung Moo Rim