Abstract: A method of fabricating a semiconductor device includes forming an interlayer dielectric on a substrate, the interlayer dielectric including first and second openings respectively disposed in first and second regions formed separately in the substrate; forming a first conductive layer filling the first and second openings; etching the first conductive layer such that a bottom surface of the first opening is exposed and a portion of the first conductive layer in the second opening remains; and forming a second conductive layer filling the first opening and a portion of the second opening.

Abstract: Embodiments of a Nickel-rich (Ni-rich) Schottky contact for a semiconductor device and a method of fabrication thereof are disclosed. Preferably, the semiconductor device is a radio frequency or power device such as, for example, a High Electron Mobility Transistor (HEMT), a Schottky diode, a Metal Semiconductor Field Effect Transistor (MESFET), or the like. In one embodiment, the semiconductor device includes a semiconductor body and a Ni-rich Schottky contact on a surface of the semiconductor body. The Ni-rich Schottky contact includes a multilayer Ni-rich contact metal stack. The semiconductor body is preferably formed in a Group III nitride material system (e.g., includes one or more Gallium Nitride (GaN) and/or Aluminum Gallium Nitride (AlGaN) layers). Because the Schottky contact is Ni-rich, leakage through the Schottky contact is substantially reduced.

Abstract: A method of forming a memory device includes forming a first interlayer insulating layer on a semiconductor substrate, forming a first electrode in the first interlayer insulating layer, the first electrode having a top surface of a rectangular shape extending in a first direction, and forming a variable resistance pattern on the first electrode, the variable resistance pattern having a bottom surface of a rectangular shape extending in a second direction crossing the first direction, the bottom surface of the variable resistance pattern contacting the first electrode, wherein the area of contact between the lower electrode and the variable resistance pattern is substantially equal to a multiplication of a minor axis length of a top surface of the first electrode and a minor axis length of a bottom surface of the variable resistance pattern.

Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.

Abstract: Provided is a semiconductor device. The semiconductor device includes a first insulation layer on a semiconductor substrate, the first insulation layer including a lower metal line, a metal head pattern on the first insulation layer, the metal head pattern including an inclined side surface, a thin film resistor pattern on the metal head pattern, a second insulation layer on the metal head pattern and the thin film resistor pattern, an upper metal line on the second insulation layer, a first via connecting the lower metal line to the upper metal line, and a second via connecting the metal head pattern to the upper metal line.

Abstract: An object of the present invention is to solve problems in that aluminum electrodes, aluminum wires, and I/O terminals are corroded by corrosive gasses when a pressure of a pressure medium containing corrosive matters such as exhaust gas is measured with a semiconductor sensor; and improve not only the corrosion resistance of the sensor chip but also the corrosion resistance of the portion particularly functioning as the pressure receiver. Each of the aluminum electrodes that is likely to be corroded portions is prevented from being corroded by forming a titanium-tungsten layer and gold layer on the aluminum electrode. The connecting wires are prevented from being corroded by corrosive matters by using gold wires. The I/O terminals are also prevented from being corroded by applying gold plating.

Abstract: A method of forming a memory device includes forming a first interlayer insulating layer on a semiconductor substrate, forming a first electrode in the first interlayer insulating layer, the first electrode having a top surface of a rectangular shape extending in a first direction, and forming a variable resistance pattern on the first electrode, the variable resistance pattern having a bottom surface of a rectangular shape extending in a second direction crossing the first direction, the bottom surface of the variable resistance pattern contacting the first electrode, wherein the area of contact between the lower electrode and the variable resistance pattern is substantially equal to a multiplication of a minor axis length of a top surface of the first electrode and a minor axis length of a bottom surface of the variable resistance pattern.

Abstract: A semiconductor device equipped with a metal thin film resistor is disclosed. The semiconductor device includes a second interlayer insulating film formed on a first interlayer insulating film including a formation area of a wiring pattern. Connecting holes are formed in the second interlayer insulating film corresponding to both ends of the metal thin film resistor and the wiring pattern. An upper part of each connecting hole is formed in a taper shape. A sidewall is formed on the inner wall of each connecting hole. The metal thin film resistor is formed on the second interlayer insulating film between the connecting holes, inside of each connecting hole, and on the wiring pattern.

Abstract: An integrated circuit includes a U-shaped access device and a first line coupled to a first side of the access device. The integrated circuit includes a contact coupled to a second side of the access device and self-aligned dielectric material isolating the first line from the contact.

Abstract: A non-volatile memory array includes an array of phase-changeable memory elements that are electrically insulated from each other by at least a first electrically insulating region extending between the array of phase-changeable memory elements. The first electrically insulating region includes a plurality of voids therein. Each of these voids extends between a corresponding pair of phase-changeable memory cells in the non-volatile memory array and, collectively, the voids form an array of voids in the first electrically insulating region.

Abstract: An integrated circuit includes a diffusion layer, a first poly-silicon layer, and a second poly-silicon layer. The first poly-silicon layer is located on the diffusion layer to form a transistor. The second poly-silicon includes a first section and a second section. The first section of the second poly-silicon layer is located on the first poly-silicon layer to form a capacitor. The second section of the second poly-silicon layer is located on the diffusion layer to form a resistor.

Abstract: Non-volatile memories formed on a substrate and fabrication methods are disclosed. A bottom electrode comprising a metal layer is disposed on the substrate. A buffer layer comprising a LaNiO3 film is disposed over the metal layer. A resistor layer comprising a SrZrO3 film is disposed on the buffer layer. A top electrode is disposed on the resistor layer.

Abstract: Provided is a semiconductor device having an electric fuse structure which receives the supply of an electric current to be permitted to be cut without damaging portions around the fuse. An electric fuse is electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the supply of an electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.

Abstract: In an embodiment of the invention, an integrated circuit having a cell is provided. The cell may include a field effect transistor structure which includes a gate stack and a resistivity changing material structure disposed above the gate stack, wherein the resistivity changing material structure includes a resistivity changing material which is configured to change its resistivity in response to the application of an electrical voltage to the resistivity changing material structure.

Abstract: Provided is a semiconductor device having an electric fuse structure which receives the supply of an electric current to be permitted to be cut without damaging portions around the fuse. An electric fuse is electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the supply of an electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.

Abstract: A trench MOS type SiC semiconductor device includes a first conductivity semiconductor substrate, a first conductivity drift layer on the substrate, a second conductivity base layer on the drift layer, a first conductivity source layer on the base layer, a stripe shaped trench reaching from the surface of the source layer to the drift layer and having a gate electrode via a gate oxide film, a second conductivity layer on the bottom of the trench, and a second conductivity type region thereon on across-the-width side walls of at least one end of the trench, electrically coupling the second conductivity layer with the base layer. The device and method for manufacturing the same allow a low on-resistance without newly forming an electrode connected to the second conductivity layer even in the case of a device in which the second conductivity layer has to be grounded.

Abstract: An object of the present invention is to solve problems in that aluminum electrodes, aluminum wires, and I/O terminals are corroded by corrosive gasses when a pressure of a pressure medium containing corrosive matters such as exhaust gas is measured with a semiconductor sensor; and improve not only the corrosion resistance of the sensor chip but also the corrosion resistance of the portion particularly functioning as the pressure receiver. Each of the aluminum electrodes that is likely to be corroded portions is prevented from being corroded by forming a titanium-tungsten layer and gold layer on the aluminum electrode. The connecting wires are prevented from being corroded by corrosive matters by using gold wires. The I/O terminals are also prevented from being corroded by applying gold plating.

Abstract: A reliability of a semiconductor device having a phase-change memory is improved. A phase-change memory device has a bottom-electrode plug buried in an interlayer insulator that is provided on a main surface of a semiconductor substrate, an electric conductive material layer provided on an upper portion of the bottom-electrode plug and on the interlayer insulator, a phase-change material layer provided on the electric conductive material layer, and an upper-electrode plug provided on the phase-change material layer. The bottom-electrode plug and the upper-electrode plug which configure the phase-change memory device are provided at respective different positions in a plane of the semiconductor substrate.

Abstract: Provided are a semiconductor probe having a resistive tip, a method of fabricating the semiconductor probe, and a method of recording and reproducing information using the semiconductor probe. The semiconductor probe includes a tip and a cantilever. The tip is doped with first impurities. The cantilever has an end portion on which the tip is positioned. The tip includes a resistive area, and first and second semiconductor electrode areas. The resistive area is positioned at the peak of the tip and lightly doped with second impurities that are different from the first impurities. The first and second semiconductor electrode areas are heavily doped with the second impurities and contact the resistive area.

Abstract: A semiconductor device equipped with an integrated circuit including a metal thin-film-resistor object is disclosed. The semiconductor device includes a lower layer side insulator film formed on a semiconductor substrate, a metal wiring pattern formed on the lower layer side insulator film, an underground insulator film having a silicon oxide-film that contains at least phosphor, or phosphor and boron in the uppermost layer formed on the lower layer side insulator film and the metal wiring pattern, and a connection hole formed in the underground insulator film on the metal wiring pattern. The metal thin-film-resistor object is formed covering the underground insulator film, and inside of the connection hole, and is electrically connected to the metal wiring pattern in the connection hole.

Abstract: An electrode structure includes a first layer of conductive material and a dielectric layer formed on a surface of the first layer. An opening is formed in the dielectric layer to expose a portion of the surface of the first layer. A binding layer is formed on the dielectric layer and on the exposed portion of the surface of the first layer and a second layer of conductive material is formed on the conductive binding layer. The binding layer can be an oxide and the second layer a conductive material that is diffusible into an oxide. The electrode structure can be annealed to cause conductive material from the second layer to be chemisorbed into the binding layer to improve adhesion between the first and second layers. A programmable cell can be formed by forming a doped glass layer in the electrode structure.

Abstract: Disclosed are a high breakdown voltage semiconductor device and a method of manufacturing the same. According to the invention, an insulation spacer capable of substitute-performing functions of an inter-insulation film, a contact hole and a mask, etc. by a self-alignment and simplifying a general process for manufacturing a device is newly arranged in a part of a gate electrode pattern. Thus, it is possible to naturally reduce the number of masks required for the device manufacture. Accordingly, a manufacturer can easily avoid various problems caused due to an increase of the number of masks. Further, it is possible to minimize a morphology abnormality of each unit patterns due to a miss-alignment of the mask and to effectively reduce a size of the device to be finally completed.