Types Of Semiconductor Device (epo) Patents (Class 257/E29.166)
  • Patent number: 9000411
    Abstract: Various embodiments of the present invention are direct to nanoscale, reconfigurable, two-terminal memristor devices. In one aspect, a device (400) includes an active region (402) for controlling the flow of charge carriers between a first electrode (104) and a second electrode (106). The active region is disposed between the first electrode and the second electrode and includes a storage material. Excess mobile oxygen ions formed within the active region are stored in the storage material by applying a first voltage.
    Type: Grant
    Filed: January 6, 2009
    Date of Patent: April 7, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Zhiyong Li, Alexandre M. Bratkovski, Jianhua Yang
  • Patent number: 8975122
    Abstract: An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines substantially disposed above the oxide layer; a plurality of via plugs substantially in electrical contact with the word lines and, an anti-fuse dielectric material substantially disposed on side walls beside the bit lines and substantially in contact with the plurality of bit lines side wall anti-fuse dielectrics.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: March 10, 2015
    Assignee: Macronix International Co., Ltd.
    Inventor: Hsiang-Lan Lung
  • Patent number: 8951892
    Abstract: A disclosed method of fabricating a hybrid nanopillar device includes forming a mask on a substrate and a layer of nanoclusters on the hard mask. The hard mask is then etched to transfer a pattern formed by the first layer of nanoclusters into a first region of the hard mask. A second nanocluster layer is formed on the substrate. A second region of the hard mask overlying a second region of the substrate is etched to create a second pattern in the hard mask. The substrate is then etched through the hard mask to form a first set of nanopillars in the first region of the substrate and a second set of nanopillars in the second region of the substrate. By varying the nanocluster deposition steps between the first and second layers of nanoclusters, the first and second sets of nanopillars will exhibit different characteristics.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: February 10, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mark D. Hall, Mehul D. Shroff
  • Patent number: 8946857
    Abstract: A semiconductor device includes a semiconductor substrate, a heat generating device, and a heat radiating part. The heat generating device is provided on the semiconductor substrate, and the heat radiating part is provided above the heat generating device. The heat radiating part is thermally coupled with the semiconductor substrate through at least one contact part.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: February 3, 2015
    Assignees: Fujitsu Limited, Fujitsu Semiconductor Limited
    Inventors: Mitsuaki Igeta, Takashi Suzuki
  • Patent number: 8900906
    Abstract: In one embodiment, a method of forming a semiconductor device includes providing a substrate, forming a sacrificial layer above the substrate layer, forming a first trench in the sacrificial layer, forming a first sidewall layer with a thickness of less than about 50 nm on a first sidewall of the first trench using atomic layer deposition (ALD), and removing the sacrificial layer.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: December 2, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Gary Yama, Fabian Purkl, Matthieu Liger, Matthias Illing
  • Patent number: 8883596
    Abstract: A semiconductor device with vertical channel transistors and a method of fabricating the same are provided. A method of fabricating the semiconductor device includes patterning a substrate to form a trench that defines an active region, forming a sacrificial pattern in a lower region of the trench, forming a spacer on an upper sidewall of the trench, recessing a top surface of the sacrificial pattern to form a window exposing a sidewall of the active region between the spacer and the sacrificial pattern, doping a sidewall of the trench through the window to form a doped region in the active region, and forming a wiring in the trench to be connected to the doped region.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seonghwee Cheong, Mansug Kang, Joon Kim, Kihong Nam, Gyuwan Choi
  • Patent number: 8866237
    Abstract: An embedded micro-electro-mechanical system (MEMS) (100) comprising a semiconductor chip (101) embedded in an insulating board (120), the chip having a cavity (102) including a radiation sensor MEMS (105), the opening (104) of the cavity at the chip surface covered by a plate (110) transmissive to the radiation (150) sensed by the MEMS. The plate surface remote from the cavity having a bare central area, to be exposed to the radiation sensed by the MEMS in the cavity, and a peripheral area covered by a metal film (111) touching the plate surface and a layer (112) of adhesive stacked on the metal film.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: October 21, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Christopher D. Manack, Frank Stepniak, Sreenivasan K. Koduri
  • Patent number: 8854033
    Abstract: A semiconductor device having a lateral semiconductor element includes a semiconductor substrate, a first electrode on the substrate, a second electrode on the substrate, and an isolation structure located in the substrate to divide the substrate into a first island and a second island electrically insulated from the first island. The lateral semiconductor element includes a main cell located in the first island and a sense cell located in the second island. The main cell causes a first current to flow between the first electrode and the second electrode so that the first current flows in a lateral direction along the surface of the substrate. The first current is detected by detecting a second current flowing though the sense cell.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: October 7, 2014
    Assignee: DENSO CORPORATION
    Inventors: Satoshi Shiraki, Norihito Tokura, Shigeki Takahashi, Masahiro Yamamoto, Akira Yamada, Hiroyasu Kudo, Youichi Ashida, Akio Nakagawa
  • Patent number: 8853745
    Abstract: A semiconductor structure, comprising: a substrate; a seed layer over an upper surface of the substrate; a semiconductor layer disposed over the seed layer; a transistor device in the semiconductor layer; wherein the substrate has an aperture therein, such aperture extending from a bottom surface of the substrate and terminating on a bottom surface of the seed layer; and an opto-electric structure disposed on the bottom surface of the seed layer.
    Type: Grant
    Filed: January 20, 2009
    Date of Patent: October 7, 2014
    Assignee: Raytheon Company
    Inventors: Kamal Tabatabaie, Jeffrey R. LaRoche, Valery S. Kaper, John P. Bettencourt, Kelly P. Ip
  • Patent number: 8816450
    Abstract: A silicon structure of the present invention is provided with a silicon substrate (1) to become a base, and a plurality of fibrous projections (2) made of silicon dioxide and directly joined to a silicon-made surface (1a) of the silicon substrate (1). By arbitrarily constructing an area where these fibrous projections (2) are formed in a predetermined area, it is possible to render the area to have at least either hydrophilicity or water retentivity, so as to provide a silicon structure useful for a variety of devices.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: August 26, 2014
    Assignee: Panasonic Corporation
    Inventors: Masaya Nakatani, Hiroshi Ushio, Soichiro Hiraoka, Akiyoshi Oshima, Makoto Takahashi
  • Patent number: 8791690
    Abstract: A semiconductor device having a lateral semiconductor element includes a semiconductor substrate, a first electrode on the substrate, a second electrode on the substrate, and an isolation structure located in the substrate to divide the substrate into a first island and a second island electrically insulated from the first island. The lateral semiconductor element includes a main cell located in the first island and a sense cell located in the second island. The main cell causes a first current to flow between the first electrode and the second electrode so that the first current flows in a lateral direction along the surface of the substrate. The first current is detected by detecting a second current flowing though the sense cell.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: July 29, 2014
    Assignee: DENSO CORPORATION
    Inventors: Satoshi Shiraki, Norihito Tokura, Shigeki Takahashi, Masahiro Yamamoto, Akira Yamada, Hiroyasu Kudo, Youichi Ashida, Akio Nakagawa
  • Patent number: 8779531
    Abstract: A microelectromechanical system (MEMS) assembly includes at least one emission source; a top wafer having a plurality of side walls and a generally horizontal portion, the horizontal portion having a thickness between a first side and a directly opposed second side, at least one window in the horizontal portion extending between the first and second sides and a transmission membrane across the at least one window; and a bottom wafer having a first portion with a first substantially planar surface, an intermediate surface directly opposed to the first substantially planar surface, a second portion with a second substantially planar surface, the at least one emission source provided on the second substantially planar surface; where the top wafer bonds to the bottom wafer at the intermediate surface and encloses a cavity within the top wafer and the bottom wafer.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: July 15, 2014
    Assignee: UTC Fire & Security Corporation
    Inventors: Joseph V. Mantese, Antonio M. Vincitore
  • Patent number: 8759205
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device, wherein an amorphous semiconductor film comprising a microcrystal is annealed using a microwave, to crystallize the amorphous semiconductor film comprising the microcrystal using the microcrystal as a nucleus.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: June 24, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomonori Aoyama, Yusuke Oshiki, Kiyotaka Miyano
  • Patent number: 8735945
    Abstract: A semiconductor device includes a transistor array including a plurality of transistors each having a gate electrode extended in a first direction, the plurality of transistors being arranged in a second direction intersecting the first direction, and a pad electrode arranged in the first direction of the transistor array and electrically connected to source regions of the plurality of transistors.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: May 27, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masashi Shima, Kaoru Saigoh, Nobuhiro Misawa, Takao Sasaki
  • Publication number: 20140084414
    Abstract: Vertical meander inductors for small core voltage regulators and approaches to fabricating vertical meander inductors for small core voltage regulators are described. For example, a semiconductor die includes a substrate. An integrated circuit is disposed on an active surface of the substrate. An inductor is coupled to the integrated circuit. The inductor is disposed conformal with an insulating layer disposed on an essentially planar surface of the substrate. The insulating layer has an undulating topography.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Inventors: Christopher J. Jezewski, Kevin P. O'Brien
  • Patent number: 8674448
    Abstract: A static random-access memory circuit includes at least one access device including source and drain sections for a pass region, at least one pull-up device and at least one pull-down device including source-and-drain sections for a pull-down region. The static random-access memory circuit is configured with external resistivity (Rext) for the pull-down region to be lower than Rext for the pass region. Processes of achieving the static random-access memory circuit include source-and-drain epitaxy.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: March 18, 2014
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Willy Rachmady, Brian S. Doyle, Robert S. Chau
  • Publication number: 20140061823
    Abstract: A micro-electrochemical sensor contains magnetic compounds inserted within a substrate that exert a magnetic force of attraction on paramagnetic beads held in contact with an electrode. The magnetic compounds can be contained within a fluid that is introduced into a void in the substrate. The electrode can be spaced apart from the magnetic compounds by a dielectric multi-layer membrane. During the fabrication process, different layers within the membrane-electrode structure can be tuned to have compressive or tensile stress so as to maintain structural integrity of the membrane, which is thin compared with the size of the void beneath it. During a process of forming the structure of the sensor, the tensile stress in a TiW adhesion layer can be adjusted to offset a composite net compressive stress associated with the dielectric layers of the membrane. The membrane can also be used in forming both the electrode and the void.
    Type: Application
    Filed: August 28, 2012
    Publication date: March 6, 2014
    Applicant: STMICROELECTRONICS PTE LTD.
    Inventors: Shian-Yeu Kam, Tien-Choy Loh, Ying Yu, Fery Riswan, Frederic Sala
  • Publication number: 20140034909
    Abstract: A thermoelectric structure comprises a thin thermoelectric film extending in a plane between parallel first and second shorting bars. A plurality of curved ballistic scattering guides are formed in a magnetic field region of the thin thermoelectric film subjected to a local, substantially uniform, nonzero magnetic field normal to the plane of the thin thermoelectric film.
    Type: Application
    Filed: August 2, 2012
    Publication date: February 6, 2014
    Applicant: HAMILTON SUNDSTRAND CORPORATION
    Inventors: Joseph V. Mantese, Eric S. Landry, Slade R. Culp
  • Publication number: 20140027772
    Abstract: Wafers with chips thereon and corresponding chips are provided where test structures or parts thereof are provided in a peripheral chip area of the chip. Corresponding methods are also disclosed.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 30, 2014
    Applicant: Infineon Technologies AG
    Inventors: Markus ZUNDEL, Uwe SCHMALZBAUER
  • Patent number: 8624299
    Abstract: An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines substantially disposed above the oxide layer; a plurality of via plugs substantially in electrical contact with the word lines and, an anti-fuse dielectric material substantially disposed on side walls beside the bit lines and substantially in contact with the plurality of bit lines side wall anti-fuse dielectrics.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: January 7, 2014
    Assignee: Macronix International Co., Ltd.
    Inventor: Hsiang-Lan Lung
  • Publication number: 20140001432
    Abstract: A disclosed method of fabricating a hybrid nanopillar device includes forming a mask on a substrate and a layer of nanoclusters on the hard mask. The hard mask is then etched to transfer a pattern formed by the first layer of nanoclusters into a first region of the hard mask. A second nanocluster layer is formed on the substrate. A second region of the hard mask overlying a second region of the substrate is etched to create a second pattern in the hard mask. The substrate is then etched through the hard mask to form a first set of nanopillars in the first region of the substrate and a second set of nanopillars in the second region of the substrate. By varying the nanocluster deposition steps between the first and second layers of nanoclusters, the first and second sets of nanopillars will exhibit different characteristics.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Mark D. Hall, Mehul D. Shroff
  • Patent number: 8618629
    Abstract: Methods and apparatuses for matching impedances in a flip-chip circuit assembly are presented. An apparatus for matching impedances in a flip-chip circuit assembly may include a first circuit associated with a first die and a through silicon via (TSV) coupling the first circuit to a second circuit. The apparatus may further include a first impedance matching inductor interposed between the TSV and the second circuit. A method for matching impedances in a flip-chip circuit assembly may include providing a die having a first circuit, and forming a TSV over the die. The method may further include providing a second circuit and forming a first impedance matching inductor interposed between the TSV and second circuit.
    Type: Grant
    Filed: October 8, 2009
    Date of Patent: December 31, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Jonghae Kim, Jeong Hwan Yang, Matthew M. Nowak
  • Publication number: 20130341739
    Abstract: A package structure is provided, including: a substrate having a ground pad and an MEMS element; a lid disposed on the substrate for covering the MEMS element; a wire segment electrically connected to the ground pad; an encapsulant encapsulating the lid and the wire segment; and a circuit layer formed on the encapsulant and electrically connected to the wire segment and the lid so as to commonly ground the substrate and the lid, thereby releasing accumulated electric charges on the lid so as to improve the reliability of the MEMS system and reduce the number of I/O connections.
    Type: Application
    Filed: October 25, 2012
    Publication date: December 26, 2013
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Hong-Da Chang, Cheng-Hsiang Liu, Kuang-Wei Huang, Chun-Hung Lin, Hsin-Yi Liao
  • Patent number: 8604588
    Abstract: A semiconductor device including: a first resistance element formed of a first polysilicon layer that contains impurities; a second resistance element provided on a same surface as the first polysilicon layer, and formed of a second polysilicon layer that contains an equal amount of impurities to the first polysilicon layer; a first interlayer insulation film provided so as to cover the first resistance element and the second resistance element; and a first metal layer provided on the first interlayer insulation film so as to cover the second resistance element with the first interlayer insulation film disposed therebetween.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: December 10, 2013
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Kenichiro Kusano, Junko Azami
  • Publication number: 20130320480
    Abstract: A semiconductor device comprises an integrated circuit (IC) die having a top side and a back side. The circuit substrate includes a heat source circuit, a heat sensitive circuit, a package substrate coupled to the top side of the circuit substrate, and a plurality of thermally conductive through-silicon vias (TSVs) formed from the back side of the circuit substrate to near but not through the top side of the circuit substrate.
    Type: Application
    Filed: May 31, 2012
    Publication date: December 5, 2013
    Inventors: Michael B. Mcshane, Kevin J. Hess, Perry H. Pelley, Tab A. Stephens
  • Patent number: 8598659
    Abstract: A transistor device includes a lightly doped layer of semiconductor material of a first type and a body region of semiconductor material of a second type. A source region of the first type is formed in the body region, the source region being more doped than the lightly doped layer. A drain region of the first type is formed in the lightly doped layer, the drain region being more doped than the lightly doped layer. A drift region of the lightly doped layer is further provided disposed between the body region and the drain region. Additionally, a gate electrode is provided surrounding the drain region. The gate electrode is partially disposed over a thin oxide and partially over a thick oxide, wherein the gate electrode extended over the thick oxide from the thin oxide controls the electric field in the drift region to increase the avalanche breakdown of the drain region.
    Type: Grant
    Filed: October 26, 2005
    Date of Patent: December 3, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Chin Dixie Huang, Jeffrey A. Hintzman, Dennis James Schloeman, Hang Liao
  • Patent number: 8592942
    Abstract: A non-volatile semiconductor memory device having a memory cell in which operating potentials are few and the scale of the peripheral circuitry is reduced includes a select transistor having a source/drain on both sides of a channel of a semiconductor substrate and having a gate electrode disposed on the channel via a thick gate insulating film; an element isolation region formed on the semiconductor substrate in an area adjacent to the select transistor; an antifuse adjacent to the element isolation region, having a lower electrode formed on the semiconductor substrate and having an upper electrode disposed on the semiconductor substrate in an area between the element isolation region and lower electrode via a thin gate insulating film; and a connection contact electrically connecting the source and upper electrode and contacting the source and the upper electrode.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: November 26, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Noriaki Kodama, Kenichi Hidaka, Hiroyuki Kobatake, Takuji Onuma
  • Patent number: 8581251
    Abstract: The invention relates to the creation of a housing for an integrated circuit which makes it possible to detect physical ingression into said housing. The invention applies in particular to the protection of secrets which may possibly be contained in said integrated circuit, in the event of physical attack, for example by destroying the secrets contained in an integrated circuit in the event of ingression into the housing thereof.
    Type: Grant
    Filed: November 14, 2009
    Date of Patent: November 12, 2013
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Yann Yves René Loisel, Renaud Guigue, Christophe Jean Tremlet
  • Patent number: 8580584
    Abstract: A system and method of increasing productivity of OLED material screening includes providing a substrate that includes an organic semiconductor, processing regions on the substrate by combinatorially varying parameters associated with the OLED device production on the substrate, performing a first characterization test on the processed regions on the substrate to generate first results, processing regions on the substrate in a combinatorial manner by varying parameters associated with the OLED device production on the substrate based on the first results of the first characterization test, performing a second characterization test on the processed regions on the substrate to generate second results, and determining whether the substrate meets a predetermined quality threshold based on the second results.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: November 12, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Yun Wang, Tony P. Chiang, Chi-I Lang
  • Patent number: 8581263
    Abstract: An embodiment is a method and apparatus to induce flaw formation in nitride semiconductors. Regions of a thin film structure are selectively decomposed within a thin film layer at an interface with a substrate to form flaws in a pre-determined pattern within the thin film structure. The flaws locally concentrate stress in the pre-determined pattern during a stress-inducing operation. The stress-inducing operation is performed. The stress-inducing operation causes the thin film layer to fracture at the pre-determined pattern.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: November 12, 2013
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Clifford F. Knollenberg, William S. Wong, Christopher L. Chua
  • Patent number: 8575597
    Abstract: The use of liquid metal contacts for devices based on thermotunneling has been investigated. Electric and thermal characteristics of low wetting contact Hg/Si, and high wetting contacts Hg/Cu were determined and compared. Tunneling I-V characteristics for Hg/Si were obtained, while for Hg/Cu, I-V characteristics were ohmic. The tunneling I-V characteristic is explained by the presence of a nanogap between the contact materials. Heat conductance of high wetting and low wetting contacts were compared, using calorimeter measurements. Heat conductance of high wetting contact was 3-4 times more than of low wetting contact. Both electric and thermal characteristics of liquid metal contact indicated that it could be used for thermotunneling devices. To reduce the work function and make liquid metal more suitable for room temperature cooling, Cs was dissolved in liquid Hg. Work function as low as 2.6 eV was obtained.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: November 5, 2013
    Assignee: Borealis Technical Limited
    Inventors: Avto Tavkhelidze, Leri Tsakadze, Zaza Taliashvili, Larissa Jangidze, Rodney Thomas Cox
  • Patent number: 8558370
    Abstract: The present invention provides a semiconductor device which is not easily damaged by external local pressure. The present invention further provides a manufacturing method of a highly-reliable semiconductor device, which is not destroyed by external local pressure, with a high yield. A structure body, in which high-strength fiber of an organic compound or an inorganic compound is impregnated with an organic resin, is provided over an element substrate having a semiconductor element formed using a single crystal semiconductor region, and heating and pressure bonding are performed, whereby a semiconductor device is manufactured, to which the element substrate and the structure body in which the high-strength fiber of an organic compound or an inorganic compound is impregnated with the organic resin are fixed together.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: October 15, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Eiji Sugiyama, Yoshitaka Dozen, Hisashi Ohtani, Takuya Tsurume
  • Patent number: 8536564
    Abstract: An integrated field emission array for ion desorption includes an electrically conductive substrate; a dielectric layer lying over the electrically conductive substrate comprising a plurality of laterally separated cavities extending through the dielectric layer; a like plurality of conically-shaped emitter tips on posts, each emitter tip/post disposed concentrically within a laterally separated cavity and electrically contacting the substrate; and a gate electrode structure lying over the dielectric layer, including a like plurality of circular gate apertures, each gate aperture disposed concentrically above an emitter tip/post to provide a like plurality of annular gate electrodes and wherein the lower edge of each annular gate electrode proximate the like emitter tip/post is rounded. Also disclosed herein are methods for fabricating an integrated field emission array.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: September 17, 2013
    Assignee: Sandia Corporation
    Inventors: Paul J. Resnick, Kristin L. Hertz, Christopher Holland, David Chichester, Paul Schwoebel
  • Publication number: 20130234270
    Abstract: In one embodiment, a method of forming a semiconductor device includes providing a substrate, forming a sacrificial layer above the substrate layer, forming a first trench in the sacrificial layer, forming a first sidewall layer with a thickness of less than about 50 nm on a first sidewall of the first trench using atomic layer deposition (ALD), and removing the sacrificial layer.
    Type: Application
    Filed: March 8, 2012
    Publication date: September 12, 2013
    Applicant: ROBERT BOSCH GMBH
    Inventors: Gary Yama, Fabian Purkl, Matthieu Liger, Matthias Illing
  • Publication number: 20130221455
    Abstract: An embedded micro-electro-mechanical system (MEMS) (100) comprising a semiconductor chip (101) embedded in an insulating board (120), the chip having a cavity (102) including a radiation sensor MEMS (105), the opening (104) of the cavity at the chip surface covered by a plate (110) transmissive to the radiation (150) sensed by the MEMS. The plate surface remote from the cavity having a bare central area, to be exposed to the radiation sensed by the MEMS in the cavity, and a peripheral area covered by a metal film (111) touching the plate surface and a layer (112) of adhesive stacked on the metal film.
    Type: Application
    Filed: February 27, 2012
    Publication date: August 29, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Christopher D. Manack, Frank Stepniak, Sreenivasan K. Koduri
  • Patent number: 8519489
    Abstract: An embodiment relates a method comprising creating a reversible change in an electrical property by adsorption of a gas by a composition, wherein the composition comprises a noble metal-containing nanoparticle and a single walled carbon nanotube. Another embodiment relates to a method comprising forming a composition comprising a noble metal-containing nanoparticle and a single walled carbon nanotube and forming a device containing the said composition. Yet another method relates to a device comprising a composition comprising a noble metal-containing nanoparticle and a single walled carbon nanotube on a silicon wafer, wherein the composition exhibits a reversible change in an electrical property by adsorption of a gas by the composition.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: August 27, 2013
    Assignee: Indian Institute of Technology Madras
    Inventors: Pradeep Thalappil, Chandramouli Subramaniam
  • Patent number: 8519447
    Abstract: An ion sensitive sensor having an EIS structure, including: a semiconductor substrate, on which a layer of a substrate oxides is produced; an adapting or matching layer, which is prepared on the substrate oxide; a chemically stable, intermediate insulator, which is deposited on the adapting or matching layer; and an ion sensitive, sensor layer, which is applied on the intermediate insulator. The adapting or matching layer differs from the intermediate insulator and the substrate oxide in its chemical composition and/or structure. The adapting or matching layer and the ion sensitive, sensor layer each have an electrical conductivity greater than that of the intermediate insulator. There is an electrically conductive connection between the adapting or matching layer and the ion sensitive, sensor layer.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: August 27, 2013
    Assignee: Endress + Hauser Conducta Gesellschaft für Mess- und Regeltechnik mbH + Co. KG
    Inventor: Hendrik Zeun
  • Patent number: 8513745
    Abstract: A MEMS switch (1, 81), and methods of fabricating thereof, the switch comprising: a sealed cavity (24); and a membrane (26); wherein the sealed cavity (24) is defined in part by the membrane (26); and the membrane is a 5 metallic membrane (26), for example consisting of a single type of metal or metal alloy. The MEMS switch (1, 81) may comprise a top electrode (30), for example extending into the cavity (24), located in a hole (32) in the metallic membrane (26). Fabrication may include providing a sacrificial layer (22) in a partly defined cavity (24). The bending stiffness of the membrane (26) may be 10 higher along an RF line (102) than along a line (104) perpendicular to the RF line (102), for example by virtue of the cavity (24) being elliptical.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: August 20, 2013
    Assignee: NXP B.V.
    Inventors: Peter Gerard Steeneken, Hilco Suy, Martijn Goossens, Olaf Wunnicke
  • Publication number: 20130187201
    Abstract: A sensor device includes a semiconductor chip. The semiconductor chip has a sensing region sensitive to mechanical loading. A pillar is mechanically coupled to the sensing region.
    Type: Application
    Filed: January 25, 2012
    Publication date: July 25, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Klaus Elian, Franz-Peter Kalz, Horst Theuss
  • Patent number: 8492744
    Abstract: Preferred embodiments of the invention provide semiconducting microcavity plasma devices. Preferred embodiments of the invention are microcavity plasma devices having at least two pn junctions, separated by a microcavity or microchannel and powered by alternate half-cycles of a time-varying voltage waveform. Alternate embodiments have a single pn junction. Microplasma is produced throughout the cavity between single or multiple pn junctions and a dielectric layer isolates the microplasma from the single or multiple pn junctions. Additional preferred embodiments are devices in which the spatial extent of the plasma itself or the n or p regions associated with a pn junction are altered by a third (control) electrode.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: July 23, 2013
    Assignees: The Board of Trustees of the University of Illinois, Acumen Scientific
    Inventors: J. Gary Eden, Paul Tchertchian, Clark J. Wagner, Steve Solomon, Robert Ginn
  • Patent number: 8487385
    Abstract: We describe the use of a high-quality-factor torsional resonator of microscale dimensions. The resonator has a paddle that is supported by two nanoscale torsion rods made of a very low thermal conductivity material, such as amorphous (“a-”) silicon. The body of the torsion paddle is coated with an infrared-absorbing material that is thin and light weight, but provides sufficient IR absorption for the applications. It may be placed above a reflecting material of similar dimensions to form a quarter wave cavity. Sensing of the response of the paddle to applied electromagnetic radiation provides a measure of the intensity of the radiation as detected by absorption, and the resulting temperature change, in the paddle.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: July 16, 2013
    Assignee: California Institute of Technology
    Inventor: Michael L. Roukes
  • Publication number: 20130168781
    Abstract: A microelectromechanical system (MEMS) assembly includes at least one emission source; a top wafer having a plurality of side walls and a generally horizontal portion, the horizontal portion having a thickness between a first side and a directly opposed second side, at least one window in the horizontal portion extending between the first and second sides and a transmission membrane across the at least one window; and a bottom wafer having a first portion with a first substantially planar surface, an intermediate surface directly opposed to the first substantially planar surface, a second portion with a second substantially planar surface, the at least one emission source provided on the second substantially planar surface; where the top wafer bonds to the bottom wafer at the intermediate surface and encloses a cavity within the top wafer and the bottom wafer.
    Type: Application
    Filed: December 28, 2011
    Publication date: July 4, 2013
    Applicant: UTC FIRE & SECURITY CORPORATION
    Inventors: Joseph V. Mantese, Antonio M. Vincitore
  • Patent number: 8471249
    Abstract: Carbon transistor devices having channels formed from carbon nanostructures, such as carbon nanotubes or graphene, and having charged monolayers to reduce parasitic resistance in un-gated regions of the channels, and methods for fabricating carbon transistor devices having charged monolayers to reduce parasitic resistance. For example, a carbon field effect transistor includes a channel comprising a carbon nanostructure formed on an insulating layer, a gate structure formed on the channel, a monolayer of DNA conformally covering the gate structure and a portion of the channel adjacent the gate structure, an insulating spacer conformally formed on the monolayer of DNA, and source and drain contacts connected by the channel.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: June 25, 2013
    Assignee: International Business Machines Corporation
    Inventors: Hsin-Ying Chiu, Shu-Jen Han, Hareem T. Maune
  • Patent number: 8470676
    Abstract: A multi-terminal programmable element. The programmable element includes a source electrode and a drain electrode on a base. The programmable element includes reference voltage contact that is not in contact with the source or drain electrode. The base includes a transition-metal oxide with oxygen vacancies for drifting under an applied electric field. Further, materials of the source electrode and the base are selected such that an interface of a source and/or drain electrode material and the transition metal oxide base material forms an energy barrier for electron injection from the electrode into the base material. The energy barrier has a height that depends on an oxygen vacancy concentration of the base material. Four non-volatile states are programmable into the programmable element.
    Type: Grant
    Filed: January 8, 2009
    Date of Patent: June 25, 2013
    Assignee: International Business Machines Corporation
    Inventors: Siegfried F. Karg, Gerhard Ingmar Meijer
  • Publication number: 20130153969
    Abstract: A structure for a metal-oxide-semiconductor field-effect transistor (MOSFET) sensor is provided. The structure includes a MOSFET, a sensing membrane, and a reference electrode. The reference electrode and the sensing membrane are formed on the first surface of the MOSFET and are arranged in such a way that the reference electrode and the sensing membrane are uniformly and electrically coupled to each other. Thus, the electric field between the sensing membrane and the reference electrode is uniformly distributed therebetween to stabilize the working signal of the MOSFET sensor.
    Type: Application
    Filed: March 13, 2012
    Publication date: June 20, 2013
    Applicant: National Chip Implementation Center National Applied Research Laboratories
    Inventors: Ying-Zong JUANG, Hann-Huei Tsai, Hsin-Hao Liao, Chen-Fu Lin
  • Patent number: 8466512
    Abstract: A method for producing a semiconductor device includes preparing a structure having a substrate, a planar semiconductor layer and a columnar semiconductor layer, forming a second drain/source region in the upper part of the columnar semiconductor layer, forming a contact stopper film and a contact interlayer film, and forming a contact layer on the second drain/source region. The step for forming the contact layer includes forming a pattern and etching the contact interlayer film to the contact stopper film using the pattern to form a contact hole for the contact layer and removing the contact stopper film remaining at the bottom of the contact hole by etching. The projection of the bottom surface of the contact hole onto the substrate is within the circumference of the projected profile of the contact stopper film formed on the top and side surface of the columnar semiconductor layer onto the substrate.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: June 18, 2013
    Assignee: Unisantis Electronics Singapore Pte Ltd.
    Inventors: Fujio Masuoka, Shintaro Arai, Hiroki Nakamura, Tomohiko Kudo, R. Ramana Murthy, Nansheng Shen, Kavitha Devi Buddharaju, Navab Singh
  • Patent number: 8461587
    Abstract: An ion-sensitive sensor with an EIS structure includes: a semiconductor substrate, on which a layer of a substrate oxide 103 is produced; an adapting or matching layer, which is prepared on the substrate oxide; a chemically stable intermediate insulator, which is deposited on the adapting or matching layer; and a sensor layer, which comprises a tantalum oxide or a tantalum oxynitride, and which is applied on the intermediate insulator; wherein the intermediate insulator comprises hafnium oxide or zirconium oxide or a mixture of zirconium oxide and hafnium oxide, and wherein the adapting or matching layer differs in its chemical composition and/or in its structure from the intermediate insulator and from the substrate oxide.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: June 11, 2013
    Assignee: Endress + Hauser Conducta Gesellschaft für Mess- und Regeltechnik mbH + Co. KG
    Inventors: Eberhard Kurth, Christian Kunath, Torsten Pechstein
  • Patent number: 8455927
    Abstract: To reduce the pixel size to the smallest dimensions and simplest form of operation, a pixel may be formed by using only one ion sensitive field-effect transistor (ISFET). This one-transistor, or 1T, pixel can provide gain by converting the drain current to voltage in the column. Configurable pixels can be created to allow both common source read out as well as source follower read out. A plurality of the 1T pixels may form an array, having a number of rows and a number of columns and a column readout circuit in each column. A cascoded device enabled during readout may be used to provide increased programmable gain.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: June 4, 2013
    Assignee: Life Technologies Corporation
    Inventor: Keith Fife
  • Patent number: 8450183
    Abstract: A method of manufacturing a power semiconductor device according to the present invention includes the steps of: (a) forming a silicon nitride film on a semiconductor substrate; (b) after the step (a), forming a ring-shaped trench along a peripheral portion of the semiconductor substrate 6; (c) forming a first silicon oxide film on an inner surface of the trench; (d) after the step (c), forming a second silicon oxide film on an entire surface of the semiconductor substrate to bury the trench; (e) planarizing the second silicon oxide film by using the silicon nitride film as a stopper; and (f) forming a third silicon oxide film in a region in which the silicon nitride film is removed.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: May 28, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ryoichi Fujii, Shigeto Honda, Atsushi Narazaki, Kaoru Motonami
  • Publication number: 20130119511
    Abstract: The present application discloses an inductor including a substrate, a first conductive line and a second conductive line formed over the substrate, a passivation layer formed over the first and the second conductive lines, and a bond wire coupling an end of the first conductive line and an end of the second conductive line. At least a portion of the at least one bond wire is positioned above an upper surface of the passivation layer. The first conductive line, the bond wire, and the second conductive line are connected to form a coil.
    Type: Application
    Filed: November 10, 2011
    Publication date: May 16, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Justin SHI, Eric SOENEN, Alan ROTH