Abstract: Semiconductor nano-devices, such as nano-probe and nano-knife devices, which are constructed using graphene films that are suspended between open cavities of a semiconductor structure. The suspended graphene films serve as electro-mechanical membranes that can be made very thin, from one or few atoms in thickness, to greatly improve the sensitivity and reliability of semiconductor nano-probe and nano-knife devices.

Abstract: A method of fabricating a FET device is provided which includes the following steps. Nanowires/pads are formed in a SOI layer over a BOX layer, wherein the nanowires are suspended over the BOX. A HSQ layer is deposited that surrounds the nanowires. A portion(s) of the HSQ layer that surround the nanowires are cross-linked, wherein the cross-linking causes the portion(s) of the HSQ layer to shrink thereby inducing strain in the nanowires. One or more gates are formed that retain the strain induced in the nanowires. A FET device is also provided wherein each of the nanowires has a first region(s) that is deformed such that a lattice constant in the first region(s) is less than a relaxed lattice constant of the nanowires and a second region(s) that is deformed such that a lattice constant in the second region(s) is greater than the relaxed lattice constant of the nanowires.

Abstract: An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.

Abstract: A thin film transistor (“TFT”) includes a gate electrode, a gate insulating layer, a source electrode, a drain electrode and a semiconductor layer. The gate insulating layer is disposed on the gate electrode. The source electrode is disposed on the gate insulating layer. The drain electrode is disposed on the gate insulating layer. The drain electrode is spaced apart from the source electrode. The semiconductor layer is disposed on the gate insulating layer. The semiconductor layer makes contact with a side surface of the source electrode and a side surface of the drain electrode.

Abstract: The carbon nanotube-based electronic and photonic devices are disclosed. The devices are united by the same technology as well as similar elements for their fabrication. The devices consist of the vertically grown semiconductor nanotube having two Schottky barriers at the nanotube ends and one Schottky barrier at the middle of the nanotube. Depending on the Schottky barrier heights and bias arrangements, the disclosed devices can operate either as transistors, CNT MESFET and CNT Hot Electron Transistor, or as a CNT Photon Emitter.

Abstract: A fin structure including a vertical alternating stack of a first isoelectric point material layer having a first isoelectric point and a second isoelectric material layer having a second isoelectric point less than the first isoelectric point is formed. The first and second isoelectric point material layers become oppositely charged in a solution with a pH between the first and second isoelectric points. Negative electrical charges are imparted onto carbon nanotubes by an anionic surfactant to the solution. The electrostatic attraction causes the carbon nanotubes to be selectively attached to the surfaces of the first isoelectric point material layer. Carbon nanotubes are attached to the first isoelectric point material layer in self-alignment along horizontal lengthwise directions of the fin structure. A transistor can be formed, which employs a plurality of vertically aligned horizontal carbon nanotubes as the channel.

Abstract: A method of patterning nanostructures comprising printing an ink comprising the nanostructures onto a solvent-extracting first surface such that a pattern of nanostructures is formed on the first surface.

Abstract: A semiconductor device includes a semiconductor island having at least one electrical dopant atom and encapsulated by dielectric materials including at least one dielectric material layer. At least two portions of the at least one dielectric material layer have a thickness less than 2 nm to enable quantum tunneling effects. A source-side conductive material portion and a drain-side conductive material portion abuts the two portions of the at least one dielectric material layer. A gate conductor is located on the at least one dielectric material layer between the source-side conductive material portion and the drain-side conductive material portion. The potential of the semiconductor island responds to the voltage at the gate conductor to enable or disable tunneling current through the two portions of the at least one dielectric material layer. Design structures for the semiconductor device are also provided.

Abstract: A method of modifying a wafer having semiconductor disposed on an insulator is provided and includes establishing first and second regions of the wafer with different initial semiconductor thicknesses, forming pairs of semiconductor pads connected via respective nanowire channels at each of the first and second regions and reshaping the nanowire channels into nanowires each having a respective differing thickness reflective of the different initial semiconductor thicknesses at each of the first and second regions.

Abstract: Techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided. In one aspect, a method of fabricating a FET includes the following steps. A doped substrate having a dielectric thereon is provided. At least one silicon (Si) nanowire is placed on the dielectric. One or more portions of the nanowire are masked off leaving other portions of the nanowire exposed. Epitaxial germanium (Ge) is grown on the exposed portions of the nanowire. The epitaxial Ge is interdiffused with Si in the nanowire to form SiGe regions embedded in the nanowire that introduce compressive strain in the nanowire. The doped substrate serves as a gate of the FET, the masked off portions of the nanowire serve as channels of the FET and the embedded SiGe regions serve as source and drain regions of the FET.

Abstract: A semiconductor device including a group III-V barrier and a method of manufacturing the semiconductor device, the semiconductor device including: a substrate, insulation layers formed to be spaced apart on the substrate, a group III-V material layer for filling the space between the insulation layers and having a portion protruding higher than the insulation layers, a barrier layer for covering the side and upper surfaces of the protruding portion of the group III-V material layer and having a bandgap larger than that of the group III-V material layer, a gate insulation film for covering the surface of the barrier layer, a gate electrode formed on the gate insulation film, and source and drain electrodes formed apart from the gate electrode. The overall composition of the group III-V material layer is uniform. The barrier layer may include a group III-V material for forming a quantum well.

Abstract: A thin film transistor includes a gate electrode configured to receive a control voltage, a source electrode insulated from the gate electrode, and configured to receive an input voltage, a drain electrode insulated from the gate electrode, and configured to receive an output voltage, at least two carbon nanotube patterns formed in a channel region between the source electrode and the drain electrode, wherein the carbon nanotube patterns are separated from each other, and at least one floating electrode connecting the two carbon nanotube patterns to each other.

Abstract: A 1D nanowire photodetector device includes a nanowire that is individually contacted by electrodes for applying a longitudinal electric field which drives the photocurrent. An intrinsic radial electric field to inhibits photo-carrier recombination, thus enhancing the photocurrent response. Circuits of 1D nanowire include groups of photodetectors addressed by their individual 1D nanowire electrode contacts. Placement of 1D nanostructures is accomplished with registration onto a substrate. A substrate is patterned with a material, e.g., photoresist, and trenches are formed in the patterning material at predetermined locations for the placement of 1D nanostructures. The 1D nanostructures are aligned in a liquid suspension, and then transferred into the trenches from the liquid suspension. Removal of the patterning material places the 1D nanostructures in predetermined, registered positions on the substrate.

Abstract: A field effect transistor device includes a nanowire, a gate stack comprising a gate dielectric layer disposed on the nanowire, a gate conductor layer disposed on the dielectric layer and a substrate, and an active region including a sidewall contact portion disposed on the substrate adjacent to the gate stack, the side wall contact portion is electrically in contact with the nanowire.

Abstract: An enhancement-mode GaN transistor, the transistor having a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate containing acceptor type dopant elements, and a diffusion barrier comprised of a III Nitride material between the gate and the buffer layer.

Abstract: A tunneling field effect transistor structure and a method for forming the same are provided. The tunneling field effect transistor structure comprises: a substrate; a plurality of convex structures formed on the substrate, every two adjacent convex structures being separated by a predetermined cavity less than 30 nm in width, the convex structures comprising a plurality of sets, and each set comprising more than two convex structures; a plurality of floated films formed on tops of the convex structures, each floated film corresponding to one set of convex structures, a region of each floated film corresponding to a top of an intermediate convex structure in each set being formed as a channel region, and regions of the each floated film at both sides of the channel region are formed as a source region and a drain region with opposite conductivity types respectively; and a gate stack formed on each channel region.

Abstract: Carbon nanotubes can be aligned with compatibility with semiconductor manufacturing processes, with scalability for forming smaller devices, and without performance degradation related to structural damages. A planar structure including a buried gate electrode and two embedded electrodes are formed. After forming a gate dielectric, carbon nanotubes are assembled in a solution on a surface of the gate dielectric along the direction of an alternating current (AC) electrical field generated by applying a voltage between the two embedded electrodes. A source contact electrode and a drain contact electrode are formed by depositing a conductive material on both ends of the carbon nanotubes. Each of the source and drain contact electrodes can be electrically shorted to an underlying embedded electrode to reduce parasitic capacitance.

Abstract: A method of modifying a wafer having a semiconductor disposed on an insulator is provided and includes forming pairs of semiconductor pads connected via respective nanowire channels at each of first and second regions with different initial semiconductor thicknesses and reshaping the nanowire channels into nanowires to each have a respective differing thickness reflective of the different initial semiconductor thicknesses.

Abstract: A detector apparatus includes a field-effect transistor configured to undergo a change in amplitude of a source-to-drain current when at least a portion of a charge-tagged molecule translocates through the nanopore. In some implementations, the field-effect transistor is a carbon nanotube field effect transistor and the nanopore is located in a membrane. In other implementations, the field-effect transistor is a carbon nanotube field effect transistor and the nanopore is implemented in the form of a nano-channel in a semiconductor layer.

Abstract: A MOSFET with a graphene nano-ribbon, and a method for manufacturing the same are provided. The MOSFET comprises an insulating substrate; and an oxide protection layer on the insulating substrate. At least one graphene nano-ribbon is embedded in the oxide protection layer and has a surface which is exposed at a side surface of the oxide protection layer. A channel region is provided in each of the at least one graphene nano-ribbon. A source region and a drain regions are provided in each of the at least one graphene nano-ribbon. The channel region is located between the source region and the drain region. A gate dielectric is positioned on the at least one graphene nano-ribbon. A gate conductor on the gate dielectric. A source and drain contacts contact the source region and the drain region respectively on the side surface of the oxide protection layer.

Abstract: A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate.

Abstract: A reconfigurable device includes a first insulating layer, a second insulating layer, and a nanoscale quasi one- or zero-dimensional electron gas region disposed at an interface between the first and second insulating layers. The device is reconfigurable by applying an external electrical field to the electron gas, thereby changing the conductivity of the electron gas region. A method for forming and erasing nanoscale-conducting structures employs tools, such as the tip of a conducting atomic force microscope (AFM), to form local electric fields. The method allows both isolated and continuous conducting features to be formed with a length well below 5 nm.

Abstract: A semiconductor structure includes a support and at least one block provided on the support. The block includes a stack including alternating layers based on a first semiconductor material and layers based on a second semiconductor material different from the first material, the layers presenting greater dimensions than layers such that the stack has a lateral tooth profile and a plurality of spacers filling the spaces formed by the tooth profile, the spacers being made of a third material different from the first material such that each of the lateral faces of the block presents alternating lateral bands based on the first material and alternating lateral bands based on the third material. At least one of the lateral faces of the block is partially coated with a material promoting the growth of nanotubes or nanowires, the catalyst material exclusively coating the lateral bands based on the first material or exclusively coating the lateral bands based on the third material.

Abstract: A substrate includes a first source region and a first drain region each having a first semiconductor layer disposed on a second semiconductor layer and a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes; nanowire channel members suspended by the first source region and the first drain region, where the nanowire channel members include the first semiconductor layer, and opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes. The substrate further includes a second source and drain regions having the characteristics of the first source and drain regions, and a single channel member suspended by the second source region and the second drain region and having the same characteristics as the nanowire channel members. A width of the single channel member is at least several times a width of a single nanowire member.

Abstract: A substrate includes a first source region and a first drain region each having a first semiconductor layer disposed on a second semiconductor layer and a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes; nanowire channel members suspended by the first source region and the first drain region, where the nanowire channel members include the first semiconductor layer, and opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes. The substrate further includes a second source and drain regions having the characteristics of the first source and drain regions, and a single channel member suspended by the second source region and the second drain region and having the same characteristics as the nanowire channel members. A width of the single channel member is at least several times a width of a single nanowire member.

Abstract: A semiconductor device, such as an LED, includes a plurality of first conductivity type semiconductor nanowire cores located over a support, a continuous second conductivity type semiconductor layer extending over and around the cores, a plurality of interstitial voids located in the second conductivity type semiconductor layer and extending between the cores, and first electrode layer that contacts the second conductivity type semiconductor layer and extends into the interstitial voids.

Abstract: A method of modifying a wafer having a semiconductor disposed on an insulator is provided and includes forming pairs of semiconductor pads connected via respective nanowire channels at each of first and second regions with different initial semiconductor thicknesses and reshaping the nanowire channels into nanowires to each have a respective differing thickness reflective of the different initial semiconductor thicknesses.

Abstract: Graphene layers can be formed on a dielectric substrate using a process that includes forming a copper thin film on a dielectric substrate; diffusing carbon atoms through the copper thin film; and forming a graphene layer at an interface between the copper thin film and the dielectric substrate.

Abstract: Incompatible materials, such as copper and nitrided barrier layers, may be adhered more effectively to one another. In one embodiment, a precursor of copper is deposited on the nitrided barrier. The precursor is then converted, through the application of energy, to copper which could not have been as effectively adhered to the barrier in the first place.

Abstract: A 3-terminal electronic device includes: a control electrode; a first electrode and a second electrode; and an active layer that is provided between the first electrode and the second electrode and is provided to be opposed to the control electrode via an insulating layer. The active layer includes a collection of nanosheets. When it is assumed that the nanosheets have an average size LS and the first electrode and the second electrode have an interval D therebetween, LS/D?10 is satisfied.

Abstract: A semiconductor device includes a substrate, a nanowire, a first structure, and a second structure. The nanowire is suspended between the first structure and the second structure, where the first structure and the second structure overly the substrate, where the nanowire includes a layer on a surface of the nanowire, where the layer includes at least one of silicide and carbide, where the layer has a substantially uniform shape.

Abstract: A graphene electronic device includes a multi-layered gate insulating layer between a graphene channel layer and a gate electrode. The multi-layered gate insulating layer includes an organic insulating layer and an inorganic insulating layer on the organic insulating layer.

Abstract: A chain of field coupled nanomagnets includes at least one elements having substantially different anisotropy energy from that of the other nanomagnets. A signal can propagate from a first input nanomagnet having a relatively high anisotropy energy through the chain to an output nanomagnet. The output nanomagnet may have a relatively lower anisotropy energy than the other nanomagnets. Signal flow direction thus can be controlled. The higher anisotropy energy nanomagnet may be attained by use of a ferromagnet material having a higher anisotropy constant and/or configured with a larger volume than the other elements. The lower anisotropy energy magnet may be attained by use of a ferromagnet material having a lower anisotropy constant and/or configured with a smaller volume than the other elements. Logic signal flow control can also be attained making use of three dimensional geometries of nanomagnets with two different orientations.

Abstract: The invention provides transistor device comprising a source, a drain and a connecting channel, the channel is a nano-structure device adapted to allow current flow between the source and drain. The channel comprises an ultra-high doping concentration and is of the same polarity as in the source and/or drain. Essentially the transistor device of the present invention acts as a junctionless, highly-doped gated resistor. In the context of optimal performance of the transistor high doping means equal to or exceeds 1×1019 atom/cm3 results in that the device can operate as a junctionless transistor device.

Abstract: A tunnel field effect transistor (TFET) and method of making the same is provided. The TFET comprises a source-channel-drain structure and a gat electrode. The source region comprises a first source sub-region which is doped with a first doping profile with a dopant element of a first doping type having a first peak concentration and a second source sub-region close to a source-channel interface which is doped with a second doping profile with a second dopant element with the same doping type as the first dopant element and having a second peak concentration. The second peak concentration of the second doping profile is substantially higher than the maximum doping level of the first doping profile close to an interface between the first and the second source sub-regions.

Abstract: An intermediate process device is provided and includes a nanowire connecting first and second silicon-on-insulator (SOI) pads, a gate including a gate conductor surrounding the nanowire and poly-Si surrounding the gate conductor and silicide forming metal disposed to react with the poly-Si to form a fully silicided (FUSI) material to induce radial strain in the nanowire.

Abstract: A hetero-junction tunneling transistor having a first layer of p++ silicon germanium which forms a source for the transistor at one end. A second layer of n+ silicon material is deposited so that a portion of the second layer overlies the first layer and forms the drain for the transistor. An insulating layer and metallic gate for the transistor is deposited on top of the second layer so that the gate is aligned with the overlying portions of the first and second layers. The gate voltage controls the conduction between the source and the drain and the conduction between the first and second layers occurs by vertical tunneling between the layers.

Abstract: A semiconductor power switch and method is disclosed. In one Embodiment, the semiconductor power switch has a source contact, a drain contact, a semiconductor structure which is provided between the source contact and the drain contact, and a gate which can be used to control a current flow through the semiconductor structure between the source contact and the drain contact. The semiconductor structure has a plurality of nanowires which are connected in parallel and are arranged in such a manner that each nanowire forms an electrical connection between the source contact and the drain contact.

Abstract: A method of forming a self-aligned device is provided and includes depositing carbon nanotubes (CNTs) onto a crystalline dielectric substrate, isolating a portion of the crystalline dielectric substrate encompassing a location of the CNTs, forming gate dielectric and gate electrode gate stacks on the CNTs while maintaining a structural integrity thereof and forming epitaxial source and drain regions in contact with portions of the CNTs on the crystalline dielectric substrate that are exposed from the gate dielectric and gate electrode gate stacks.

Abstract: A nanowire tunnel device includes a nanowire suspended above a semiconductor substrate by a first pad region and a second pad region, the nanowire having a channel portion surrounded by a gate structure disposed circumferentially around the nanowire, an n-type doped region including a first portion of the nanowire adjacent to the channel portion, and a p-type doped region including a second portion of the nanowire adjacent to the channel portion.

Abstract: Techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided. In one aspect, a method of fabricating a FET includes the following steps. A doped substrate having a dielectric thereon is provided. At least one silicon (Si) nanowire is placed on the dielectric. One or more portions of the nanowire are masked off leaving other portions of the nanowire exposed. Epitaxial germanium (Ge) is grown on the exposed portions of the nanowire. The epitaxial Ge is interdiffused with Si in the nanowire to form SiGe regions embedded in the nanowire that introduce compressive strain in the nanowire. The doped substrate serves as a gate of the FET, the masked off portions of the nanowire serve as channels of the FET and the embedded SiGe regions serve as source and drain regions of the FET.

Abstract: A nanowire field effect transistor (FET) device includes a channel region including a silicon nanowire portion having a first distal end extending from the channel region and a second distal end extending from the channel region, the silicon portion is partially surrounded by a gate stack disposed circumferentially around the silicon portion, a source region including the first distal end of the silicon nanowire portion, a drain region including the second distal end of the silicon nanowire portion, a metallic layer disposed on the source region and the drain region, a first conductive member contacting the metallic layer of the source region, and a second conductive member contacting the metallic layer of the drain region.

Abstract: This invention describes a field-effect transistor in which the channel is formed in an array of quantum dots. In one embodiment the quantum dots are cladded with a thin layer serving as an energy barrier. The quantum dot channel (QDC) may consist of one or more layers of cladded dots. These dots are realized on a single or polycrystalline substrate. When QDC FETs are realized on polycrystalline or nanocrystalline thin films they may yield higher mobility than in conventional nano- or microcrystalline thin films. These FETs can be used as thin film transistors (TFTs) in a variety of applications. In another embodiment QDC-FETs are combined with: (a) coupled quantum well SWS channels, (b) quantum dot gate 3-state like FETs, and (c) quantum dot gate nonvolatile memories.

Abstract: A nanowire tunnel field effect transistor (FET) device includes a channel region including a silicon portion having a first distal end and a second distal end, the silicon portion is surrounded by a gate structure disposed circumferentially around the silicon portion, a drain region including an doped silicon portion extending from the first distal end, a portion of the doped silicon portion arranged in the channel region, a cavity defined by the second distal end of the silicon portion and an inner diameter of the gate structure, and a source region including a doped epi-silicon portion epitaxially extending from the second distal end of the silicon portion in the cavity, a first pad region, and a portion of a silicon substrate.

Abstract: In one embodiment, a method of providing a nanowire semiconductor device is provided, in which the gate structure to the nanowire semiconductor device has a trapezoid shape. The method may include forming a trapezoid gate structure surrounding at least a portion of a circumference of a nanowire. The first portion of the trapezoid gate structure that is in direct contact with an upper surface of the nanowire has a first width and a second portion of the trapezoid gate structure that is in direct contact with a lower surface of the nanowire has a second width. The second width of the trapezoid gate structure is greater than the first width of the trapezoid gate structure. The exposed portions of the nanowire that are adjacent to the portion of the nanowire that the trapezoid gate structure is surrounding are then doped to provide source and drain regions.

Abstract: A semiconductor structure including nanotubes forming an electrical connection between electrodes is disclosed. The semiconductor structure may include an open volume defined by a lower surface of an electrically insulative material and sidewalls of at least a portion of each of a dielectric material and opposing electrodes. The nanotubes may extend between the opposing electrodes, forming a physical and electrical connection therebetween. The nanotubes may be encapsulated within the open volume in the semiconductor structure. A semiconductor structure including nanotubes forming an electrical connection between source and drain regions is also disclosed. The semiconductor structure may include at least one semiconducting carbon nanotube electrically connected to a source and a drain, a dielectric material disposed over the at least one semiconducting carbon nanotube and a gate dielectric overlying a portion of the dielectric material. Methods of forming the semiconductor structures are also disclosed.

Abstract: Disclosed is a ribbon of graphene less than 3 nm wide, more preferably less than 1 nm wide. In a more preferred embodiment, there are multiple ribbons of graphene each with a width of one of the following dimensions: the length of 2 phenyl rings fused together, the length of 3 phenyl rings fused together, the length of 4 phenyl rings fused together, and the length of 5 phenyl rings fused together. In another preferred embodiment the edges of the ribbons are parallel to each other. In another preferred embodiment, the ribbons have at least one arm chair edge and may have wider widths. The invention further comprises a method of making a ribbon of graphene comprising the steps of: a. placing one or more polyaromatic hydrocarbon (PAH) precursors on a substrate; b. applying UV light to the PAH until one or more intermolecular bonds are formed between adjacent PAH molecules; and c. applying heat to the PAH molecules to increase the number of intermolecular bonds that are formed to create a ribbon of graphene.

Abstract: The disclosure relates to a hot electron injection MOS transistor, comprising source and drain regions formed in a semiconductor substrate, a control gate, and a floating gate comprising electrically conductive nanoparticles. The control gate comprises a first portion arranged at a first distance from the substrate, a second portion arranged at a second distance less than the first distance from the substrate, and an intermediary portion linking the first and the second portions.

Abstract: Techniques for forming a thin coating of a material on a carbon-based material are provided. In one aspect, a method for forming a thin coating on a surface of a carbon-based material is provided. The method includes the following steps. An ultra thin silicon nucleation layer is deposited to a thickness of from about two angstroms to about 10 angstroms on at least a portion of the surface of the carbon-based material to facilitate nucleation of the coating on the surface of the carbon-based material. The thin coating is deposited to a thickness of from about two angstroms to about 100 angstroms over the ultra thin silicon layer to form the thin coating on the surface of the carbon-based material.

Abstract: A field-effect transistor is provided and includes source, gate and drain regions, where the gate region controls charge carrier location in the transport channel, the transport channel includes a asymmetric coupled quantum well layer, the asymmetric quantum well layer includes at least two quantum wells separated by a barrier layer having a greater energy gap than the wells, the transport channel is connected to the source region at one end, and the drain regions at the other, the drain regions include at least two contacts electrically isolated from each other, the contacts are connected to at least one quantum well. The drain may include two regions that are configured to form the asymmetric coupled well transport channel. In an embodiment, two sources and two drains are also envisioned.