Thin-film Transistor (epo) Patents (Class 257/E29.273)

  • Patent number: 9040981
    Abstract: Provided is a transistor which has favorable transistor characteristics and includes an oxide semiconductor, and a highly reliable semiconductor device which includes the transistor including the oxide semiconductor. In the semiconductor device including the transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode are stacked in this order, a sidewall insulating film is formed along side surfaces and a top surface of the gate electrode, and the oxide semiconductor film is subjected to etching treatment so as to have a cross shape having different lengths in the channel length direction or to have a larger length than a source electrode and a drain electrode in the channel width direction. Further, the source electrode and the drain electrode are formed in contact with the oxide semiconductor film.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: May 26, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9035314
    Abstract: An object of the present invention is to provide an electrooptical device having high operation performance and reliability, and a method of manufacturing the electrooptical device. Lov region 207 is disposed in n-channel TFT 302 that comprises a driver circuit, and a TFT structure which is resistant to hot carriers is realized. Loff regions 217 to 220 are disposed in n-channel TFT 304 that comprises a pixel section, and a TFT structure of low off current is realized. An input-output signal wiring 305 and gate wiring 306 are formed by laminating a first wiring and a second wiring having lower resistivity than the first wiring, and wiring resistivity is steeply reduced.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: May 19, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 9035390
    Abstract: A thin film transistor substrate is equipped with: an insulating substrate (10a); a gate electrode (2) constituted by a stack of a first barrier metal layer (3) formed of titanium and disposed over the insulating substrate (10a), a first copper layer (4) disposed over the first barrier metal layer (3), and a second barrier metal layer (5) formed of titanium and disposed over the first copper layer (4); a gate insulating layer (7) disposed covering the gate electrode (2); and a semiconductor layer (8) disposed over the gate insulating layer (7), and having a channel region (C) disposed overlapping the gate electrode (2).
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: May 19, 2015
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Tohru Amano
  • Patent number: 9035287
    Abstract: Disclosed are polysulfone-based materials that can be used as active and/or passive components in various electronic, optical, and optoelectronic devices, particularly, metal-oxide-semiconductor field-effect transistors. For example, various metal-oxide-semiconductor field-effect transistors can include a dielectric layer and/or a passivation layer prepared from such polysulfone-based materials and exhibit good device performance.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 19, 2015
    Assignee: Polyera Corporation
    Inventors: Antonio Facchetti, Daniel Batzel, Jing Chen, Chun Huang, Shaofeng Lu, William Christopher Sheets, Jingqi Wang, Yu Xia
  • Patent number: 9029858
    Abstract: Provided is an organic light emitting display apparatus. The organic light emitting display apparatus includes: a substrate; a display unit disposed on the substrate; an encapsulation layer covering the display unit; an integrated circuit device disposed on an outer portion of the display unit on the substrate; and a transparent protection unit (window) disposed on the encapsulation layer and separated from the integrated circuit device.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: May 12, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Chang-Yong Jeong, Mu-Gyeom Kim
  • Patent number: 9024288
    Abstract: Embodiments of the present invention provide an array substrate, a manufacturing method thereof and a display device. The manufacturing method of an array substrate, comprising: forming a gate electrode on a base substrate by a first patterning process, and then depositing a gate insulating layer on the base substrate on which the gate electrode is formed; forming source and drain electrodes on the base substrate obtained after the above step, by a second patterning process; forming an active layer formed of a graphene layer, and a protective layer disposed on the active layer, on the base substrate obtained after the above steps, by a third patterning process; and forming a planarizing layer on the base substrate, obtained after the above steps, by a fourth patterning process, in which the planarizing layer is provided with a through hole through which the source or drain electrode is exposed.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: May 5, 2015
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Tuo Sun
  • Patent number: 9018638
    Abstract: A MOSFET device is provided. An N-type epitaxial layer is disposed on an N-type substrate. An insulating trench is disposed in the epitaxial layer. A P-type well region is disposed in the epitaxial layer at one side of the insulating trench. An N-type heavily doped region is disposed in the well region. A gate structure is disposed on the epitaxial layer and partially overlaps with the heavily doped region. At least two P-type first doped regions are disposed in the epitaxial layer below the well region. At least one P-type second doped region is disposed in the epitaxial layer and located between the first doped regions. Besides, the first and second doped regions are separated from each other. The first doped regions extend along a first direction, and the second doped region extends along a second direction different from the first direction.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: April 28, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Chee-Wee Liu, Hui-Hsuan Wang
  • Patent number: 9006736
    Abstract: To give favorable electrical characteristics to a semiconductor device. The semiconductor device includes an insulating layer, a semiconductor layer over the insulating layer, a pair of electrodes over the semiconductor layer and each electrically connected to the semiconductor layer, a gate electrode over the semiconductor layer, and a gate insulating layer between the semiconductor layer and the gate electrode. The insulating layer includes an island-shaped projecting portion. A top surface of the projecting portion of the insulating layer is in contact with a bottom surface of the semiconductor layer, and is positioned on an inner side of the semiconductor layer when seen from above. The pair of electrodes covers part of a top surface and part of side surfaces of the semiconductor layer. Furthermore, the gate electrode and the gate insulating layer cover side surfaces of the projecting portion of the insulating layer.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: April 14, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Motomu Kurata
  • Patent number: 9006744
    Abstract: An array substrate of a liquid crystal display device and a method of fabricating the array substrate. A gate electrode of a thin film transistor of the array substrate is formed. The gate electrode has an edge region surrounding an interior region of the gate electrode and the edge region of the gate electrode is thicker than the interior region of the gate electrode. A semiconductor layer is formed over the gate electrode. A source electrode and a drain electrode of the thin film transistor are formed that define a channel region in the semiconductor layer. The channel region is located over the interior region of the gate electrode. Additionally, the gate electrode may be formed with a half-tone mask that results in the edge region of the gate electrode being thicker than the interior region of the gate electrode.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: April 14, 2015
    Assignee: LG Display Co., Ltd.
    Inventors: Jae Seok Lee, Jae Chang Kwon, Yu Ri Shim, Min Bo Kim
  • Patent number: 8999776
    Abstract: Thin-film transistors and techniques for forming thin-film transistors (TFT). In some embodiments, there is provided a method of forming a TFT, comprising forming a body region of the TFT comprising an organic semiconducting material, and forming a protective layer comprising an organic insulating material. Forming the protective layer comprises contacting the body region of the TFT with a solution comprising the organic insulating material. The organic insulating material is a material that phase separates with the organic semiconducting material when the solution contacts the organic semiconducting material. In other embodiments, there is provided an apparatus comprising a TFT.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: April 7, 2015
    Assignee: Sony Corporation
    Inventor: Akihiro Nomoto
  • Patent number: 8994019
    Abstract: The invention is to provide a structure of a semiconductor device which achieves quick response and high-speed drive by improving on-state characteristics of a transistor, and to provide a highly reliable semiconductor device. In a transistor in which a semiconductor layer, a source and drain electrode layers, a gate insulating film, and a gate electrode are sequentially stacked, a non-single-crystal oxide semiconductor layer containing at least indium, a Group 3 element, zinc, and oxygen is used as the semiconductor layer. The Group 3 element functions as a stabilizer.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: March 31, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8981376
    Abstract: A semiconductor device includes a first conductive layer, a first insulating layer over the first conductive layer, first and second oxide semiconductor layers over the first insulating layer, a second conductive layer over the first oxide semiconductor layer, a third conductive layer over the second oxide semiconductor layer, a fourth conductive layer over the first oxide semiconductor layer and the second oxide semiconductor layer, a second insulating layer over the second conductive layer, the third conductive layer, and the fourth conductive layer, a fifth conductive layer electrically connected to the first conductive layer over the second insulating layer, and a sixth conductive layer over the second insulating layer. Each of the first and fifth conductive layers includes an area overlapping with the first oxide semiconductor layer. The sixth conductive layer includes an area overlapping with the second oxide semiconductor layer.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: March 17, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hideki Matsukura
  • Patent number: 8975630
    Abstract: An organic light emitting diodes display includes: a switching thin film transistor and a driving thin film transistor connected to the switching thin film transistor, wherein the driving thin film transistor includes a driving semiconductor layer section, a first gate insulating layer covering the driving semiconductor layer section, a floating gate electrode disposed on the first gate insulating layer, a second gate insulating layer covering the floating gate electrode, and a driving gate electrode disposed on the second gate insulating layer and at a position corresponding to the floating gate electrode, wherein the second gate insulating layer has a permittivity in the range of about 10 to about 100.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: March 10, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ju-Won Yoon, Su-Yeon Sim, Seung Min Lee, Il Jeong Lee, Jeong Ho Lee, Choong Youl Im, Jin Sung An
  • Patent number: 8969875
    Abstract: The present invention relates to a thin film transistor substrate and method for fabricating the same which can secure an alignment margin and reduce the number of mask steps. A thin transistor substrate according to the present invention includes a gate line and a data line crossing each other to define a pixel, a gate metal pattern under the data line, a thin film transistor having a gate electrode, a source electrode and a drain electrode in the pixel, and a pixel electrode connected to the drain electrode of the thin film transistor by a connection electrode, wherein the data line has a plurality of first slits to disconnect the gate metal pattern from the gate line.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: March 3, 2015
    Assignee: LG Display Co., Ltd.
    Inventor: Seung Hee Nam
  • Patent number: 8969931
    Abstract: A semiconductor device and a method for fabricating the semiconductor device. The device includes: a doped semiconductor having a source region, a drain region, a channel between the source and drain regions, and an extension region between the channel and each of the source and drain regions; a gate formed on the channel; and a screening coating on each of the extension regions. The screening coating includes: (i) an insulating layer that has a dielectric constant that is no greater than about half that of the extension regions and is formed directly on the extension regions, and (ii) a screening layer on the insulating layer, where the screening layer screens the dopant ionization potential in the extension regions to inhibit dopant deactivation.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mikael T. Bjoerk, Joachim Knoch, Heike E. Riel, Walter Heinrich Riess, Heinz Schmid
  • Patent number: 8969868
    Abstract: A thin film transistor comprises a transparent substrate, a gate is disposed on the transparent substrate, a gate insulator is disposed on the gate and the transparent substrate, an active layer is disposed on the gate insulator, an electrode layer is electrically connected the active layer and the portion of the active layer is exposed, and an ultraviolet light absorbing layer is disposed on the electrode layer. By using the advantage of the ultraviolet light absorbing layer with the range of visible light transmittance and with the component protection, preventing the optical characteristics of the thin film transistor from the outside moisture is achieved, and by adjusting the parameters in the thin film deposition process to change its conductivity.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: March 3, 2015
    Assignee: National Chiao Tung University
    Inventors: Han-Ping D. Shieh, Po-Tsun Liu, Yun-Chu Tsai, Min-Yen Tsai, Li-Feng Teng
  • Patent number: 8963131
    Abstract: An electronic device, such as a thin-film transistor, includes a semiconducting layer formed from a semiconductor composition. The semiconductor composition comprises a polymer binder and a small molecule semiconductor. The semiconducting layer has been deposited on an alignment layer that has been aligned in the direction between the source and drain electrodes. The resulting device has increased charge carrier mobility.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: February 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yiliang Wu, Anthony J. Wigglesworth, Ping Liu, Nan-Xing Hu
  • Patent number: 8963155
    Abstract: To provide a semiconductor device which has transistor characteristics with little variation and includes an oxide semiconductor. The semiconductor device includes an insulating film over a conductive film and an oxide semiconductor film over the insulating film. The oxide semiconductor film includes a first oxide semiconductor layer, a second oxide semiconductor layer over the first oxide semiconductor layer, and a third oxide semiconductor layer over the second oxide semiconductor layer. The energy level of a bottom of a conduction band of the second oxide semiconductor layer is lower than those of the first and third oxide semiconductor layers. An end portion of the second oxide semiconductor layer is positioned on an inner side than an end portion of the first oxide semiconductor layer.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: February 24, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Tokunaga, Takuya Handa
  • Patent number: 8957423
    Abstract: A semiconductor device in which defects in characteristics due to electrostatic discharge is reduced and a method for manufacturing the semiconductor device are provided. The semiconductor device has at least one of these structures: (1) a structure in which a first and second insulating films are in direct contact with each other in a peripheral region of a circuit portion, (2) a structure in which a first and second insulators are closely attached to each other, and (3) a structure in which a first conductive layer and a second conductive layer are provided on outer surfaces of the first insulator and the second insulator, respectively, and electrical conduction between the first and second conductive layers is achieved at a side surface of the peripheral region. Note that the conduction at the side surface can be achieved by cutting a plurality of semiconductor devices into separate semiconductor devices.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: February 17, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shingo Eguchi, Yoshiaki Oikawa
  • Patent number: 8952387
    Abstract: According to embodiments of the present invention, there are provided a TFT array substrate, a method for manufacturing the TFT array substrate and an electronic device.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: February 10, 2015
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Ce Ning, Xuehui Zhang, Jing Yang
  • Patent number: 8952455
    Abstract: In the case of using an analog buffer circuit, an input voltage is required to be added a voltage equal to a voltage between the gate and source of a polycrystalline silicon TFT; therefore, a power supply voltage is increased, thus a power consumption is increased with heat. In view of the foregoing problem, the invention provides a depletion mode polycrystalline silicon TFT as a polycrystalline silicon TFT used in an analog buffer circuit such as a source follower circuit. The depletion mode polycrystalline silicon TFT has a threshold voltage on its negative voltage side; therefore, an input voltage does not have to be increased as described above. As a result, a power supply voltage requires no increase, thus a low power consumption of a liquid crystal display device in particular can be realized.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: February 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Jun Koyama
  • Patent number: 8946716
    Abstract: A capacitor structure of gate driver in panel (GIP) includes a first metal layer, a first dielectric layer, a second metal layer, a second dielectric layer, a first and second transparent capacitor electrode layers. The first dielectric layer covers the first metal layer. The second metal layer is disposed on the first dielectric layer and coupled to the first metal layer. The second dielectric layer covers the second metal layer. The first transparent capacitor electrode layer is disposed on the first dielectric layer and connected to the second metal layer. The second transparent capacitor electrode layer is disposed on the second dielectric layer and coupled to the first metal layer, in which the second and first transparent capacitor electrode layers are arranged to be stacked in a thickness direction and mutually opposed across the second dielectric layer therebetween.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: February 3, 2015
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventors: Shih-Chieh Lin, Wen-Chuan Wang, Wei-Lien Sung, Bo-Han Chu
  • Patent number: 8946708
    Abstract: The band tail state and defects in the band gap are reduced as much as possible, whereby optical absorption of energy which is in the vicinity of the band gap or less than or equal to the band gap is reduced. In that case, not by merely optimizing conditions of manufacturing an oxide semiconductor film, but by making an oxide semiconductor to be a substantially intrinsic semiconductor or extremely close to an intrinsic semiconductor, defects on which irradiation light acts are reduced and the effect of light irradiation is reduced essentially. That is, even in the case where light with a wavelength of 350 nm is delivered at 1×1013 photons/cm2·sec, a channel region of a transistor is formed using an oxide semiconductor, in which the absolute value of the amount of the variation in the threshold voltage is less than or equal to 0.65 V.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: February 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Tsubuku, Kosei Noda
  • Patent number: 8946011
    Abstract: A manufacturing method of a semiconductor device having a stacked structure in which a lower layer is exposed is provided without increasing the number of masks. A source electrode layer and a drain electrode layer are formed by forming a conductive film to have a two-layer structure, forming an etching mask thereover, etching the conductive film using the etching mask, and performing side-etching on an upper layer of the conductive film in a state where the etching mask is left so that part of a lower layer is exposed. The thus formed source and drain electrode layers and a pixel electrode layer are connected in a portion of the exposed lower layer. In the conductive film, the lower layer and the upper layer may be a Ti layer and an Al layer, respectively. The plurality of openings may be provided in the etching mask.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: February 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Takafumi Mizoguchi
  • Patent number: 8941180
    Abstract: Disclosed is an integrated circuit having an asymmetric FET as a power gate for an electronic circuit, which has at least two stacked symmetric field effect transistors. The asymmetric FET has an asymmetric halo configuration (i.e., a single source-side halo or a source-side halo with a higher dopant concentration than a drain-side halo) and an asymmetric source/drain extension configuration (i.e., the source extension can be overlapped to a greater extent by the gate structure than the drain extension and/or the source extension can have a higher dopant concentration than the drain extension). As a result, the asymmetric FET has a low off current. In operation, the asymmetric FET is turned off when the electronic circuit is placed in a standby state and, due to the low off current (Ioff), effectively reduces standby leakage current from the electronic circuit.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: January 27, 2015
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Andres Bryant, Edward J. Nowak
  • Patent number: 8933442
    Abstract: An embodiment of the invention provides a thin film transistor substrate includes: a substrate; and a plurality of transistors, wherein each of the transistors includes a gate electrode disposed on the substrate; a first diffusion barrier layer disposed on the substrate and covering an upper surface and a ring sidewall of the gate electrode; a gate insulating layer disposed on the first diffusion barrier layer; an active layer disposed on the gate insulating layer and over the gate electrode; a source electrode disposed on the substrate and electrically connected to the active layer; a drain electrode disposed on the substrate and electrically connected to the active layer; and a protective layer covering the source electrode and the drain electrode.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: January 13, 2015
    Assignee: Innolux Corporation
    Inventor: Kuan-Feng Lee
  • Patent number: 8932902
    Abstract: The present disclosure relates to a thin film transistor substrate with a metal oxide semiconductor layer that has enhanced characteristics and stability. The present disclosure also relates to a method for manufacturing a thin film transistor substrate in which a thermal treatment is conducted for the metal oxide semiconductor layer and the damages to the substrate by the thermal treatment are minimized.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: January 13, 2015
    Assignee: LG Display Co., Ltd.
    Inventors: Kisul Cho, Seongmoh Seo
  • Patent number: 8921866
    Abstract: An electroluminescent display panel and method of fabricating the same are provided. The electroluminescent display panel includes a first multiple-layered structural layer, a second multiple-layered structural layer, a passivation layer and a third patterned conductive layer. The first multiple-layered structural layer includes a first patterned conductive layer, a first patterned insulation layer and an oxide semiconductor layer, and the first patterned conductive layer, the first patterned insulation layer and the oxide semiconductor layer have substantially the same shape. The second multiple-layered structural layer includes a second patterned conductive layer. The passivation layer has a plurality of through holes. A portion of the through holes expose the top surface and the lateral surface of the oxide semiconductor layer and the lateral surface of the first patterned conductive layer.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: December 30, 2014
    Assignee: AU Optronics Corp.
    Inventors: Peng-Bo Xi, Yu-Chi Chen
  • Patent number: 8921863
    Abstract: A thin film transistor TFT, including a substrate, a gate electrode on the substrate, a gate insulating layer on the gate electrode, an active layer on the gate insulating layer, the active layer corresponding to the gate electrode and including a channel region, source and drain electrodes contacting the active layer, the source and drain electrodes being separate from each other, and an ohmic contact layer between the active layer and at least one of the source and drain electrodes, the ohmic contact layer including an oxide semiconductor material.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: December 30, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventor: Chun-Gi You
  • Patent number: 8916460
    Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: December 23, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoung-Ho Kwon, Cheol Kim, Ho-Young Kim, Se-Jung Park, Myeong-Cheol Kim, Bo-Kyeong Kang, Bo-Un Yoon, Jae-Kwang Choi, Si-Young Choi, Suk-Hoon Jeong, Geum-Jung Seong, Hee-Don Jeong, Yong-Joon Choi, Ji-Eun Han
  • Patent number: 8912539
    Abstract: An array substrate includes an oxide semiconductor layer; an etch stopper including a first contact hole exposing each of both sides of the oxide semiconductor layer; source and drain electrodes spaced apart from each other with the oxide semiconductor layer therebetween; a first passivation layer including a contact hole exposing each of both ends of the oxide semiconductor layer and each of ends of the source and drain electrode that oppose the both ends of the oxide semiconductor layer, respectively; and a connection pattern at the second contact hole contacting both the oxide semiconductor layer and each of the source and drain electrodes.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: December 16, 2014
    Assignee: LG Display Co., Ltd.
    Inventor: Joon-Young Yang
  • Patent number: 8912543
    Abstract: The display device includes a substrate and a capacitor positioned on the substrate, the capacitor including a first capacitor electrode having a mesh shape and a second capacitor electrode having a mesh shape and positioned on the first capacitor electrode with an insulation layer therebetween.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: December 16, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Cheon-Deok Park, So-Ra Kwon
  • Patent number: 8912538
    Abstract: Embodiments of the present invention provide a thin film transistor array substrate, a method for manufacturing the same, a display panel and a display device. The method for manufacturing the thin film transistor array substrate comprises: sequentially depositing a first metal oxide layer, a second metal oxide layer and a source and drain metal layer, conductivity of the first metal oxide layer being smaller than conductivity of the second metal oxide layer; patterning the first metal oxide layer, the second metal oxide layer and the source and drain metal layer, so as to form an active layer, a buffer layer, a source electrode and a drain electrode, respectively. According to technical solutions of the embodiments of the invention, it is possible that the manufacturing process of the metal oxide TFT array substrate is simplified, and the production cost of products is reduced.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: December 16, 2014
    Assignee: Boe Technology Group Co., Ltd.
    Inventors: Xiang Liu, Woobong Lee
  • Patent number: 8907343
    Abstract: A display panel is provided, which includes a transparent substrate, a first thin film transistor (TFT), a second TFT, a transparent bottom electrode, a capacitance layer, a transparent top electrode, an opposite substrate and a display medium layer. The transparent substrate has a display region and a peripheral region. The display region has sub-pixel regions, and at least one sub-pixel region at least includes a capacitance region and a transistor region. The first and the second TFTs are disposed on the transistor region of the transparent substrate. The transparent bottom electrode, the capacitance layer and the transparent top electrode are sequentially disposed on the capacitance region of transparent substrate, in which the transparent bottom electrode is connected to a source/drain electrode of the first TFT, and the transparent top electrode is connected to a source/drain electrode of the second TFT.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: December 9, 2014
    Assignee: AU Optronics Corporation
    Inventor: Peng-Bo Xi
  • Patent number: 8901550
    Abstract: An organic light-emitting display apparatus includes an active layer of a thin film transistor (TFT), a gate electrode including a transparent conductive material or a metal that on the active layer, a first insulating layer on the substrate, source and drain electrodes electrically connected to the active layer, a second insulating layer between the gate electrode and the source and drain electrodes, a first conductive layer of a transparent conductive material on the first insulating layer, a second conductive layer on the first conductive layer, the second conductive layer being a metal, a third conductive layer on the second conductive layer, the third conductive layer being made of a same material as the source and drain electrodes, and being connected to the first conductive layer; and a protection layer that includes a transparent conductive oxide, the protection layer being on the third conductive layer.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: December 2, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Se-Hun Park, Won-Kyu Lee, Yeoung-Jin Chang, Jae-Hwan Oh, Seong-Hyun Jin, Jae-Beom Choi
  • Patent number: 8901691
    Abstract: A touch sensing substrate includes a substrate, a first light sensing element, a second light sensing element and a first bias line. The first light sensing element includes a first gate electrode, a first active pattern overlapping with the first gate electrode, a first source electrode partially overlapping with the first active pattern and a first drain electrode partially overlapping with the first active pattern. The second light sensing element includes a second gate electrode, a second active pattern overlapping with the second gate electrode, a second source electrode partially overlapping with the second active pattern and a second drain electrode partially overlapping with the second active pattern. The first bias line is connected to the first and second gate electrodes.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: December 2, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yun-Jong Yeo, Byeong-Hoon Cho, Ki-Hun Jeong, Hong-Kee Chin, Jung-Suk Bang, Woong-Kwon Kim, Sung-Ryul Kim, Hee-Joon Kim, Dae-Cheol Kim, Kun-Wook Han
  • Patent number: 8901655
    Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. At least one first/second set of nanowires and pads are patterned in the SOI layer. A conformal gate dielectric layer is selectively formed surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration. A second metal gate stack is formed surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 8901658
    Abstract: A thin film transistor (TFT) is provided, which includes a gate, a semiconductor layer, an insulation layer, a source and a drain. The semiconductor layer has a first end and a second end opposite to the first end. The insulation layer is disposed between the gate and the semiconductor layer. The source clamps the first end of the semiconductor layer and the drain clamps the second end of the semiconductor layer.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: December 2, 2014
    Assignee: E Ink Holdings Inc.
    Inventors: Henry Wang, Chia-Chun Yeh, Xue-Hung Tsai, Ted-Hong Shinn
  • Patent number: 8901557
    Abstract: High field-effect mobility is provided for a transistor including an oxide semiconductor. Further, a highly reliable semiconductor device including the transistor is provided. In a bottom-gate transistor including an oxide semiconductor layer, an oxide semiconductor layer functioning as a current path (channel) of the transistor is sandwiched between oxide semiconductor layers having lower carrier densities than the oxide semiconductor layer. In such a structure, the channel is formed away from the interface of the oxide semiconductor stacked layer with an insulating layer in contact with the oxide semiconductor stacked layer, i.e., a buried channel is formed.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: December 2, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8890157
    Abstract: The present invention provides a pixel structure including a substrate, a thin-film transistor disposed on the substrate, a first insulating layer covering the thin-film transistor and the substrate, a common electrode, a connecting electrode, a second insulating layer, and a pixel electrode. The thin-film transistor includes a drain electrode. The first insulating layer has a first opening exposing the drain electrode. The common electrode and the connecting electrode are disposed on the first insulating layer. The connecting electrode extends into the first opening to be electrically connected to the drain electrode. The connecting electrode is electrically insulated from the common electrode. The second insulating layer covers the first insulating layer, the common electrode, the connecting electrode, and has a second opening exposing the connecting electrode. The pixel electrode is disposed on the second insulating layer and electrically connected to the connecting electrode through the second opening.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 18, 2014
    Assignee: HannStar Display Corp.
    Inventors: Hsuan-Chen Liu, Hsien-Cheng Chang, Da-Ching Tang, Chien-Hao Wu, Ching-Chao Wang, Jung-Chen Lin
  • Patent number: 8890159
    Abstract: An oxide semiconductor stacked film which does not easily cause a variation in electrical characteristics of a transistor and has high stability is provided. Further, a transistor which includes the oxide semiconductor stacked film in its channel formation region and has stable electrical characteristics is provided. An oxide semiconductor stacked film includes a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer which are sequentially stacked and each of which contains indium, gallium, and zinc. The content percentage of indium in the second oxide semiconductor layer is higher than that in the first oxide semiconductor layer and the third oxide semiconductor layer, and the absorption coefficient of the oxide semiconductor stacked film, which is measured by the CPM, is lower than or equal to 3×10?3/cm in an energy range of 1.5 eV to 2.3 eV.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: November 18, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masashi Tsubuku, Ryosuke Watanabe, Masashi Oota, Noritaka Ishihara, Koki Inoue
  • Patent number: 8890153
    Abstract: An active matrix substrate is disclosed, enabling to suppress variation in signal voltages among pixel electrodes. An active matrix substrate includes: an insulating substrate; a plurality of pixel electrodes arranged in a matrix on the insulating substrate; and a source wiring extending in a column direction so as to overlap with two pixel electrodes adjacent to each other in a row direction on the insulating substrate. The pixel electrodes and the source wiring are formed in different layers via an insulating film, the source wiring has a main line portion and extension portions extended from both sides of the main line portion, and the extension portion is formed of a transparent conductive material.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: November 18, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Akiyoshi Fujii
  • Patent number: 8890158
    Abstract: An object is to provide a highly reliable transistor and a semiconductor device including the transistor. A semiconductor device including a gate electrode; a gate insulating film over the gate electrode; an oxide semiconductor film over the gate insulating film; and a source electrode and a drain electrode over the oxide semiconductor film, in which activation energy of the oxide semiconductor film obtained from temperature dependence of a current (on-state current) flowing between the source electrode and the drain electrode when a voltage greater than or equal to a threshold voltage is applied to the gate electrode is greater than or equal to 0 meV and less than or equal to 25 meV, is provided.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: November 18, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takahiro Tsuji, Teruaki Ochiai, Koji Kusunoki, Hidekazu Miyairi
  • Patent number: 8884297
    Abstract: A manufacturing method of a microcrystalline silicon film includes the steps of forming a first microcrystalline silicon film over an insulating film by a plasma CVD method under a first condition; and forming a second microcrystalline silicon film over the first microcrystalline silicon film under a second condition. As a source gas supplied to a treatment chamber, a deposition gas containing silicon and a gas containing hydrogen are used. In the first condition, a flow rate of hydrogen is set at a flow rate 50 to 1000 times inclusive that of the deposition gas, and the pressure inside the treatment chamber is set 67 to 1333 Pa inclusive. In the second condition, a flow rate of hydrogen is set at a flow rate 100 to 2000 times inclusive that of the deposition gas, and the pressure inside the treatment chamber is set 1333 to 13332 Pa inclusive.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: November 11, 2014
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Sachiaki Tezuka, Yasuhiro Jinbo, Toshinari Sasaki, Hidekazu Miyairi, Yosuke Kanzaki, Masao Moriguchi
  • Patent number: 8884282
    Abstract: A transistor is provided in which the bottom surface portion of an oxide semiconductor film is provided with a metal oxide film containing a constituent similar to that of the oxide semiconductor film, and an insulating film containing a different constituent from the metal oxide film and the oxide semiconductor film is formed in contact with a surface of the metal oxide film, which is opposite to the surface in contact with the oxide semiconductor film. In addition, the oxide semiconductor film used for the active layer of the transistor is an oxide semiconductor film highly purified to be electrically i-type (intrinsic) through heat treatment in which impurities such as hydrogen, moisture, hydroxyl, and hydride are removed from the oxide semiconductor and oxygen which is one of main component materials of the oxide semiconductor is supplied and is also reduced in a step of removing impurities.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: November 11, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8884302
    Abstract: A semiconductor device including a first gate electrode and a second gate electrode formed apart from each other over an insulating surface, an oxide semiconductor film including a region overlapping with the first gate electrode with a gate insulating film interposed therebetween, a region overlapping with the second gate electrode with the gate insulating film interposed therebetween, and a region overlapping with neither the first gate electrode nor the second gate electrode, and an insulating film covering the gate insulating film, the first gate electrode, the second gate electrode, and the oxide semiconductor film, and being in direct contact with the oxide semiconductor film is provided.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: November 11, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Seiko Inoue, Hiroyuki Miyake, Kouhei Toyotaka
  • Patent number: 8884345
    Abstract: The graphene electronic device may include a gate oxide on a conductive substrate, the conductive substrate configured to function as a gate electrode, a pair of first metals on the gate oxide, the pair of the first metals separate from each other, a graphene channel layer extending between the first metals and on the first metals, and a source electrode and a drain electrode on both edges of the graphene channel layer.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-seong Heo, Hyun-jong Chung, Sun-ae Seo, Sung-hoon Lee, Hee-jun Yang
  • Patent number: 8878184
    Abstract: A display device having the high aperture ratio and a storage capacitor with high capacitance is to be obtained. The present invention relates to a display device and a manufacturing method thereof. The display device includes a thin film transistor which includes a gate electrode, a gate insulating film, a first semiconductor layer, a channel protective film, a second semiconductor having conductivity which is divided into a source region and a drain region, and a source electrode and a drain electrode; a third insulating layer formed over the second conductive film; a pixel electrode formed over the third insulating layer, which is connected to one of the source electrode and the drain electrode; and a storage capacitor formed in a region where a capacitor wiring over the first insulating layer and the pixel electrode are overlapped with the third insulating layer over the capacitor wiring interposed therebetween.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: November 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kunio Hosoya
  • Patent number: 8877569
    Abstract: An object is to provide a semiconductor device provided with a thin film transistor having excellent electric characteristics using an oxide semiconductor layer. An In—Sn—O-based oxide semiconductor layer including SiOX is used for a channel formation region. In order to reduce contact resistance between the In—Sn—O-based oxide semiconductor layer including SiOX and a wiring layer formed from a metal material having low electric resistance, a source region or drain region is formed between a source electrode layer or drain electrode layer and the In—Sn—O-based oxide semiconductor layer including SiOX. The source region or drain region and a pixel region are formed using an In—Sn—O-based oxide semiconductor layer which does not include SiOX.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: November 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiaki Oikawa, Hotaka Maruyama, Hiromichi Godo, Daisuke Kawae, Shunpei Yamazaki
  • Patent number: 8878181
    Abstract: An oxide thin film transistor (TFT) and a fabrication method thereof are provided.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: November 4, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Hoon Yim, Dae-Hwan Kim