Comprising Group Iii-v Or Ii-vi Compound, Or Of Se, Te, Or Oxide Semiconductor (epo) Patents (Class 257/E29.296)
  • Patent number: 8698143
    Abstract: An aperture ratio of a semiconductor device is improved. A driver circuit and a pixel are provided over one substrate, and a first thin film transistor in the driver circuit and a second thin film transistor in the pixel each include a gate electrode layer, a gate insulating layer over the gate electrode layer, an oxide semiconductor layer over the gate insulating layer, source and drain electrode layers over the oxide semiconductor layer, and an oxide insulating layer in contact with part of the oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer, and the source and drain electrode layers. The gate electrode layer, the gate insulating layer, the oxide semiconductor layer, the source and drain electrode layers, and the oxide insulating layer of the second thin film transistor each have a light-transmitting property.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: April 15, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Hiroyuki Miyake, Hideaki Kuwabara, Tatsuya Takahashi
  • Patent number: 8698214
    Abstract: A semiconductor device includes a base insulating film including silicon, an oxide semiconductor film over the base insulating film, a gate insulating film over the oxide semiconductor film, a gate electrode which is in contact with the gate insulating film and overlaps with at least the oxide semiconductor film, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. The oxide semiconductor film includes a region in which a concentration of silicon distributed from the interface with the base insulating film toward an inside of the oxide semiconductor film is lower than or equal to 1.0 at. %. A crystal portion is included at least in the region.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: April 15, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Honda, Masashi Tsubuku, Yusuke Nonaka, Takashi Shimazu
  • Patent number: 8686416
    Abstract: Provided is an oxide semiconductor film which has more stable electric characteristics and essentially consists of indium zinc oxide. In addition, provided is a highly reliable semiconductor device which has stable electric characteristics by using the oxide semiconductor film. The oxide semiconductor film essentially consisting of indium zinc oxide has a hexagonal crystal structure in which the a-b plane is substantially parallel to a surface of the oxide semiconductor film and a rhombohedral crystal structure in which the a-b plane is substantially parallel to the surface of the oxide semiconductor film.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: April 1, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Honda, Hiroshi Kanemura, Kengo Akimoto, Suzunosuke Hiraishi
  • Patent number: 8679904
    Abstract: A thin film transistor includes: an insulating layer; a gate electrode provided on the insulating layer; a gate insulating film provided on the gate electrode; a semiconductor layer provided on the gate insulating film, the semiconductor layer being formed of oxide; source and drain electrodes provided on the semiconductor layer; and a channel protecting layer provided between the source and drain electrodes and the semiconductor layer. The source electrode is opposed to one end of the gate electrode. The drain electrode is opposed to another end of the gate electrode. The another end is opposite to the one end. The drain electrode is apart from the source electrode. The channel protecting layer covers at least a part of a side face of a part of the semiconductor layer. The part of the semiconductor layer is not covered with the source and drain electrodes above the gate electrode.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: March 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuyoshi Saito, Tomomasa Ueda, Shintaro Nakano, Shuichi Uchikoga
  • Patent number: 8673401
    Abstract: A method for depositing gallium using a gallium ink, comprising, as initial components: a gallium component comprising gallium; a stabilizing component; an additive; and, a liquid carrier; is provided comprising applying the gallium ink on the substrate; heating the applied gallium ink to eliminate the additive and the liquid carrier, depositing gallium on the substrate; and, optionally, annealing the deposited gallium.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: March 18, 2014
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: David Mosley, David Thorsen
  • Patent number: 8669553
    Abstract: A thin-film transistor includes a gate electrode, a gate dielectric disposed on the gate electrode, a channel layer, and a passivation layer. The channel layer has a first surface and an opposed second surface, where the first surface is disposed over at least a portion of the gate dielectric. The channel layer also has a first oxide composition including at least one predetermined cation. The passivation layer is disposed adjacent to at least a portion of the opposed second surface of the channel layer. The passivation layer has a second oxide composition including the at least one predetermined cation of the first oxide composition and at least one additional cation that increases a bandgap of the passivation layer relative to the channel layer.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: March 11, 2014
    Assignees: Hewlett-Packard Development Company, L.P., Oregon State University
    Inventors: Chris Knutson, Rick Presley, John F. Wager, Douglas Keszler, Randy Hoffman
  • Patent number: 8664036
    Abstract: An oxide semiconductor layer with excellent crystallinity is formed to enable manufacture of transistors with excellent electrical characteristics for practical application of a large display device, a high-performance semiconductor device, etc. By first heat treatment, a first oxide semiconductor layer is crystallized. A second oxide semiconductor layer is formed over the first oxide semiconductor layer. By second heat treatment, an oxide semiconductor layer including a crystal region having the c-axis oriented substantially perpendicular to a surface is efficiently formed and oxygen vacancies are efficiently filled. An oxide insulating layer is formed over and in contact with the oxide semiconductor layer. By third heat treatment, oxygen is supplied again to the oxide semiconductor layer. A nitride insulating layer containing hydrogen is formed over the oxide insulating layer.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: March 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hotaka Maruyama, Yoshiaki Oikawa, Katsuaki Tochibayashi
  • Patent number: 8653515
    Abstract: Provided is a thin film transistor and thin film transistor panel array. The thin film transistor includes: a substrate; a gate electrode disposed on the substrate; a semiconductor layer disposed on the substrate and partially overlapping with the gate electrode; a source electrode and a drain electrode spaced apart from each other with respect to a channel region of the semiconductor layer; an insulating layer disposed between the gate electrode and the semiconductor layer; and a barrier layer disposed between the semiconductor layer and the source electrode and between the semiconductor layer and the drain electrode, in which the barrier layer comprises graphene. An ohmic contact is provided based on the type of material used for the semiconductor layer.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: February 18, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yong-Su Lee, Yoon Ho Khang, Se Hwan Yu, Chong Sup Chang
  • Patent number: 8653514
    Abstract: An object is to manufacture a semiconductor device with high reliability by providing the semiconductor device including an oxide semiconductor with stable electric characteristics. In a transistor including an oxide semiconductor layer, a gallium oxide film is used for a gate insulating layer and made in contact with an oxide semiconductor layer. Further, gallium oxide films are provided so as to sandwich the oxide semiconductor layer, whereby reliability is increased. Furthermore, the gate insulating layer may have a stacked structure of a gallium oxide film and a hafnium oxide film.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: February 18, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8653513
    Abstract: A semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode in contact with the oxide semiconductor layer, a gate electrode overlapping with the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate electrode, in which the source electrode or the drain electrode comprises a first conductive layer and a second conductive layer having a region which extends beyond an end portion of the first conductive layer in a channel length direction and which overlaps with part of the gate electrode, in which a sidewall insulating layer is provided over the extended region of the second conductive layer, and in which the sidewall insulating layer comprises a stack of a plurality of different material layers.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: February 18, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Shinya Sasagawa, Motomu Kurata
  • Patent number: 8643011
    Abstract: It is an object to provide an oxide semiconductor which is suitable for use in a semiconductor device. Alternatively, it is another object to provide a semiconductor device using the oxide semiconductor. Provided is a semiconductor device including an In—Ga—Zn—O based oxide semiconductor layer in a channel formation region of a transistor. In the semiconductor device, the In—Ga—Zn—O based oxide semiconductor layer has a structure in which crystal grains represented by InGaO3(ZnO)m (m=1) are included in an amorphous structure represented by InGaO3(ZnO)m (m>0).
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: February 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Junichiro Sakata, Takuya Hirohashi, Masahiro Takahashi, Hideyuki Kishida, Akiharu Miyanaga
  • Patent number: 8643009
    Abstract: To suppress deterioration in electrical characteristics in a transistor including an oxide semiconductor layer or a semiconductor device including the transistor. In a transistor in which a channel layer is formed using an oxide semiconductor, a silicon layer is provided in contact with a surface of the oxide semiconductor layer. Further, the silicon layer is provided in contact with at least a region of the oxide semiconductor layer, in which a channel is formed, and a source electrode layer and a drain electrode layer are provided in contact with regions of the oxide semiconductor layer, over which the silicon layer is not provided.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: February 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichiro Sakata, Hiromichi Godo, Takashi Shimazu
  • Patent number: 8643010
    Abstract: A semiconductor device includes an oxide semiconductor film in which a channel portion is formed and a gate portion arranged to be opposed to the channel portion. A drain portion in which the oxide semiconductor film has been subjected to resistance reduction process and an intermediate area which is provided between the drain portion and the channel portion and has not been subjected to resistance reduction process are formed in the oxide semiconductor film, and the semiconductor device includes a conductive film to block resistance reduction process to the intermediate area at least at a part.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: February 4, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Hiroshi Matsukizono
  • Patent number: 8637863
    Abstract: One object is to provide a transistor including an oxide semiconductor film which is used for the pixel portion of a display device and has high reliability. A display device has a first gate electrode; a first gate insulating film over the first gate electrode; an oxide semiconductor film over the first gate insulating film; a source electrode and a drain electrode over the oxide semiconductor film; a second gate insulating film over the source electrode, the drain electrode and the oxide semiconductor film; a second gate electrode over the second gate insulating film; an organic resin film having flatness over the second gate insulating film; a pixel electrode over the organic resin film having flatness, wherein the concentration of hydrogen atoms contained in the oxide semiconductor film and measured by secondary ion mass spectrometry is less than 1×1016 cm?3.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: January 28, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8637864
    Abstract: A miniaturized transistor is provided with high yield. Further, a semiconductor device which has high on-state characteristics and which is capable of high-speed response and high-speed operation is provided. In the semiconductor device, an oxide semiconductor layer, a gate insulating layer, a gate electrode layer, an insulating layer, a conductive film, and an interlayer insulating layer are stacked in this order. A source electrode layer and a drain electrode layer are formed in a self-aligned manner by cutting the conductive film so that the conductive film over the gate electrode layer and the conductive layer is removed and the conductive film is divided. An electrode layer which is in contact with the oxide semiconductor layer and overlaps with a region in contact with the source electrode layer and the drain electrode layer is provided.
    Type: Grant
    Filed: October 1, 2012
    Date of Patent: January 28, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshihiko Saito, Atsuo Isobe, Kazuya Hanaoka, Junichi Koezuka, Shinya Sasagawa, Motomu Kurata, Akihiro Ishizuka
  • Patent number: 8637861
    Abstract: Provided is a semiconductor device for high power application including a novel semiconductor material with high productivity. Alternatively, provided is a semiconductor device having a novel structure in which the novel semiconductor material is used. Provided is a vertical transistor including a channel formation region formed using an oxide semiconductor which has a wider band gap than a silicon semiconductor and is an intrinsic semiconductor or a substantially intrinsic semiconductor with impurities that serve as electron donors (donors) in the oxide semiconductor removed. The thickness of the oxide semiconductor is greater than or equal to 1 micrometer, preferably greater than 3 micrometer, more preferably greater than or equal to 10 micrometer.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: January 28, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Daisuke Kawae
  • Patent number: 8637865
    Abstract: An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limit on the number of write operations. The semiconductor device includes a first memory cell including a first transistor and a second transistor, a second memory cell including a third transistor and a fourth transistor, and a driver circuit. The first transistor and the second transistor overlap at least partly with each other. The third transistor and the fourth transistor overlap at least partly with each other. The second memory cell is provided over the first memory cell. The first transistor includes a first semiconductor material. The second transistor, the third transistor, and the fourth transistor include a second semiconductor material.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: January 28, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kiyoshi Kato
  • Patent number: 8629432
    Abstract: A semiconductor device including a thin film transistor which includes an oxide semiconductor layer and has high electric characteristics and reliability. Film deposition is performed using an oxide semiconductor target containing an insulator (an insulating oxide, an insulating nitride, silicon oxynitride, aluminum oxynitride, or the like), typically SiO2, so that the semiconductor device in which the Si-element concentration in the thickness direction of the oxide semiconductor layer has a gradient which increases in accordance with an increase in a distance from a gate electrode is realized.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: January 14, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichiro Sakata, Takashi Shimazu, Hiroki Ohara, Toshinari Sasaki, Shunpei Yamazaki
  • Patent number: 8624237
    Abstract: An embodiment is to include an inverted staggered (bottom gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: January 7, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Akiharu Miyanaga, Kengo Akimoto, Kojiro Shiraishi
  • Patent number: 8624238
    Abstract: A thin-film transistor (TFT) substrate having reduced defects is fabricated using a reduced number of masks. The TFT substrate includes gate wiring formed on a substrate. The gate wiring includes a gate electrode. A semiconductor pattern is formed on the gate wiring. An etch-stop pattern is formed on the semiconductor pattern. Data wiring includes a source electrode which is formed on the semiconductor pattern and the etch-stop pattern. Each of the gate wiring and the data wiring includes a copper-containing layer and a buffer layer formed on or under the copper-containing layer.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: January 7, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jong-In Kim, Young-Wook Lee, Jean-Ho Song, Jae-Hyoung Yoon, Sung-Ryul Kim, Byeong-Beom Kim, Je-Hyeong Park, Woo-Geun Lee
  • Patent number: 8618537
    Abstract: A semiconductor device includes, in a first region over a semiconductor substrate, a first insulating layer, a first wiring, a second insulating layer, a third insulating layer, and a via and a second wiring embedded in the second insulating layer and the third insulating layer through a barrier metal, and includes, in a second region, the first insulating layer, a gate electrode, the second insulating layer, a semiconductor layer located, the third insulating layer, and a first electric conductor and a second electric conductor embedded in the third insulating layer so as to sandwich the gate electrode in a position overlapped with the semiconductor layer in a plan view through a barrier metal and coupled to the semiconductor layer through the barrier metal.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: December 31, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Kishou Kaneko, Naoya Inoue, Yoshihiro Hayashi
  • Patent number: 8617920
    Abstract: It is an object to provide a semiconductor device having excellent electric characteristics or high reliability, or a manufacturing method thereof. A semiconductor device including a gate electrode, an oxide semiconductor layer overlapping with the gate electrode, a source electrode and a drain electrode in contact with the oxide semiconductor layer, and a gate insulating layer provided between the gate electrode and the oxide semiconductor layer is provided. The oxide semiconductor layer is formed by a facing target sputtering method. The carrier concentration of the oxide semiconductor is less than 1×1012/cm3.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: December 31, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8610120
    Abstract: A photolithography step and an etching step for forming an island-shaped semiconductor layer is omitted, and a liquid crystal display device is manufactured through the following four photolithography steps: a step for forming a gate electrode (including a wiring or the like formed from the same layer), a step for forming a source electrode and a drain electrode (including a wiring or the like formed from the same layer), a step for forming a contact hole (including removal of an insulating layer or the like in a region other than the contact hole), and a step for forming a pixel electrode (including a wiring or the like formed from the same layer). In the step of forming the contact hole, a groove portion in which the semiconductor layer is removed is formed, so that formation of parasitic channels is prevented.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: December 17, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroyuki Miyake, Ryo Arasawa, Koji Kusunoki
  • Patent number: 8610180
    Abstract: It is an object to provide a gas sensor which is formed by a simple manufacturing process. Another object is to provide a gas sensor whose manufacturing cost is reduced. A transistor which includes an oxide semiconductor layer in contact with a gas and which serves as a detector element of a gas sensor, and a transistor which includes an oxide semiconductor layer in contact with a film having a gas barrier property and which forms a detection circuit are formed over one substrate by the same process, whereby a gas sensor using these transistors may be formed.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: December 17, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Koichiro Kamata
  • Patent number: 8609460
    Abstract: A semiconductor structure and a fabricating method thereof are provided. The fabricating method includes forming a gate, a source, and a drain on a substrate and forming an oxide semiconductor material between the gate and the source and drain. The oxide semiconductor material is formed by performing a deposition process, and nitrogen gas is introduced before the deposition process is completely performed, so as to form oxide semiconductor nitride on the oxide semiconductor material.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: December 17, 2013
    Assignee: Au Optronics Corporation
    Inventors: Po-Tsun Liu, Yi-Teh Chou, Li-Feng Teng, Fu-Hai Li, Han-Ping D. Shieh, Wei-Ting Lin, Ming-Chin Hung, Chun-Ching Hsiao, Jiun-Jye Chang, Po-Lun Chen
  • Patent number: 8604473
    Abstract: An object is to provide a UV sensor with high accuracy, which can be manufactured at low cost and formed over a flexible substrate. A semiconductor device includes a transistor having an oxide semiconductor film, and a voltage source electrically connected to a gate of the transistor, in which a threshold voltage of the transistor is changed by irradiating the oxide semiconductor film with UV rays; a change in the threshold voltage of the transistor is dependent on a wavelength of the UV rays with which the oxide semiconductor film is irradiated, and the voltage source adjusts a voltage output to the gate of the transistor.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: December 10, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshihiko Saito, Yuta Uemura
  • Patent number: 8604469
    Abstract: A thin film transistor array panel includes a substrate, a gate line formed on the substrate and including a gate electrode, a gate insulating layer formed on the gate line, a semiconductor formed on the gate insulating layer and including a channel of a thin film transistor, a data line formed on the semiconductor and including a source electrode and a drain electrode formed on the semiconductor and opposite to the source electrode with respect to the channel of the thin film transistor, wherein the channel of the thin film transistor covers both side surfaces of the gate electrode.
    Type: Grant
    Filed: May 13, 2009
    Date of Patent: December 10, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Woo-Geun Lee, Jae-Hyoung Youn, Ki-Won Kim, Young-Wook Lee, Jong-In Kim
  • Patent number: 8604471
    Abstract: A semiconductor structure and an organic electroluminescence device applying the same are provided. A gate insulating layer covers a gate electrode disposed on a substrate. A channel layer has a channel length L along a channel direction and has a first side and a second side opposite to the first side. The channel layer is located on the gate insulating layer over the gate electrode. A source electrode and a drain electrode are located at and electrically connected to the first side and the second side of the channel layer, respectively. A conductive light-shielding pattern layer is disposed on a dielectric layer covering the source electrode, the drain electrode and the channel layer, and is overlapped to a portion of the source electrode and a portion of the channel layer in a vertical projection. The conductive light-shielding pattern layer and the channel layer have an overlapping length d1, and 0.3?d1/L?0.85.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: December 10, 2013
    Assignee: Au Optronics Corporation
    Inventors: Chih-Pang Chang, Hsing-Hung Hsieh
  • Publication number: 20130320327
    Abstract: A thin film transistor includes a substrate, an oxide semiconductor layer that is disposed on the substrate, a gate electrode that overlaps with the oxide semiconductor layer, a gate insulating layer that is disposed between the oxide semiconductor layer and the gate electrode, and a source electrode and a drain electrode that at least partially overlap with the oxide semiconductor layer and are spaced from each other. The gate insulating layer includes an oxide including a first material. The oxide semiconductor layer includes an oxide which includes a same material as the first material and a second material, and the source electrode and the drain electrode include an oxide that includes a same material as the second material and a third material, and a grain boundary is not formed on an interface between at least one of the gate insulating layer and the oxide semiconductor layer or between the oxide semiconductor layer, and the source electrode and the drain electrode.
    Type: Application
    Filed: November 9, 2012
    Publication date: December 5, 2013
    Applicant: Samsung Display Co., Ltd.
    Inventors: Doo Hyoung LEE, Bo Sung Kim, Chan Woo Yang, Seung-Ho Jung, Yeon Taek Jeong, June Whan Choi, Tae-Young Choi
  • Patent number: 8586979
    Abstract: An oxide semiconductor thin film transistor (TFT) and a method of manufacturing the oxide semiconductor TFT. The oxide semiconductor TFT includes a first gate insulating layer arranged between an oxide semiconductor channel layer and a first gate and a second gate insulating layer arranged between the channel layer and a second gate. The first and second gate insulating layers are made out of different materials and have different thicknesses. Preferably, the second gate insulating layer is silicon oxide and is thinner than the first gate insulating layer which is preferably silicon nitride. Oxide semiconductor refers to an oxide material such as Zinc Oxide, Tin Oxide, Ga—In—Zn Oxide, In—Zn Oxide, In—Sn Oxide, and one of Zinc Oxide, Tin Oxide, Ga—In—Zn Oxide, In—Zn Oxide and In—Sn Oxide.
    Type: Grant
    Filed: February 2, 2009
    Date of Patent: November 19, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-Seok Son, Tae-Sang Kim, Jang-Yeon Kwon, Ji-Sim Jung, Sang-Yoon Lee, Myung-Kwan Ryu, Kyung-Bae Park, Byung-Wook Yoo
  • Publication number: 20130299817
    Abstract: A thin film transistor array panel includes: a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, and a data wire layer disposed on the substrate and including a data line intersecting the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode. In addition, at least one of the data line, the source electrode or the drain electrode of the data wire layer includes a barrier layer and a main wiring layer disposed on the barrier layer. The main wiring layer includes copper or a copper alloy. Also, the barrier layer includes a metal oxide, and the metal oxide includes zinc.
    Type: Application
    Filed: October 25, 2012
    Publication date: November 14, 2013
    Applicant: Samsung Display Co., Ltd.
    Inventors: Jae Woo PARK, Do-Hyun Kim, Young Joo Choi, Dong Hoon Lee, Sung Haeng Cho
  • Patent number: 8581244
    Abstract: Example embodiments are directed to oxide thin film transistors and methods of manufacturing the oxide thin film transistors. The oxide thin film transistor includes an active region in a gate insulation layer and under a source and a drain in a bottom gate structure, thus improving electrical characteristics of the oxide thin film transistor.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: November 12, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon Seok Park, Tae Sang Kim
  • Publication number: 20130285044
    Abstract: Embodiments of the present invention relate to a display device, an array substrate, and a thin film transistor. The thin film transistor comprises a gate, an active layer and a gate insulating layer disposed between the gate and the active layer, the active layer is an oxide semiconductor, and the gate insulating layer comprises at least one layer of inorganic insulating thin film. With the gate insulating layer of the thin film transistor, it is possible that an adverse effect on the oxide semiconductor given by hydrogen-containing groups is effectively avoided, stability of the whole TFT device is enhanced to the most extent, and yield of final products is increased.
    Type: Application
    Filed: September 28, 2012
    Publication date: October 31, 2013
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Guangcai YUAN, Woobong LEE
  • Patent number: 8569760
    Abstract: A thin film transistor TFT, including a substrate, a gate electrode on the substrate, a gate insulating layer on the gate electrode, an active layer on the gate insulating layer, the active layer corresponding to the gate electrode and including a channel region, source and drain electrodes contacting the active layer, the source and drain electrodes being separate from each other, and an ohmic contact layer between the active layer and at least one of the source and drain electrodes, the ohmic contact layer including an oxide semiconductor material.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: October 29, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventor: Chun-Gi You
  • Patent number: 8569754
    Abstract: A semiconductor device having a novel structure or a method for manufacturing the semiconductor device is provided. For example, the reliability of a transistor which is driven at high voltage or large current is improved. For improvement of the reliability of the transistor, a buffer layer is provided between a drain electrode layer (or a source electrode layer) and an oxide semiconductor layer such that the end portion of the buffer layer is beyond the side surface of the drain electrode layer (or the source electrode layer) when seen in a cross section, whereby the buffer layer can relieve the concentration of electric field. The buffer layer is a single layer or a stacked layer including a plurality of layers, and includes, for example, an In—Ga—Zn—O film containing nitrogen, an In—Sn—O film containing nitrogen, an In—Sn—O film containing SiOx, or the like.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: October 29, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yusuke Nonaka, Takatsugu Omata, Tatsuya Honda, Akiharu Miyanaga, Hiroki Ohara
  • Patent number: 8563976
    Abstract: A semiconductor device includes an oxide semiconductor layer including a channel formation region which includes an oxide semiconductor having a wide band gap and a carrier concentration which is as low as possible, and a source electrode and a drain electrode which include an oxide conductor containing hydrogen and oxygen vacancy, and a barrier layer which prevents diffusion of hydrogen and oxygen between an oxide conductive layer and the oxide semiconductor layer. The oxide conductive layer and the oxide semiconductor layer are electrically connected to each other through the barrier layer.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: October 22, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto
  • Patent number: 8563088
    Abstract: A method for preparing a Group 1a-1b-3a-6a material using a selenium/Group 1b ink comprising, as initial components: a selenium component comprising selenium, an organic chalcogenide component having a formula selected from RZ—Z?R? and R2—SH, a Group 1b component and a liquid carrier; wherein Z and Z? are each independently selected from sulfur, selenium and tellurium; wherein R is selected from H, C1-20 alkyl group, a C6-20 aryl group, a C1-20 alkylhydroxy group, an arylether group and an alkylether group; wherein R? and R2 are selected from a C1-20 alkyl group, a C6-20 aryl group, a C1-20 alkylhydroxy group, an arylether group and an alkylether group; and wherein the selenium/Group 1b ink is a stable dispersion.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: October 22, 2013
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: Kevin Calzia, David Mosley, David L. Thorsen, Charles R. Szmanda
  • Patent number: 8558233
    Abstract: One embodiment of the present invention is to achieve high mobility in a device using an oxide semiconductor and provide a highly reliable display device. An oxide semiconductor layer including a crystal region in which c-axis is aligned in a direction substantially perpendicular to a surface is formed and an oxide insulating layer is formed over and in contact with the oxide semiconductor layer. Oxygen is supplied to the oxide semiconductor layer by third heat treatment. A nitride insulating layer containing hydrogen is formed over the oxide insulating layer and fourth heat treatment is performed, so that hydrogen is supplied at least to an interface between the oxide semiconductor layer and the oxide insulating layer.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: October 15, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8552434
    Abstract: An object is, in a thin film transistor in which an oxide semiconductor is used as an active layer, to prevent change in composition, film quality, an interface, or the like of an oxide semiconductor region serving as an active layer, and to stabilize electrical characteristics of the thin film transistor. In a thin film transistor in which a first oxide semiconductor region is used as an active layer, a second oxide semiconductor region having lower electrical conductivity than the first oxide semiconductor region is formed between the first oxide semiconductor region and a protective insulating layer for the thin film transistor, whereby the second oxide semiconductor region serves as a protective layer for the first oxide semiconductor region; thus, change in composition or deterioration in film quality of the first oxide semiconductor region can be prevented, and electrical characteristics of the thin film transistor can be stabilized.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: October 8, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Toshinari Sasaki, Hideaki Kuwabara
  • Patent number: 8552425
    Abstract: An object is to provide a semiconductor device having good electrical characteristics. A gate insulating layer having a hydrogen concentration less than 6×1020 atoms/cm3 and a fluorine concentration greater than or equal to 1×1020 atoms/cm3 is used as a gate insulating layer in contact with an oxide semiconductor layer forming a channel region, so that the amount of hydrogen released from the gate insulating layer can be reduced and diffusion of hydrogen into the oxide semiconductor layer can be prevented. Further, hydrogen present in the oxide semiconductor layer can be eliminated with the use of fluorine; thus, the hydrogen content in the oxide semiconductor layer can be reduced. Consequently, the semiconductor device having good electrical characteristics can be provided.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: October 8, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mitsuhiro Ichijo, Toshiya Endo, Kunihiko Suzuki
  • Publication number: 20130256653
    Abstract: A plural semiconductive oxides TFT (sos-TFT) provides improved electrical functionality in terms of charge-carrier mobility and/or threshold voltage variability. The sos-TFT may be used to form a thin film transistor array panel for display devices. An example sos-TFT includes: an insulated gate electrode; a first semiconductive oxide layer having a composition including a first semiconductive oxide; and a second semiconductive oxide layer having a different composition that also includes a semiconductive oxide. The first and second semiconductive oxide layers have respective channel regions that are capacitively influenced by a control voltage applied to the gate electrode. In one embodiment, the second semiconductive oxide layer includes at least one additional element that is not included in the first semiconductive oxide layer where the additional element is one of gallium (Ga), silicon (Si), niobium (Nb), hafnium (Hf), and germanium (Ge).
    Type: Application
    Filed: July 23, 2012
    Publication date: October 3, 2013
    Applicant: SAMSUNG DISPLAY CO., LTD.
    Inventors: Byung Du AHN, Ji Hun LIM, Gun Hee KIM, Kyoung Won LEE, Je Hun LEE
  • Publication number: 20130256652
    Abstract: A thin film transistor, a thin film transistor array panel including the same, and a method of manufacturing the same are provided, wherein the thin film transistor includes a channel region including an oxide semiconductor, a source region and a drain region connected to the channel region and facing each other at both sides with respect to the channel region, an insulating layer positioned on the channel region, and a gate electrode positioned on the insulating layer, wherein an edge boundary of the gate electrode and an edge boundary of the channel region are substantially aligned.
    Type: Application
    Filed: July 19, 2012
    Publication date: October 3, 2013
    Inventors: Yong Su LEE, Yoon Ho Khang, Dong Jo Kim, Hyun Jae Na, Sang Ho Park, Se Hwan Yu, Chong Sup Chang
  • Publication number: 20130256651
    Abstract: A thin film transistor includes a substrate and an active layer formed on the substrate. The active layer includes a channel region, a source region and a drain region. A source electrode and a drain electrode are formed on the source region and the drain region respectively. A gate insulating layer is formed between a gate electrode and the channel region. The thin film transistor further includes a nitride conductive layer formed between the drain electrode and the drain region, and between the source electrode and source region. The nitride conductive layer has a carrier concentration higher than that of the active layer, thereby reducing contacting resistances between the drain electrode and the drain region and between the source electrode and source region.
    Type: Application
    Filed: June 21, 2012
    Publication date: October 3, 2013
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: JIAN-SHIHN TSANG
  • Patent number: 8546181
    Abstract: A highly reliable semiconductor device is provided. A semiconductor device is manufactured at a high yield, so that high productivity is achieved. In a semiconductor device including a transistor in which a gate electrode layer, a gate insulating film, an oxide semiconductor film containing indium, and an insulating layer provided on and in contact with the oxide semiconductor film so as to overlap with the gate electrode layer are stacked and a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor film and the insulating layer, the chlorine concentration and the indium concentration on a surface of the insulating layer are lower than or equal to 1×1019/cm3 and lower than or equal to 2×1019/cm3, respectively.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: October 1, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8546182
    Abstract: An object is, in a thin film transistor in which an oxide semiconductor is used as an active layer, to prevent change in composition, film quality, an interface, or the like of an oxide semiconductor region serving as an active layer, and to stabilize electrical characteristics of the thin film transistor. In a thin film transistor in which a first oxide semiconductor region is used as an active layer, a second oxide semiconductor region having lower electrical conductivity than the first oxide semiconductor region is formed between the first oxide semiconductor region and a protective insulating layer for the thin film transistor, whereby the second oxide semiconductor region serves as a protective layer for the first oxide semiconductor region; thus, change in composition or deterioration in film quality of the first oxide semiconductor region can be prevented, and electrical characteristics of the thin film transistor can be stabilized.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: October 1, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Toshinari Sasaki, Hideaki Kuwabara
  • Publication number: 20130248850
    Abstract: A thin film transistor includes a source electrode, a drain electrode, a channel portion disposed between the source electrode and the drain electrode, and a gate electrode disposed on the channel portion and insulated from the channel portion. The source electrode, the drain electrode, and the channel portion are disposed on a same layer. A display apparatus includes a display device and the thin film transistor that applies a driving signal to the display device.
    Type: Application
    Filed: August 10, 2012
    Publication date: September 26, 2013
    Inventors: Tae-Young CHOI, Bo Sung Kim, Byungju Lee, Kangmoon Jo
  • Patent number: 8536571
    Abstract: A manufacturing method of a semiconductor device includes the steps of: forming a gate electrode over a substrate; forming a gate insulating film over the gate electrode; forming an oxide semiconductor film; performing heat treatment to form a second oxide semiconductor film after the step of forming the first oxide semiconductor film; forming a first conductive film; forming a first resist mask including regions whose thicknesses are different; etching the second oxide semiconductor film and the first conductive film using the first resist mask to form a third oxide semiconductor film and a second conductive film; reducing the size of the first resist mask to form a second resist mask; selectively etching the second conductive film using the second resist mask to remove a part of the second conductive film so that a source electrode and a drain electrode are formed.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: September 17, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8530893
    Abstract: A display substrate includes a gate wire formed on an insulating substrate, a semiconductor pattern formed on the gate wire and containing a metal oxynitride compound, and a data wire formed on the semiconductor pattern to cross the gate wire. The semiconductor pattern has a carrier number density ranging from 1016/cm3 to 1019/cm3.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: September 10, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ki-Won Kim, Kyoung-Jae Chung, Hye-Young Ryu, Young-Joo Choi, Seung-Ha Choi, Kap-Soo Yoon
  • Patent number: 8525166
    Abstract: Methods of forming transparent zinc-tin oxide structures are described. Devices that include transparent zinc-tin oxide structures as at least one of a channel layer in a transistor or a transparent film disposed over an electrical device that is at a substrate.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: September 3, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8519387
    Abstract: An insulating layer which releases a large amount of oxygen is used as an insulating layer in contact with a channel region of an oxide semiconductor layer, and an insulating layer which releases a small amount of oxygen is used as an insulating layer in contact with a source region and a drain region of the oxide semiconductor layer. By releasing oxygen from the insulating layer which releases a large amount of oxygen, oxygen deficiency in the channel region and an interface state density between the insulating layer and the channel region can be reduced, so that a highly reliable semiconductor device having small variation in electrical characteristics can be manufactured. The source region and the drain region are provided in contact with the insulating layer which releases a small amount of oxygen, thereby suppressing the increase of the resistance of the source region and the drain region.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: August 27, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Endo, Kosei Noda, Toshinari Sasaki