For Device Having Potential Or Surface Barrier (epo) Patents (Class 257/E31.037)
  • Patent number: 12009440
    Abstract: The disclosure relates to the technical field of solar cells, and provides a solar cell and a doped region structure thereof, a cell assembly, and a photovoltaic system. The doped region structure includes a first doped layer, a passivation layer, and a second doped layer that are disposed on a silicon substrate in sequence. The passivation layer is a porous structure having the first doped layer and/or the second doped layer inlaid in a hole region. The first doped layer and the second doped layer have a same doping polarity. By means of the doped region structure of the solar cell provided in the disclosure, the difficulty in production and the limitation on conversion efficiency as a result of precise requirements for the accuracy of a thickness of a conventional tunneling layer are resolved.
    Type: Grant
    Filed: September 29, 2023
    Date of Patent: June 11, 2024
    Assignee: Solarlab Aiko Europe GmbH
    Inventors: Gang Chen, Wenli Xu, Kaifu Qiu, Yongqian Wang, Xinqiang Yang
  • Patent number: 11860033
    Abstract: A photodetector includes: at least one avalanche photodiode including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type; a first transistor connected to the first semiconductor layer and including a channel of the second conductivity type that has polarity opposite to polarity of the first conductivity type; and a second transistor connected to the first semiconductor layer and including a channel of the first conductivity type.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: January 2, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Akito Inoue, Mitsuyoshi Mori, Yusuke Sakata, Motonori Ishii
  • Patent number: 11837669
    Abstract: A dynamic photodiode may comprise a substrate comprising a first surface opposite a second surface, the substrate being of a first doping type; a substrate region disposed on the first surface, the substrate region comprising a substrate contact configured to be grounded; a first doped region disposed on the first surface, the first doped region being of the first doping type and comprising a first contact configured to receive a first voltage; a second doped region disposed on the first surface, the second doped region being of a second doping type opposite to the first doping type and comprising a second contact configured to receive a second voltage. The substrate region may surround the second doped region, the second doped region may surround the first doped region, and exposed portions of the substrate form light absorbing regions may be configured to generate electron-hole pairs in the substrate.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: December 5, 2023
    Assignee: ActLight SA
    Inventors: Denis Sallin, Maxim Gureev, Serguei Okhonin
  • Patent number: 11837671
    Abstract: The disclosure relates to the technical field of solar cells, and provides a solar cell and a doped region structure thereof, a cell assembly, and a photovoltaic system. The doped region structure includes a first doped layer, a passivation layer, and a second doped layer that are disposed on a silicon substrate in sequence. The passivation layer is a porous structure having the first doped layer and/or the second doped layer inlaid in a hole region. The first doped layer and the second doped layer have a same doping polarity. By means of the doped region structure of the solar cell provided in the disclosure, the difficulty in production and the limitation on conversion efficiency as a result of precise requirements for the accuracy of a thickness of a conventional tunneling layer are resolved.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: December 5, 2023
    Assignee: SOLARLAB AIKO EUROPE GMBH
    Inventors: Gang Chen, Wenli Xu, Kaifu Qiu, Yongqian Wang, Xinqiang Yang
  • Patent number: 11749761
    Abstract: The disclosure relates to the technical field of solar cells, and provides a solar cell and a doped region structure thereof, a cell assembly, and a photovoltaic system. The doped region structure includes a first doped layer, a passivation layer, and a second doped layer that are disposed on a silicon substrate in sequence. The passivation layer is a porous structure having the first doped layer and/or the second doped layer inlaid in a hole region. The first doped layer and the second doped layer have a same doping polarity. By means of the doped region structure of the solar cell provided in the disclosure, the difficulty in production and the limitation on conversion efficiency as a result of precise requirements for the accuracy of a thickness of a conventional tunneling layer are resolved.
    Type: Grant
    Filed: October 24, 2021
    Date of Patent: September 5, 2023
    Assignee: SOLARLAB AIKO EUROPE GMBH
    Inventors: Gang Chen, Wenli Xu, Kaifu Qiu, Yongqian Wang, Xinqiang Yang
  • Patent number: 11581442
    Abstract: Discussed is a solar cell including a first conductive region positioned at a front surface of a semiconductor substrate and containing impurities of a first conductivity type or a second conductivity type, a second conductive region positioned at a back surface of the semiconductor substrate and containing impurities of a conductivity type opposite a conductivity type of impurities of the first conductive region, a first electrode positioned on the front surface of the semiconductor substrate and connected to the first conductive region, and a second electrode positioned on the back surface of the semiconductor substrate and connected to the second conductive region. Each of the first and second electrodes includes metal particles and a glass frit.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: February 14, 2023
    Assignee: SHANGRAO JINKO SOLAR TECHNOLOGY DEVELOPMENT CO LTD
    Inventors: Haejong Cho, Donghae Oh, Juhwa Cheong, Junyong Ahn
  • Patent number: 8963169
    Abstract: Photonic devices monolithically integrated with CMOS are disclosed, including sub-100 nm CMOS, with active layers comprising acceleration regions, light emission and absorption layers, and optional energy filtering regions. Light emission or absorption is controlled by an applied voltage to deposited films on a pre-defined CMOS active area of a substrate, such as bulk Si, bulk Ge, Thick-Film SOI, Thin-Film SOI, Thin-Film GOI.
    Type: Grant
    Filed: July 28, 2005
    Date of Patent: February 24, 2015
    Assignee: Quantum Semiconductor LLC
    Inventor: Carlos J. R. P. Augusto
  • Patent number: 8853526
    Abstract: Photovoltaic devices are driven by intense photoemission of “hot” electrons from a suitable nanostructured metal. The metal should be an electron source with surface plasmon resonance within the visible and near-visible spectrum range (near IR to near UV (about 300 to 1000 nm)). Suitable metals include silver, gold, copper and alloys of silver, gold and copper with each other. Silver is particularly preferred for its advantageous opto-electronic properties in the near UV and visible spectrum range, relatively low cost, and simplicity of processing.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: October 7, 2014
    Assignee: The Regents of The University of California
    Inventors: Robert Kostecki, Samuel Mao
  • Patent number: 8742413
    Abstract: In a photosensor and a method of manufacturing the same, the photosensor comprises: an intrinsic silicon layer formed on a substrate; a P-type doped region formed in a same plane with the intrinsic silicon layer; and an oxide semiconductor layer formed on or under the intrinsic silicon layer, and overlapping an entire region of the intrinsic silicon layer.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: June 3, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jae-Hwan Oh, Won-Kyu Lee, Seong-Hyun Jin, Young-Jin Chang, Jae-Beom Choi
  • Patent number: 8697477
    Abstract: Disclosed herein is a method for producing a solid-state imaging element which has pixels, each including a sensor section that performs photoelectric conversion and a charge transfer section that transfers charges generated by the sensor section. The method includes: forming an impurity region of the first conduction type and a second impurity region of the second conduction type on the impurity region of the first conduction type by ion implantation by using the same mask; forming on the surface of the semiconductor substrate a transfer gate constituting the charge transfer section which extends over the second impurity region of the second conduction type; forming a charge accumulating region of the first conduction type constituting the sensor section by ion implantation; and forming a first impurity region of the second conduction type, which has a higher impurity concentration than the second impurity region of the second conduction type, by ion implantation.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: April 15, 2014
    Assignee: Sony Corporation
    Inventors: Sanghoon Ha, Hiroaki Ishiwata
  • Publication number: 20140076390
    Abstract: A method of depositing III-V solar collection materials on a GeSn template on a silicon substrate including the steps of providing a crystalline silicon substrate and epitaxially growing a single crystal GeSn layer on the silicon substrate using a grading profile to grade Sn through the layer. The single crystal GeSn layer has a thickness in a range of approximately 3 ?m to approximately 5 ?m. A layer of III-V solar collection material is epitaxially grown on the graded single crystal GeSn layer. The graded single crystal GeSn layer includes Sn up to an interface with the layer of III-V solar collection material.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Inventors: Radek Roucka, Michael Lebby, Scott Semans
  • Patent number: 8659107
    Abstract: A radiation receiver has a semiconductor body including a first active region and a second active region, which are provided in each case for detecting radiation. The first active region and the second active region are spaced vertically from one another. A tunnel region is arranged between the first active region and the second active region. The tunnel region is connected electrically conductively with a land, which is provided between the first active region and the second active region for external electrical contacting of the semiconductor body. A method of producing a radiation receiver is additionally indicated.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: February 25, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Rainer Butendeich, Reiner Windisch
  • Publication number: 20140048122
    Abstract: A photovoltaic device that includes an upper cell that absorbs a first range of wavelengths of light and a bottom cell that absorbs a second range of wavelengths of light. The bottom cell includes a heterojunction comprising a crystalline germanium containing (Ge) layer. At least one surface of the crystalline germanium (Ge) containing layer is in contact with a silicon (Si) containing layer having a larger band gap than the crystalline (Ge) containing layer.
    Type: Application
    Filed: August 15, 2012
    Publication date: February 20, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Keith E. Fogel, Bahman Hekmatshoartabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Publication number: 20130164882
    Abstract: Disclosed is a method which includes forming a bottom metallic electrode on an insulating substrate; forming a semiconductor junction on the metallic electrode; forming a transparent conducting overlayer in contact with the semiconductor junction; and forming a metallic layer in contact with the transparent conducting overlayer, wherein the metallic layer is formed by a plating process. The plating process may be an electroplating process or an electroless plating process. The transparent conducting overlayer may be carbon nanotubes or graphene. The semiconductor junction may be a p-i-n semiconductor junction, a p-n semiconductor junction, an n-p semiconductor junction or an n-i-p semiconductor junction.
    Type: Application
    Filed: December 23, 2011
    Publication date: June 27, 2013
    Applicant: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Ageeth A. Bol, Mostafa M. EI-Ashry, Amal Kasry, Ahmed Maarouf, Glenn J. Martyna, Dennis M. Newns, Razvan Nistor, George S. Tulevski
  • Patent number: 8445310
    Abstract: The present invention provides a stacked-layered thin film solar cell and manufacturing method thereof The manufacturing method includes the steps of: providing a substrate, a first electrode layer and a first light-absorbing layer; providing a mask with a plurality of patterns above the first light-absorbing layer; forming an interlayer made of an opaque, highly reflective material by providing the mask on the first light-absorbing layer, wherein the interlayer has a plurality of light transmissive regions corresponding to the patterns, and the light transmissive regions are provided to divide the interlayer into a plurality of units; and then depositing a second light-absorbing layer on the units and a second electrode layer on the second light-absorbing layer.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: May 21, 2013
    Assignee: Nexpower Technology Corp.
    Inventors: Chien-Chung Bi, Chun-Hsiung Lu
  • Publication number: 20130099205
    Abstract: An electrical device comprising (A) a substrate having a surface and (B) a nanohole superlattice superimposed on a portion of the surface is provided. The nanohole superlattice comprises a plurality of sheets having an array of holes defined therein. The array of holes is characterized by a band gap or band gap range. The plurality of sheets forms a first edge and a second edge. A first lead comprising a first electrically conductive material forms a first junction with the first edge. A second lead comprising a second electrically conductive material forms a second junction with the second edge. The first junction is a Schottky barrier with respect to a carrier. In some instances a metal protective coating covers all or a portion of a surface of the first lead. In some instances, the first lead comprises titanium, the second lead comprises palladium, and the metal protective coating comprises gold.
    Type: Application
    Filed: October 19, 2012
    Publication date: April 25, 2013
    Applicant: University of Utah Research Foundation
    Inventor: University of Utah Research Foundation
  • Publication number: 20130092980
    Abstract: A photodetector structure can include a silicon substrate and a silicon layer on the silicon substrate, that can include a first portion of an optical transmission medium that further includes a silicon cross-sectional transmission face. A germanium layer can be on the silicon substrate and can include a second portion of the optical transmission medium, adjacent to the first portion can include a germanium cross-sectional transmission face butt-coupled to the silicon cross-sectional transmission face.
    Type: Application
    Filed: October 12, 2012
    Publication date: April 18, 2013
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Samsung Electronics Co., Ltd.
  • Publication number: 20130095599
    Abstract: An electronic device includes a substrate and a plurality of particles anchored to the substrate. An electrode material is formed over the particles and configured to form peaks over the particles. One or more operational layers are fog led over the electrode material for performing a device function.
    Type: Application
    Filed: October 18, 2011
    Publication date: April 18, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: AHMED ABOU-KANDIL, Keith E. Fogel, Augustin J. Hong, Jeehwan Kim, Hisham S. Mohamed, Devendra K. Sadana
  • Publication number: 20130081679
    Abstract: A low-cost method is provided for forming a photovoltaic device, which is a high-performance nanostructured multijunction cell. The multiple P-N junctions or P-I-N junctions are contiguously joined to form a single contiguous P-N junction or a single contiguous P-I-N junction. The photovoltaic device integrates vertically-aligned semiconductor nanowires including a doped semiconductor material with a thin silicon layer having an opposite type of doping. This novel hybrid cell can provide a higher efficiency than conventional photovoltaic devices through the combination of the enhanced photon absorptance, reduced contact resistance, and short carrier transport paths in the nanowires. Room temperature processes or low temperature processes such as plasma-enhanced chemical vapor deposition (PECVD) and electrochemical processes can be employed for fabrication of this photovoltaic device in a low-cost, scalable, and energy-efficient manner.
    Type: Application
    Filed: September 30, 2011
    Publication date: April 4, 2013
    Applicant: UT-BATTELLE, LLC
    Inventors: Jun Qu, Theodore M. Besmann, Sheng Dai, Xiaoguang Zhang
  • Publication number: 20130062604
    Abstract: A photodetector includes a semiconductor substrate having an irradiation zone configured to generate charge carriers having opposite charge carrier types in response to an irradiation of the semiconductor substrate. The photodetector further includes an inversion zone generator configured to operate in at least two operating states to generate different inversion zones within the substrate, wherein a first inversion zone generated in a first operating state differs from a second inversion zone generated in a second operating state, and wherein the first inversion zone and the second inversion zone have different extensions in the semiconductor substrate. A corresponding method for manufacturing a photodetector and a method for determining a spectral characteristic of an irradiation are also described.
    Type: Application
    Filed: September 14, 2011
    Publication date: March 14, 2013
    Applicant: Infineon Technologies AG
    Inventor: Thoralf Kautzsch
  • Publication number: 20130049155
    Abstract: A photosite is formed in a semiconductor substrate and includes a photodiode confined in a direction orthogonal to the surface of the substrate. The photodiode includes a semiconductor zone for storing charge that is formed in an upper semiconductor region having a first conductivity type and includes a main well of a second conductivity type opposite the first conductivity type and laterally pinned in a first direction parallel to the surface of the substrate. The photodiode further includes an additional semiconductor zone including an additional well having the second conductivity type that is buried under and makes contact with the main well.
    Type: Application
    Filed: June 21, 2012
    Publication date: February 28, 2013
    Applicants: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS S.A.
    Inventors: Francois Roy, Julien Michelot
  • Publication number: 20130037854
    Abstract: A photodetector is provided, comprising: a radiation-absorbing semiconductor region and a collection semiconductor region separated by and each in contact with a barrier semiconductor region; wherein, at least in the absence of an applied bias voltage, the band gap between the valence band energy and the conduction band energy of the barrier semiconductor region is offset from the band gap between the valence band energy and the conduction band energy of the radiation-absorbing semiconductor region so as to form an energy barrier between the radiation-absorbing semiconductor region and the collection semiconductor region which resists the flow of minority carriers from the radiation-absorbing semiconductor region to the collection semiconductor region. Also provided is a method of manufacturing a photodetector.
    Type: Application
    Filed: August 10, 2011
    Publication date: February 14, 2013
    Applicant: BAH Holdings LLC
    Inventor: Michael TKACHUK
  • Publication number: 20130034929
    Abstract: A method includes forming a blocking layer over a substrate, and etching the blocking layer to form a trench in the blocking layer. A dielectric layer is formed, wherein the dielectric layer comprises a first portion over the blocking layer, and a second portion in the trench. After the step of forming the dielectric layer, an implantation is performed to implant an impurity into the substrate to form a deep well region. After the implantation, the dielectric layer and the blocking layer are removed.
    Type: Application
    Filed: August 2, 2011
    Publication date: February 7, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Chung Su, Shih-Chang Liu, Shih Pei Chou, Chia-Shiung Tsai, Chun-Tsung Kuo, Wen-I Hsu, Yi-Shin Chu
  • Publication number: 20120329201
    Abstract: Certain embodiments provide method for manufacturing a solid-state imaging device, including forming an electrode and forming a second impurity layer. The electrode is formed on a semiconductor substrate including a first impurity layer of a first conductivity type on a surface. The second impurity layer is a second conductivity type and is formed by implanting an impurity of a second conductivity type into the first impurity layer in an oblique direction with respect to the surface of the semiconductor substrate on the condition that the impurity penetrates an end portion of the electrode, based on a position of the electrode. The second impurity layer is bonded to the first impurity layer to constitute a photodiode, and a portion of the second impurity layer is disposed under the electrode.
    Type: Application
    Filed: March 12, 2012
    Publication date: December 27, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Ken TOMITA, Atsushi SASAKI
  • Publication number: 20120329194
    Abstract: The invention relates to a method for treating a silicon substrate for the production of photovoltaic cells against reduction in yield during the illumination of said photovoltaic cells. The invention also relates to a method for producing photovoltaic cells from the treated substrate. To said end, the invention relates to a method for treating a silicon substrate for the production of photovoltaic cells, said method including the following steps: a) providing a silicon substrate obtained from a metallurgically purified load, and b) annealing said substrate by heating the substrate to a temperature between 880° C. and 930° C. for a duration of between one and four hours, preferably at a temperature of 900° C., give or take 10° C., for two hours, give or take 10 minutes.
    Type: Application
    Filed: December 8, 2010
    Publication date: December 27, 2012
    Applicant: COMMISSARIAT A'LENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sébastien Dubois, Nicolas Enjalbert
  • Publication number: 20120326260
    Abstract: A photodiode comprises a first terminal formed in a surface of a semiconductor substrate; a second terminal formed in the substrate surface and spaced apart from the first terminal; and a plurality of adjacent alternating N-type and P-type diffusion regions formed in the substrate surface between the first terminal and the second terminal.
    Type: Application
    Filed: June 21, 2011
    Publication date: December 27, 2012
    Inventors: William French, Peter J. Hopper, Philipp Lindorfer, Vladislav Vashchenko
  • Publication number: 20120313200
    Abstract: Methods and devices are provided for forming multi-nary semiconductor. In one embodiment, a method is provided comprising of depositing a precursor material onto a substrate, wherein the precursor material may include or may be used with an additive to minimize concentration of group IIIA material such as Ga in the back portion of the final semiconductor layer. The additive may be a non-copper Group IB additive in elemental or alloy form. Some embodiments may use both selenium and sulfur, forming a senary or higher semiconductor alloy. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Application
    Filed: June 26, 2012
    Publication date: December 13, 2012
    Applicant: Nanosolar, Inc.
    Inventors: David B. Jackrel, Katherine Dickey, Kristin Pollock, Jacob Woodruff, Peter Stone, Gregory Brown
  • Publication number: 20120204930
    Abstract: A thin-layer solar module includes a plurality of interconnected solar cells, having in the order indicated the layers (a) a substrate 3; (b) a first electrode layer 4; (c) a semiconductor layer 5; and (d) a second electrode layer 6. At least one non-linear recess is disposed in the first electrode layer and a second non-linear recess is disposed in the second electrode layer and in the semiconductor layer, wherein a first projection of the first non-linear recess onto the substrate 3 and a second projection 10 of the second non-linear recess onto the substrate intersect or contact each other at least two projection points. The thin-layer solar module has at least one island-shaped contact region extending in a direction vertical to the substrate through the layers (a) through (d). A third recess is present in the semiconductor layer 5 within the island-shaped contact region 11 and is filled with an electrically conductive material.
    Type: Application
    Filed: July 20, 2010
    Publication date: August 16, 2012
    Applicant: Q-CELLS SE
    Inventor: Victor Verdugo
  • Publication number: 20120182063
    Abstract: The present invention belongs to the technical field of semiconductor devices, and discloses a power device using photoelectron injection to modulate conductivity and the method thereof. The power device comprises at least one photoelectron injection light source and a power MOS transistor. The present invention uses photoelectron injection method to inject carriers to the drift region under the gate of the power MOS transistor, thus modulating the conductivity and further decreasing the specific on-resistance of the power MOS transistor. Moreover, as the doping concentration of the drift region can be decreased and the blocking voltage can be increased, the performance of the power MOS transistor can be greatly improved and the application of power MOS transistor can be expanded to high-voltage fields.
    Type: Application
    Filed: April 21, 2011
    Publication date: July 19, 2012
    Applicant: Fundan University
    Inventors: Pengfei Wang, Qingqing Sun, Shijin Ding, Wei Zhang
  • Publication number: 20120175677
    Abstract: A photocell which operates at multiple wavelengths for efficient power generation from broadband incident radiation. According to a preferred embodiment, the photocell is a multi-layer device that includes a first outer layer, a middle layer and an inner layer disposed on a substrate. All three layers are formed from II-VI semiconductor layers. The device is arranged such that the outer layer has a high band gap, the middle layer has a band gap which is less than half the band gap of the outer layer and the inner layer has a band gap which is less than half that of the substrate. Thus, there is a step change in band gap between various layers.
    Type: Application
    Filed: September 21, 2010
    Publication date: July 12, 2012
    Applicant: QINETIQ LIMITED
    Inventors: Neil Thomson Gordon, Timothy Ashley
  • Patent number: 8183657
    Abstract: A solid state imaging device, includes: a sensor cell array having a plurality of sensor cells arranged in a matrix on a substrate, each sensor cell including: a photoelectric transducer provided in the substrate and generating photo-generated electric charges according to an incident light; a transfer gate formed on the substrate with a gate insulating layer therebetween; a charge retention region formed under the gate insulating layer and storing the photo-generated electric charges that are transferred from the photoelectric transducer by applying a predetermined potential to the transfer gate; a buried layer formed between the charge retention region and the gate insulating layer; and a floating diffusion storing the photo-generated electric charges that are transferred from the charge retention region by applying a predetermined potential to the transfer gate.
    Type: Grant
    Filed: September 15, 2005
    Date of Patent: May 22, 2012
    Assignee: Seiko Epson Corporation
    Inventor: Kazunobu Kuwazawa
  • Publication number: 20120097226
    Abstract: A solar cell includes a semiconductor substrate including a first conductive type, a first amorphous silicon thin film layer disposed on the semiconductor substrate and a second amorphous silicon thin film layer including a second conductive type and disposed on the first amorphous silicon thin film layer. The first amorphous silicon thin film layer includes a first intrinsic silicon thin film layer, a second intrinsic silicon thin film layer facing the semiconductor substrate while interposing the first intrinsic silicon thin film layer therebetween and a first low concentration silicon thin film layer including the second conductive type and disposed between the first intrinsic silicon thin film layer and the second intrinsic silicon thin film layer.
    Type: Application
    Filed: June 14, 2011
    Publication date: April 26, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD
    Inventors: HOON HA JEON, Min Seok OH, NAMKYU SONG, MIN PARK,, YEONIK JANG, Yun-Seok LEE, Cho-Young LEE
  • Publication number: 20120056243
    Abstract: A photodetector 1 according to an embodiment of the present invention includes: an n-type InAs substrate 12; an n-type InAs buffer layer 14 formed on the n-type InAs substrate 12; an n-type InAs light absorbing layer 16 formed on the n-type InAs buffer layer 14; an InAsXPYSb1-X-Y cap layer 18 (X?0, Y>0) formed on the n-type InAs light absorbing layer 16; a first inorganic insulating film 20 formed on the cap layer 18, and having an opening portion 20h in a deposition direction; a p-type impurity semiconductor region 24 fowled by diffusing a p-type impurity from the opening portion 20h of the first inorganic insulating film 20, and reaching from the cap layer 18 to an upper layer of the n-type InAs light absorbing layer 16; and a second inorganic insulating film 22 formed on the first inorganic insulating film 20 and on the p-type impurity semiconductor region 24.
    Type: Application
    Filed: November 10, 2011
    Publication date: March 8, 2012
    Inventor: Akihito YOKOI
  • Publication number: 20120052621
    Abstract: Methods are generally provided for manufacturing such thin film photovoltaic devices via sputtering a mixed phase layer from a target (e.g., at least including CdSOx, where x is 3 or 4) on a transparent conductive oxide layer and depositing a cadmium telluride layer on the mixed layer. The transparent conductive oxide layer is on a glass substrate.
    Type: Application
    Filed: May 31, 2011
    Publication date: March 1, 2012
    Applicant: PRIMESTAR SOLAR, INC.
    Inventors: Scott Daniel Feldman-Peabody, Robert Dwayne Gossman
  • Publication number: 20120052620
    Abstract: Thin film photovoltaic devices are provided that generally include a transparent conductive oxide layer on the glass, a multi-layer n-type stack on the transparent conductive oxide layer, and an absorber layer (e.g., a cadmium telluride layer) on the multi-layer n-type stack. The multi-layer n-type stack generally includes a first layer (e.g., a cadmium sulfide layer) and a second layer (e.g., a mixed phase layer). The multi-layer n-type stack can, in certain embodiments, include additional layers (e.g., a third layer, a fourth layer, etc.). Methods are also generally provided for manufacturing such thin film photovoltaic devices.
    Type: Application
    Filed: May 31, 2011
    Publication date: March 1, 2012
    Applicant: PRIMESTAR SOLAR, INC.
    Inventors: Scott Daniel Feldman-Peabody, Robert Dwayne Gossman
  • Publication number: 20120028407
    Abstract: Thin film photovoltaic devices are provided that generally include a transparent conductive oxide layer on the glass, a multi-layer n-type stack on the transparent conductive oxide layer, and a cadmium telluride layer on the multi-layer n-type stack. The multi-layer n-type stack generally includes a first layer and a second layer, where the first layer comprises cadmium and sulfur and the second layer comprises cadmium and oxygen. The multi-layer n-type stack can, in certain embodiments, include additional layers (e.g., a third layer, a fourth layer, etc.). Methods are also generally provided for manufacturing such thin film photovoltaic devices.
    Type: Application
    Filed: May 31, 2011
    Publication date: February 2, 2012
    Applicant: PRIMESTAR SOLAR, INC.
    Inventors: Scott Daniel Feldman-Peabody, Robert Dwayne Gossman
  • Publication number: 20120015473
    Abstract: A photoelectric conversion device manufacturing method manufactures a photoelectric conversion device in which a first photoelectric conversion unit and a second photoelectric conversion unit are sequentially stacked on a transparent-electroconductive film formed on a substrate. The method includes: forming each of a first p-type semiconductor layer, a first i-type semiconductor layer, a first n-type semiconductor layer, and a second p-type semiconductor layer in a plurality of first plasma CVD reaction chambers; exposing the second p-type semiconductor layer to an air atmosphere; supplying a gas including p-type impurities to inside a second plasma CVD reaction chamber before forming of the second i-type semiconductor layer; forming the second i-type semiconductor layer on the second p-type semiconductor layer that was exposed to an air atmosphere, in the second plasma CVD reaction chamber; and forming the second n-type semiconductor layer on the second i-type semiconductor layer.
    Type: Application
    Filed: January 29, 2010
    Publication date: January 19, 2012
    Applicant: ULVAC, INC.
    Inventors: Hiroto Uchida, Tetsushi Fujinaga, Masafumi Wakai, Tadamasa Kobayashi, Yoshinobu Ue, Kyuzo Nakamura, Shin Asari, Kazuya Saito, Koichi Matsumoto, Yasuo Shimizu, Katsuhiko Mori
  • Publication number: 20120012173
    Abstract: A method for manufacturing a solar cell includes disposing a first doping layer on a substrate, disposing a diffusion preventing layer on the first doping layer, patterning the first doping layer and the diffusion preventing layer to expose a portion of the substrate, forming a second doping layer which is disposed on the exposed portion of the substrate on the diffusion preventing layer, diffusing an impurity from the first doping layer to form a first doping region in a surface of the substrate and diffusing an impurity from the second doping layer to form a second doping region in the surface of the substrate surface, wherein the exposed portion of the substrate formed by patterning the first doping layer and the diffusion preventing layer and a portion of the remaining first doping layer and the diffusion preventing layer which are not patterned are alternately arranged with a lattice shape, and the first doping region and the second doping region are alternately arranged with the lattice shape.
    Type: Application
    Filed: February 16, 2011
    Publication date: January 19, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Su KIM, Chan Bin MO
  • Publication number: 20110315201
    Abstract: Embodiments of the present invention provide methods to fabricate semiconductor nanostructure/polymer heterojunctions of solar cells. The methods comprise that a conductive polymer is adhered on the surface of semiconductor nanostructures by capillary effect and core-sheath shaped heterojunctions are formed. The incident photo-to-current conversion efficiency (IPCE) of the solar cells having core-sheath heterojunctions can reach 30% or more.
    Type: Application
    Filed: December 22, 2010
    Publication date: December 29, 2011
    Applicant: NATIONAL TAIWAN UNIVERSITY
    Inventors: CHING-FUH LIN, SHU-JIA SYU
  • Publication number: 20110308588
    Abstract: A photoelectric conversion device having a high electric generating capacity at low illuminance, in which a semiconductor layer is appropriately separated and short circuit of a side surface portion of a cell is prevented. The photoelectric conversion device includes an isolation groove formed between one first electrode and the other first electrode that is adjacent to the one first electrode; a stack including a first semiconductor layer having one conductivity type over the first electrode, a second semiconductor layer formed using an intrinsic semiconductor, and a third semiconductor layer having a conductivity type opposite to the one conductivity type; and a connection electrode connecting one first electrode and a second electrode that is in contact with a third semiconductor layer included in a stack formed over the other first electrode that is adjacent to the one first electrode. A side surface portion of the second semiconductor layer is not crystallized.
    Type: Application
    Filed: June 14, 2011
    Publication date: December 22, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kazuo NISHI, Takashi HIROSE, Naoto KUSUMOTO
  • Publication number: 20110297213
    Abstract: An energy efficient triple junction InGaP/GaAs/Ge solar cell. In one embodiment, the triple junction InGaP/GaAs/Ge solar cell includes: a bottom Ge layer; a first tunnel junction layer above the bottom Ge layer; a middle GaAs layer above the first tunnel junction layer; a second tunnel junction layer above the middle GaAs layer; and a top InGaP layer above the second tunnel junction layer.
    Type: Application
    Filed: January 12, 2010
    Publication date: December 8, 2011
    Inventor: Michael Hideto Tsutagawa
  • Publication number: 20110290310
    Abstract: A solar cell capable of restricting carrier loss and yields higher energy conversion efficiency than was conventionally possible and a method of producing a solar cell enabling formation of a light absorbing layer containing quantum dots through a low-temperature process using a coating or printing method requiring no vacuum equipment or complicated apparatuses. The solar cell includes a light absorbing layer containing quantum dots in a matrix layer, and the light absorbing layer is connected to an N-type semiconductor layer on one side and to a P-type semiconductor layer on the other side. In the light absorbing layer, the quantum dots are made of nanocrystalline semiconductor and arranged 3-dimensionally uniformly enough and spaced regularly so that a plurality of wave functions lie on one another between adjacent quantum dots to form intermediate bands. The matrix layer is formed of amorphous IGZO.
    Type: Application
    Filed: May 26, 2011
    Publication date: December 1, 2011
    Inventors: Teruhiko KURAMACHI, Makoto Kikuchi, Takeshi Hama, Atsushi Tanaka, Youichi Hosoya
  • Publication number: 20110272016
    Abstract: In one embodiment, a solar cell has base and emitter diffusion regions formed on the back side. The emitter diffusion region is configured to collect minority charge carriers in the solar cell, while the base diffusion region is configured to collect majority charge carriers. The emitter diffusion region may be a continuous region separating the base diffusion regions. Each of the base diffusion regions may have a reduced area to decrease minority charge carrier recombination losses without substantially increasing series resistance losses due to lateral flow of majority charge carriers. Each of the base diffusion regions may have a dot shape, for example.
    Type: Application
    Filed: July 19, 2011
    Publication date: November 10, 2011
    Inventors: Denis DE CEUSTER, Peter John COUSINS
  • Publication number: 20110265867
    Abstract: A template for three-dimensional thin-film solar cell substrate formation for use in three-dimensional thin-film solar cells. The template comprises a substrate which comprises a plurality of posts and a plurality of trenches between said plurality of posts. The template forms an environment for three-dimensional thin-film solar cell substrate formation.
    Type: Application
    Filed: May 3, 2011
    Publication date: November 3, 2011
    Applicant: Solexel, Inc.
    Inventor: Mehrdad Moslehi
  • Publication number: 20110220193
    Abstract: A photovoltaic cell including a substrate composed of a semiconductor of a first type of conductivity including two main faces substantially parallel with one another, the substrate including a plurality of blind holes, openings of which are positioned in a single one of the two main faces, and the blind holes filled by a semiconductor of a second type of conductivity opposed to the first type of conductivity forming an emitter of the photovoltaic cell. The substrate forms a base of the photovoltaic cell. First collector pins composed of a semiconductor of the second type of conductivity are in contact with the emitter of the photovoltaic cell, and second collector pins composed of a semiconductor of the first type of conductivity are in contact with the substrate and interdigitated with the first collector pins.
    Type: Application
    Filed: November 20, 2009
    Publication date: September 15, 2011
    Applicant: Commissariat A L'energie Atomique ET Aux Ene Alt
    Inventors: Jean-Paul Garandet, Luc Federzoni, Yannick Veschetti
  • Publication number: 20110159635
    Abstract: An image sensor having an imaging area that includes a substrate layer and a plurality of pixels formed therein. Multiple pixels each include a photodetector formed in the substrate layer. Isolation layers are formed in the substrate layer by performing a series of implants of one or more dopants of a first conductivity type into the substrate layer. Each isolation layer implant is performed with a different energy than the other isolation layer implants in the series and each implant implants the one or more dopants into the entire imaging area. The photodetectors are formed in the substrate layer by performing a series of implants of one or more dopants of a second conductivity type into each pixel in the substrate layer. Each photodetector implant is performed with a different energy than the other photodetector implants in the series.
    Type: Application
    Filed: November 9, 2010
    Publication date: June 30, 2011
    Inventors: Hung Q. Doan, Eric G. Stevens
  • Publication number: 20110126907
    Abstract: A solar cell includes; a semiconductor substrate, an n+ region disposed on a surface of the semiconductor substrate, a plurality of first electrodes connected to the n+ region, a p+ region disposed on the surface of the semiconductor substrate and separated from the n+ region, a second electrode connected to the p+ region, and a first dielectric layer which has a positive fixed charge and is disposed between adjacent first electrodes of the plurality of first electrodes, and a method of manufacturing the same.
    Type: Application
    Filed: June 21, 2010
    Publication date: June 2, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Wook LEE, Doo-Youl LEE, Hwa-Young KO
  • Publication number: 20110124148
    Abstract: Provided are methods of forming a nano structure and method of forming a solar cell using the same. The method of forming the nano structure includes: preparing a template; ionizing a surface of the template; forming an oxide layer enclosing the template on the surface of the template; and removing the template.
    Type: Application
    Filed: June 30, 2010
    Publication date: May 26, 2011
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Mi Hee JUNG, Hogyeong Yun, Mangu Kang, Sangee Kim, Hunkyun Pak
  • Publication number: 20110111550
    Abstract: A novel photovoltaic solar cell and method of making the same are disclosed. The solar cell includes: at least one absorber layer which could either be a lightly doped layer or an undoped layer, and at least a doped window-layers which comprise at least two sub-window-layers. The first sub-window-layer, which is next to the absorber-layer, is deposited to form desirable junction with the absorber-layer. The second sub-window-layer, which is next to the first sub-window-layer, but not in direct contact with the absorber-layer, is deposited in order to have transmission higher than the first-sub-window-layer.
    Type: Application
    Filed: December 14, 2010
    Publication date: May 12, 2011
    Inventors: Xunming Deng, Xianbo Liao, Wenhui Du
  • Patent number: 7915610
    Abstract: A ZnO-based thin film transistor (TFT) is provided herein, as is a method of manufacturing the TFT. The ZnO-based TFT has a channel layer that comprises ZnO and ZnCl, wherein the ZnCl has a higher bonding energy than ZnO with respect to plasma. The ZnCl is formed through the entire channel layer, and specifically is formed in a region near the surface of the channel layer. Since the ZnCl is strong enough not to be decomposed when exposed to plasma etching gas, an increase in the carrier concentration can be prevented. The distribution of ZnCl in the channel layer, may result from the inclusion of chlorine (Cl) in the plasma gas during the patterning of the channel layer.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: March 29, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myung-kwan Ryu, Jun-seong Kim, Sang-yoon Lee, Euk-che Hwang, Tae-sang Kim, Jang-yeon Kwon, Kyung-bae Park, Kyung-seok Son, Ji-sim Jung