Abstract: A method for producing a single crystal silicon solar cell including the steps of: implanting ions into a single crystal silicon substrate through an ion implanting surface thereof to form an ion implanted layer in the single crystal silicon substrate; forming a transparent electroconductive film on a surface of a transparent insulator substrate; conducting a surface activating treatment for the ion implanting surface of the single crystal silicon substrate and/or a surface of the transparent electroconductive film on the transparent insulator substrate; bonding the ion implanting surface of the single crystal silicon substrate and the surface of the transparent electroconductive film on the transparent insulator substrate to each other; applying an impact to the ion implanted layer; and forming a p-n junction in the single crystal silicon layer.

Abstract: A method for producing a single crystal silicon solar cell including the steps of: implanting ions into a single crystal silicon substrate through an ion implanting surface thereof; closely contacting the single crystal silicon substrate and a transparent insulator substrate with each other via a transparent electroconductive adhesive while using the ion implanting surface as a bonding surface; curing and maturing the transparent electroconductive adhesive into a transparent electroconductive film; applying an impact to the ion implanted layer to mechanically delaminate the single crystal silicon substrate to leave a single crystal silicon layer; and forming a p-n junction in the single crystal silicon layer.

Abstract: Provided is a method applicable to the production of silicon wafers having crystal orientation <100> or <110> and consisting in specifying wafer-supporting positions on the occasion of heat treatment in a vertical heat treatment furnace as well as a heat treatment jig for use in carrying out that method. It becomes possible to suppress the shear stress which contributes to the extension of the slip generated at each wafer-supporting element contact point as an initiation, suppress slip growth and thus markedly improve the yield of heat-treated silicon wafers. The heat-treated wafer obtained by using the supporting method and the heat treatment jig has few slip, in particular has no long and large slip, and is high in quality.

Abstract: A composite material is described. The composite material comprises semiconductor nanocrystals, and organic molecules that passivate the surfaces of the semiconductor nanocrystals. One or more properties of the organic molecules facilitate the transfer of charge between the semiconductor nanocrystals. A semiconductor material is described that comprises p-type semiconductor material including semiconductor nanocrystals. At least one property of the semiconductor material results in a mobility of electrons in the semiconductor material being greater than or equal to a mobility of holes. A semiconductor material is described that comprises n-type semiconductor material including semiconductor nanocrystals. At least one property of the semiconductor material results in a mobility of holes in the semiconductor material being greater than or equal to a mobility of electrons.

Abstract: This invention relates to compounds and compositions used to prepare semiconductor and optoelectronic materials and devices. This invention provides a range of compounds, compositions, materials and methods directed ultimately toward photovoltaic applications, as well as devices and systems for energy conversion, including solar cells. In particular, this invention relates to molecular precursor compounds, precursor materials and methods for preparing photovoltaic layers.

Abstract: An array substrate for a liquid crystal display device includes: a gate line and a first storage electrode on a substrate; a gate insulating layer on the gate line and the first storage electrode; a data line over the gate insulating layer, the data line crossing the gate line to define a pixel region; a passivation layer on the data line, wherein a first thickness of the passivation layer and the gate insulating layer over the first storage electrode is thinner than a second thickness of the passivation layer and the gate insulating layer over the gate line; and a pixel electrode and a second storage electrode on the passivation layer, the second storage electrode extended from the pixel electrode and overlapped with the first storage electrode.

Abstract: A fragile layer is formed in a region at a depth of less than 1000 nm from one surface of a single crystal semiconductor substrate, and a first impurity semiconductor layer and a first electrode are formed at the one surface side. After bonding the first electrode and a supporting substrate, the single crystal semiconductor substrate is separated using the fragile layer or the vicinity as a separation plane, thereby forming a first single crystal semiconductor layer over the supporting substrate. An amorphous semiconductor layer is formed on the first single crystal semiconductor layer, and a second single crystal semiconductor layer is formed by heat treatment for solid phase growth of the amorphous semiconductor layer. A second impurity semiconductor layer having a conductivity type opposite to that of the first impurity semiconductor layer and a second electrode are formed over the second single crystal semiconductor layer.

Abstract: A sensor array substrate, a display device including the sensor array substrate, and a method of manufacturing the sensor array substrate are provided. The sensor array substrate includes a substrate, a first sensor formed on a first pixel area of the substrate and configured to detect light, an overcoat layer formed on the first sensor, and a shield layer formed over the overcoat layer, wherein the shield layer overlaps the first sensor.

Abstract: A method for manufacturing a thin-film solar cell including the follow processes is provided. First, a substrate is provided. Then, a first conductive layer is formed on the substrate. Afterward, a first photovoltaic layer is formed on the first conductive layer. Then, the first photovoltaic layer is processed by a stabilized process, so as to reduce the light induced degradation as the first photovoltaic layer is illuminated. The material of the first photovoltaic layer is an amorphous semiconductor material. Later, a second photovoltaic layer is formed on the first photovoltaic layer. Then, a second conductive layer is formed on the second photovoltaic layer. A thin-film solar cell is also provided.

Abstract: In order to form a metal thin film, a silicide film, or the like between an upper-layer unit cell and a lower-layer unit cell in stacked-layer photoelectric conversion devices, a step of forming the thin film is additionally needed. Therefore, a problem such as decline in productivity of the photoelectric conversion devices occurs. A first unit cell including a single crystal semiconductor layer with a thickness of 10 ?m or less as a photoelectric conversion layer and a second unit cell including a non-single-crystal semiconductor layer as a photoelectric conversion layer, which is provided over the first unit cell, are at least included, and conductive clusters are dispersed between the unit cells. The conductive clusters are located between the lower-layer unit cell and the upper-layer unit cell to form an ohmic contact; thus, current flows between the both unit cells.

Abstract: A thin film solar cell including a first substrate, a first electrode on the first substrate, an upper surface of the first electrode having a plurality of irregularities, an absorption layer on the first electrode, the absorption layer including amorphous silicon layers and microcrystal silicon layers contacting the first electrode at an angle relative to the first substrate, a second electrode on the absorption layer, and a second substrate on the second electrode.

Abstract: Reduction in characteristic due to non-uniformity of crystallinity of a microcrystalline silicon film in a surface of a solar cell module is inhibited. A solar cell module is provided having an i-type layer of a microcrystalline silicon film as a photovoltaic layer in a photovoltaic unit (14), the i-type layer has a first region (30) and a second region (32) having a lower crystallization percentage than the first region (30) in the surface, and a tab electrode (22) to a terminal box (24) of the solar cell module (100) is formed overlapping the second region (32).

Abstract: The present invention discloses a thin film solar cell module and a manufacturing method thereof. The thin film solar cell comprises, from bottom to top, a first substrate, a first electrode, an absorber layer, and a second electrode layer. A first current output region formed at the positive electrode of the thin film solar cell module. A first current output element is disposed in the first current output region, and the absorber layer further comprises at least a first gap which is disposed in the first current output region to increase the contact between the first electrode layer and the second electrode layer. The useless current, the resistance and the heat generated there are reduced. The heat generated there is also reduced.

Abstract: A semiconductor structure includes a semiconductor mesa located upon an isolating substrate. The semiconductor mesa includes a first end that includes a first doped region separated from a second end that includes a second doped region by an isolating region interposed therebetween. The first doped region and the second doped region are of different polarity. The semiconductor structure also includes a channel stop dielectric layer located upon a horizontal surface of the semiconductor mesa over the second doped region. The semiconductor structure also includes a first device located using a sidewall and a top surface of the first end as a channel region, and a second device located using the sidewall and not the top surface of the second end as a channel. A related method derives from the foregoing semiconductor structure. Also included is a semiconductor circuit that includes the semiconductor structure.

Abstract: This invention relates to methods for making materials using compounds, polymeric compounds, and compositions used to prepare semiconductor and optoelectronic materials and devices including thin film and band gap materials. This invention provides a range of compounds, polymeric compounds, compositions, materials and methods directed ultimately toward photovoltaic applications, transparent conductive materials, as well as devices and systems for energy conversion, including solar cells. This invention further relates to methods for making CA(I,G,A)S, CAIGAS, A(I,G,A)S, AIGAS, C(I,G,A)S, and CIGAS materials by providing one or more polymeric precursor compounds or inks thereof, providing a substrate, depositing the compounds or inks onto the substrate; and heating the substrate at a temperature of from about 20° C. to about 650° C.

Abstract: This invention relates to methods for making materials using a range of compounds, polymeric compounds, and compositions used to prepare semiconductor and optoelectronic materials and devices including thin film and band gap materials for photovoltaic applications including devices and systems for energy conversion and solar cells. In particular, this invention relates to polymeric precursor compounds and precursor materials for preparing photovoltaic layers. This invention further relates to methods for making a CIGS, CIS or CGS material by providing one or more polymeric precursor compounds or inks thereof, providing a substrate, depositing the compounds or inks onto the substrate; and heating the substrate at a temperature of from about 20° C. to about 650° C.

Abstract: This invention relates to methods for making materials using compounds, polymeric compounds, and compositions used to prepare semiconductor and optoelectronic materials and devices including thin film and band gap materials. This invention provides a range of compounds, polymeric compounds, compositions, materials and methods directed ultimately toward photovoltaic applications, transparent conductive materials, as well as devices and systems for energy conversion, including solar cells. This invention further relates to methods for making AIGS, AIS or AGS materials by providing one or more polymeric precursor compounds or inks thereof, providing a substrate, depositing the compounds or inks onto the substrate; and heating the substrate at a temperature of from about 20° C. to about 650° C.

Abstract: A microelectronic assembly in which a semiconductor device structure is directionally positioned on an off-axis substrate (201). In an illustrative implementation, a laser diode is oriented on a GaN substrate (201) wherein the GaN substrate includes a GaN (0001) surface off-cut from the <0001> direction predominantly towards either the <1120> or the <1100> family of directions. For a <1120> off-cut substrate, a laser diode cavity (207) may be oriented along the <1100> direction parallel to lattice surface steps (202) of the substrate (201) in order to have a cleaved laser facet that is orthogonal to the surface lattice steps. For <1100> off-cut substrate, the laser diode cavity may be oriented along the <1100> direction orthogonal to lattice surface steps (207) of the substrate (201) in order to provide a cleave laser facet that is aligned with the surface lattice steps.

Abstract: A method of forming an optical sensor includes the following steps. A substrate is provided, and a read-out device is formed on the substrate. a first electrode electrically connected to the read-out device is formed on the substrate. a photosensitive silicon-rich dielectric layer is formed on the first electrode, wherein the photosensitive silicon-rich dielectric layer comprises a plurality of nanocrystalline silicon crystals. A second electrode is formed on the photosensitive silicon-rich dielectric layer.

Abstract: A solar cell and a method for producing a solar cell are described, comprising at least one photovoltaic layer region (1) which at least partially absorbs photons (6) incident therein, whose photon energy is greater than a minimum photon energy Emin, and releases electrical charge carriers in the form of electron-hole pairs, which are spatially separable within the photovoltaic layer region (1) and can be tapped via at least two electrodes (2), which are electrically connected to the photovoltaic layer region (1), to implement an electrical voltage, and comprising at least one interaction layer (3 and/or 4), which at least partially overlaps the photovoltaic layer region, in which at least a part of the incident photons (6) are subject to an interaction with emission of photons of higher or lower photon energy than that of the incident photons.

Abstract: One embodiment of the present invention provides a double-sided heterojunction solar cell module. The solar cell includes a frontside glass cover, a backside glass cover situated below the frontside glass cover, and a number of solar cells situated between the frontside glass cover and the backside glass cover. Each solar cell includes a semiconductor multilayer structure situated below the frontside glass cover, including: a frontside electrode grid, a first layer of heavily doped amorphous Si (a-Si) situated below the frontside electrode, a layer of lightly doped crystalline-Si (c-Si) situated below the first layer of heavily doped a-Si, and a layer of heavily doped c-Si situated below the lightly doped c-Si layer. The solar cell also includes a second layer of heavily doped a-Si situated below the multilayer structure; and a backside electrode situated below the second layer of heavily doped a-Si.

Abstract: A photovoltaic device is provided comprising a layer. The layer comprises a plurality of grains separated by grain boundaries wherein the grains are either p-type or n-type. The grain boundaries comprise an active dopant. The active dopant concentration in the grain boundaries is higher than the effective dopant concentration in the grains. The grains and grain boundaries may be of the same type or of the opposite type. Further, when the grain boundaries are n-type the bottom of the grain boundaries may be p-type. A method of making the layer is also disclosed.

Abstract: A semiconductor process and apparatus provide a dual or hybrid substrate by forming a second semiconductor layer (214) that is isolated from, and crystallographically rotated with respect to, an underlying first semiconductor layer (212) by a buried insulator layer (213); forming an STI region (218) in the second semiconductor layer (214) and buried insulator layer (213); exposing the first semiconductor layer (212) in a first area (219) of a STI region (218); epitaxially growing a first epitaxial semiconductor layer (220) from the exposed first semiconductor layer (212); and selectively etching the first epitaxial semiconductor layer (220) and the second semiconductor layer (214) to form CMOS FinFET channel regions (e.g., 223) and planar channel regions (e.g., 224) from the first epitaxial semiconductor layer (220) and the second semiconductor layer (214).

Abstract: In some embodiments, a method of forming a photovoltaic cell includes (1) forming a cleave plane in a donor body so as to define a lamina to be bonded to a receiver element and exfoliated from the donor body; (2) prior to bonding, pre-heating the donor body without the receiver element to a temperature of greater than about 200° C. for a first time period that is less than a time period required for exfoliation of the lamina from the donor body; (3) cooling the donor body after pre-heating the donor body; (4) bonding the donor body to the receiver element; and (5) heating the bonded donor body and receiver element for a second time period so as to complete the exfoliation of the lamina from the donor body. Numerous other aspects are provided.

Abstract: A method for growing III-V nitride films having an N-face or M-plane using an ammonothermal growth technique. The method comprises using an autoclave, heating the autoclave, and introducing ammonia into the autoclave to produce smooth N-face or M-plane Gallium Nitride films and bulk GaN.

Abstract: A thin film transistor (TFT) array substrate for an X-ray detector and a method of fabricating the same are provided. The TFT array substrate includes a substrate, a gate line formed on the substrate, a data line crossing the gate line, a thin film transistor including a gate electrode, a source electrode, and a drain electrode, a first electrode connected to the drain electrode, a passivation layer formed over the gate line, the data line, the thin film transistor and the first electrode, a photoconductor formed over the passivation layer and connected to the first electrode, and a second electrode formed on the photoconductor.

Abstract: The present invention provides a method and apparatus for edge film stack removal process for fabricating photovoltaic devices. In one embodiment, a method for manufacturing solar cell devices on a substrate includes providing a substrate into a chemical vapor deposition chamber, contacting a shadow frame disposed in the deposition chamber to a periphery region of the substrate, depositing a silicon-containing layer on the substrate through an aperture defined by the shadow frame, transferring the substrate to a physical vapor deposition chamber, depositing a transparent conductive layer on the silicon-containing layer, transferring the substrate to a laser edge removal tool, and laser scribing the layers formed on the periphery region of the substrate.

Abstract: The oxidation of a lower electrode by the reaction between a metal element in the lower electrode and oxygen in a bonding layer is suppressed. The contamination of a semiconductor layer that is a photoelectric conversion layer by the diffusion of the metal element in the lower electrode into the semiconductor layer is suppressed.

Abstract: A back contact integrated photovoltaic cell includes a substrate having a dielectric surface and a patterned metal layer with parallel spaced alternately positive and negative electrode fingers forming an interdigitated two-terminal structure over the dielectric surface of the substrate. A dielectric filler may be in the interstices of separation between adjacent spaced parts of the patterned metal layer. Parallel spaced strips, alternately of p+ doped polysilicon and of n+ doped polysilicon, may top the positive and negative interdigitated electrode fingers, respectively, and form doped p-type active regions and n-type active regions of the integrated photovoltaic cell, spaced and isolated by a strip of undoped or negligibly doped polysilicon. An n? or p? doped or intrinsic semiconducting layer of at least partly crystallized silicon, forming a semiconductor region of thickness adapted to maximize absorption of photonic energy when illuminated by sunlight, may cover the interdigitated active doped regions.

Abstract: A plurality of pixel portions (12) are formed on a silicon substrate (11). A photoelectric converter portion (10) constituting each of the pixel portions (12) is electrically isolated by an element isolation portion (13) comprising an insulating film formed on the silicon substrate (11). The photoelectric converter portion (10) partitioned by the element isolation portion (13) is so formed that a crystal orientation of the sides in contact with the element isolation portion (13) corresponds to a <00-1> direction. This makes it possible to reduce dark current caused by stress in the vicinity of the interface of the element isolation portion (13) and maintain high sensitivity even if the pixel portions (12) are made smaller in size.

Abstract: A fabricating method of a TFT includes first forming a source on a substrate. Then, a first insulation pattern layer is formed to cover parts of the source and the substrate. The first insulation pattern layer has an opening exposing a part of the source. Thereafter, a gate pattern layer is formed on the first insulation pattern layer. Then, the gate pattern layer and a second insulation pattern layer formed thereon surround the opening. Moreover, a second lateral protection wall is formed on an edge of the gate pattern layer in the opening. Afterwards, a channel layer is formed in the opening and covers the second lateral protection wall and the source. Then, a passivation layer with a contact window is formed on the channel layer and the second insulation pattern layer to expose a portion of the channel layer. Thereafter, a drain is formed on the exposed channel layer.

Abstract: A structural element having a region of porous silicon or porous silicon oxide, which was obtained from a porization, starting from an edge area of the region, in at least largely crystalline silicon. Relative to the edge area, the crystalline silicon has a crystal orientation that has an orientation that differs from a <100> orientation or from an orientation that is equivalent for reasons of symmetry. This structural element is suited for use in a mass-flow sensor, in a component for the thermal decoupling of sensor and/or actuator structures, or a gas sensor. Furthermore, methods for setting the thermal conductivity of a region of porous silicon or porous silicon oxide of a structural element are described.

Abstract: An optical switching system comprising an embodiment with a high pass filter operable to eliminate a portion of frequencies present in an image and an optical device operative to receive the spectrally modified image from the high pass filter, alternatively amplify the spectrally modified image, and propagate at least those frequency components in the spectrally modified image exhibiting a frequency less than an absorption frequency of the optical switching device when the optical switching device is active. Alternatively, the optical switching system may transmit an image only when the system is active. The optical switching system may, for example, comprise superluminescent light emitting diodes which may be, for example, formed in the shape of an inverted truncated prism. For human viewing purposes, the operative transmission ranges may closely coincide with the maximum sensitivity of the photopic response of the corresponding red, blue and green cones in human eyes.

Abstract: A solar cell includes an electron conductor, a plurality of quantum dots on a surface of the electron conductor forming a quantum dot layer, and a supplemental light-absorbing material in one or more gaps in the quantum dot layer. The supplemental light-absorbing material is capable of absorbing light that passes through the one or more gaps in the quantum dot layer and converting the absorbed light into holes and electrons. The supplemental light-absorbing material may also inhibit a hole conductor from coming into contact with the electron conductor. The supplemental light-absorbing material could include one or more polymers, semiconductors, fluorophores, metal particles, nanowires, nanotubes, and nanoparticles.

Abstract: A heating process is performed in a nitrogen atmosphere at a temperature of not less than 1650° C. upon an epitaxial substrate including a single crystal base and an upper layer made of a group-III nitride crystal and epitaxially formed on a main surface of the single crystal base. The result shows that the heating process reduces the number of pits in a top surface to produce the effect of improving the surface flatness of the group-III nitride crystal. The result also shows that the dislocation density in the group-III nitride crystal is reduced to not more than one-half the dislocation density obtained before the heat treatment.

Abstract: Provided are a thin film transistor and method of fabricating the same, in which an amorphous silicon layer is formed on a substrate, a capping layer containing a metal catalyst having a different concentration according to its thickness is formed on the amorphous silicon layer, the capping layer is patterned to form a capping layer pattern, and the amorphous silicon layer is crystallized, such that the density and position of seeds formed at an interface between the amorphous silicon layer and the capping layer pattern is controlled, thereby improving the size and uniformity of grains, and in which polycrystalline silicon of desired size and uniformity is selectively formed at a desired position by one crystallization process, resulting in a thin film transistor having excellent and desired properties.

Abstract: Because a restricting plate 27 is disposed using a spacer 25, an upper plate 15 is allowed to expand upward when resin is injected, but unnecessary overexpansion is restricted by the restricting plate 27. Therefore the injection of a slightly larger amount of resin 37 does not cause a distortion or breakage of the upper plate 15 and a large amount resin 37 than the predetermined amount may be injected. As a result, damage to the upper plate 15 by the injection of the resin 37 and damage to the upper plate 15, the exfoliation of the radiation sensitive layer, and the like caused by the curing of the resin 37 may be prevented and damage to the flat panel radiation detector 1 may be prevented thereby.

Abstract: A semiconductor structure includes a semiconductor mesa located upon an isolating substrate. The semiconductor mesa includes a first end that includes a first doped region separated from a second end that includes a second doped region by an isolating region interposed therebetween. The first doped region and the second doped region are of different polarity. The semiconductor structure also includes a channel stop dielectric layer located upon a horizontal surface of the semiconductor mesa over the second doped region. The semiconductor structure also includes a first device located using a sidewall and a top surface of the first end as a channel region, and a second device located using the sidewall and not the top surface of the second end as a channel. A related method derives from the foregoing semiconductor structure. Also included is a semiconductor circuit that includes the semiconductor structure.

Abstract: A TFT array substrate is disclosed. In the pixel structure of the TFT array substrate, patterned transparent conductive layers are disposed under a first metal layer (M1) and a second metal layer (M2) and most areas of the M1 and M2 are substituted by the patterned transparent conductive layers. So, the pixel structure has high aperture ratio and large storage capacitance. Besides, a scan bonding pad on the TFT array substrate includes a first patterned transparent conductive layer (T1), the M1 and a third patterned transparent conductive layer (T3). The M1 is disposed on the T1, and the T3 is electrically connected to the T1 via a contact hole in the M1. So, the contact resistance of the scan bonding pad is small. The data bonding pad on the TFT array substrate has similar design. Moreover, fabricating methods of TFT array substrates are also provided.

Abstract: In accordance with the invention, a photonic device comprises a semiconductor substrate including at least one circuit component comprising a metal silicide layer and an overlying layer including at least one photoresponsive component. The metal silicide layer is disposed between the circuit component and the photoresponsive component to prevent entry into the circuit component of light that penetrates the photoresponsive component. The silicide layer advantageously reflects the light back into the photoresponsive element. In addition, the overlying layer can include one or more reflective layers to reduce entry of oblique light into the photoresponsive component. In an advantageous embodiment, the substrate comprises single-crystal silicon including one or more insulated gate field effect transistors (IGFETs), and/or capacitors, and the photoresponsive element comprises germanium and/or germanium alloy epitaxially grown from seeds on the silicon.

Abstract: In a semiconductor device having SiC vertical trench MOSFETs, it is aimed to prevent the generation of large scattering in the channel resistance without largely increasing the average value of channel resistance. A 4H-SiC substrate having a major face thereof that is generally a {0001} face and having an off angle ?. The trench is formed with the standard deviation ? in scattering of the angle formed by a trench side wall face and a substrate major face within a wafer face. By setting the designed value of the angle formed by the trench side wall face and the substrate major face at an any angle ranging from [(60 degrees)+2?] to [(90 degrees)?tan?1 (0.87×tan ?)?2?] in forming the trench in the SiC substrate, a semiconductor device in which the angle formed by the trench side wall face and the substrate major face is 60 degrees or more but not more than [(90 degrees)?tan?1 (0.87×tan ?)] can be obtained.

Abstract: A process is provided for etching a silicon-containing substrate to form nanowire arrays. In this process, one deposits nanoparticles and a metal film onto the substrate in such a way that the metal is present and touches silicon where etching is desired and is blocked from touching silicon or not present elsewhere. One submerges the metallized substrate into an etchant aqueous solution comprising HF and an oxidizing agent. In this way arrays of nanowires with controlled diameter and length are produced.

Abstract: A photoelectric conversion device includes a first unit cell in which one face of a single crystal semiconductor layer is provided with a first electrode and a first impurity semiconductor layer including one conductivity type and an opposite face is provided with a second impurity semiconductor layer including a conductivity type opposite to the one conductivity type, and a second unit cell including a p-type organic semiconductor and an n-type organic semiconductor. The first unit cell and the second unit cell are connected in series with an intermediate layer interposed therebetween. The intermediate layer includes a transition metal oxide. A face of the first electrode which is opposite to the single crystal semiconductor layer is provided with an insulating layer, and the insulating layer is bonded to a supporting substrate.

Abstract: The present invention provides a method of manufacturing a TFT substrate, in which method a data signal line is separated into upper and lower regions at a separating point(Q) that is not around above a scan signal line but in a region where an i-layer and an n+ layer formed on a gate insulating film are removed away in a flattened region of a gate insulating film.

Abstract: A fragile layer is formed in a region at a depth of less than 1000 nm from one surface of a single crystal semiconductor substrate, and a first impurity semiconductor layer and a first electrode are formed at the one surface side. After bonding the first electrode and a supporting substrate, the single crystal semiconductor substrate is separated using the fragile layer or the vicinity as a separation plane, thereby forming a first single crystal semiconductor layer over the supporting substrate. An amorphous semiconductor layer is formed on the first single crystal semiconductor layer, and a second single crystal semiconductor layer is formed by heat treatment for solid phase growth of the amorphous semiconductor layer. A second impurity semiconductor layer having a conductivity type opposite to that of the first impurity semiconductor layer and a second electrode are formed over the second single crystal semiconductor layer.

Abstract: A method for manufacturing a photoelectric conversion device typified by a solar cell, having an excellent photoelectric conversion characteristic with a silicon semiconductor material effectively utilized. The point is that the surface of a single crystal semiconductor layer bonded to a supporting substrate is irradiated with a pulsed laser beam to become rough. The single crystal semiconductor layer is irradiated with the pulsed laser beam in an atmosphere containing an inert gas and oxygen so that the surface thereof is made rough. With the roughness of surface of the single crystal semiconductor layer, light reflection is suppressed so that incident light can be trapped. Accordingly, even when the thickness of the single crystal semiconductor layer is equal to or greater than 0.1 ?m and equal to or less than 10 ?m, path length of incident light is substantially increased so that the amount of light absorption can be increased.

Abstract: A photoelectric conversion device which is excellent in photoelectric conversion characteristics is provided by effectively utilizing silicon semiconductor materials. The present invention relates to a method for manufacturing a photoelectric conversion device using a solar cell, in which a plurality of single crystal semiconductor substrates in each of which a damaged layer is formed at a predetermined depth is arranged over a supporting substrate having an insulating surface; a surface layer part of the single crystal semiconductor substrate is separated thinly using the damaged layer as a boundary so as to form a single crystal semiconductor layer over one surface of the supporting substrate; and the single crystal semiconductor layer is irradiated with a laser beam from a surface side which is exposed by separation of the single crystal semiconductor layer to planarize the surface of the single crystal semiconductor layer.

Abstract: Disclosed are detector devices and related methods. In an AlN EUV detector a low temperature AlN layer is deposed above an AlN buffer layer. In one embodiment, the low temperature AlN layer is deposed at about 800° C. Pulsed NH3 is used when growing an AlN epilayer above the low temperature layer. Numerous embodiments are disclosed.

Abstract: A zinc-blende nitride semiconductor free-standing substrate has a front surface and a back surface opposite the front surface. The distance between the front and back surfaces is not less than 200 ?m. The area ratio of the zinc-blende nitride semiconductor to the front surface is not less than 95%.

Abstract: A semiconductor device comprising a first transistor device and second transistor device both on a semiconductor substrate. The first transistor device has a first n-channel and a first p-channel and the second transistor device has a second n-channel and a second p-channel. Each of the p-channels and the n-channels have a long lateral axis that is aligned with a orientation plane of a silicon layer of the semiconductor substrate. The second p-channel and the first and second n-channels include the silicon layer configured as strained silicon. The first p-channel includes the silicon layer configured as relaxed silicon. Each of the n-channels contact gate structures that impart a tensile stress in the n-channels.