Abstract: A method and system provide a magnetic junction usable in a magnetic device. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, a free layer, at least one insulating layer, and at least one magnetic insertion layer adjoining the at least one insulating layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The at least one insulating layer is adjacent to at least one of the free layer and the pinned layer. The at least one magnetic insertion layer adjoins the at least one insulating layer. In some aspects, the insulating layer(s) include at least one of magnesium oxide, aluminum oxide, tantalum oxide, ruthenium oxide, titanium oxide, and nickel oxide The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.

Abstract: A method for fabricating a semiconductor device includes forming a bottom-electrode metal layer over a substrate, planarizing the bottom-electrode metal layer by a first thickness through a chemical mechanical polishing (CMP) process, etching the bottom-electrode metal layer by a second thickness through a wet etching process, forming a plurality of layers of a magnetic tunneling junction (MTJ) element over the bottom-electrode metal layer, forming a top electrode over the plurality of layers, and forming the MTJ element and a bottom electrode by etching the plurality of layers and the bottom-electrode metal layer using the top electrode as an etch mask.

Abstract: A Hall sensor has a P-type semiconductor substrate and a Hall sensing portion having a square shape and an N-type conductivity disposed on a surface of the semiconductor substrate. The Hall sensor includes Hall voltage output terminals having the same shape with each other, and control current input terminals having the same shape with each other. The Hall voltage output terminals are disposed at respective ones of four vertices of the Hall sensing portion. The control current input terminals include pairs of control current input terminals disposed at respective ones of the four vertices of the Hall sensing portion and arranged on both sides of respective ones of the Hall voltage output terminals in spaced apart relation from the Hall voltage output terminals so as to prevent electrical connection between the control current input terminals and the Hall voltage output terminals.

Abstract: A method of manufacturing a magnetic device includes forming a stack structure, the stack structure including a magnetic layer, and etching the stack structure by using an etching gas, the etching gas including at least 80% by volume of H2 gas.

Abstract: A memory device may comprise a magnetic tunnel junction (MTJ) stack, a bottom electrode (BE) layer, and a contact layer. The MTJ stack may include a free layer, a barrier, and a pinned layer. The BE layer may be coupled to the MTJ stack, and encapsulated in a planarized layer. The BE layer may also have a substantial common axis with the MTJ stack. The contact layer may be embedded in the BE layer, and form an interface between the BE layer and the MTJ stack.

Abstract: An apparatus may include a back-bias magnet; and a semiconductor chip element; wherein the semiconductor chip element has a sensor for measuring a magnetic field strength; and wherein a contact surface is formed on a contact side of the back-bias magnet and on a contact side of the semiconductor chip element and wherein the contact side of the semiconductor chip element has one or more structures such that the contact surface of the back-bias magnet is shaped in a manner corresponding to the structures of the semiconductor chip element.

Abstract: According to one embodiment, a method for patterning a medium having a patterned hard mask applied thereon is disclosed herein. The patterned hard mark includes a plurality of apertures exposing portions of the medium. The method includes directing ions toward the medium, implanting a portion of the ions into the exposed portions of the medium, removing a layer of the patterned hard mask with another portion of the ions, and depositing hard mask material onto the patterned hard mask. Depositing hard mask material onto the exposed portions of the medium may follow implantation of the portion of the ions into the exposed portions of the medium.

Abstract: A method for fabricating a semiconductor device includes: forming an MTJ element and an electrode layer pattern over a substrate; forming a protective layer to protect the MTJ element and the electrode layer pattern; forming at least one insulation layer over the protective layer; forming a first hole by selectively removing the at least one insulation layer; forming an overhang pattern protruding from the sidewall of the first hole; forming a second hole exposing the electrode layer pattern by selectively removing the at least one insulation layer exposed at the bottom of the first hole by using the overhang pattern as a mask; and forming a conductive layer pattern to be electrically coupled to the electrode layer pattern exposed through the second hole.

Abstract: Methods are provided for enhancing properties, including polarization, of thin-film ferroelectric materials in electronic devices. According to one embodiment, a process for enhancing properties of ferroelectric material in a device having completed wafer processing includes applying mechanical stress to the device, independently controlling the temperature of the device to cycle the temperature from room temperature to at or near the Curie temperature of the ferroelectric material and back to room temperature while the device is applied with the mechanical stress, and then removing the mechanical stress. Certain of the subject methods can be performed as part of a back end of line (BEOL) process, and may be performed during the testing phase at wafer or die level.

Abstract: Perpendicular magnetic anisotropy (PMA) type magnetic random access memory cells are constructed with a composite PMA layer to provide a magnetic tunnel junction (MTJ) with an acceptable thermal barrier, A PMA coupling layer is deposited between a first PMA layer and a second PMA layer to form the composite PMA layer. The composite PMA layer may be incorporated in PMA type MRAM cells or in-plane type MRAM cells.

Abstract: A method for manufacturing a semiconductor device includes forming plural layers of a MTJ device, depositing a conductive layer over the plural layers, forming a hard mask pattern used for patterning the plural layers over the conductive layer, where the conductive layer is exposed through the hard mask pattern, performing hydrogen peroxide process to volatilize the exposed conductive layer and removing the volatilized conductive layer, and patterning the plural layers by using the hard mask pattern as an etch mask to form the MTJ device.

Abstract: A method for manufacturing a semiconductor device includes forming a mask film on a partial region of a semiconductor substrate; forming a mask member above the semiconductor substrate in both the region where the mask film is formed and a region where the mask film is not formed; patterning the mask film and an upper portion of the semiconductor substrate by performing etching using the mask member as a mask. The method further includes removing part of the patterned upper portion of the semiconductor substrate by performing etching using the patterned mask film as a mask.

Abstract: A fluxgate magnetometer is formed in a semiconductor wafer fabrication sequence, which significantly reduces the size and cost of the fluxgate magnetometer. The semiconductor wafer fabrication sequence attaches a die, which has drive and sense circuits, to the bottom surface of a cavity formed in a larger structure, and forms drive and sense coils around a magnetic core structure on the top surface of the larger structure.

Abstract: There is provided a magnetic memory with using a magnetoresistive effect element of a spin-injection magnetization reversal type, in which a multi-value operation is possible and whose manufacturing and operation are simple. A preferred aim of this is solved by providing two or more magnetoresistive effect elements which are electrically connected in series to each other and by selecting one of the series-connected elements depending on a direction of a current carried in the series-connected elements, a magnitude thereof, and an order of the current thereof for performing the writing operation. For example, it is solved by differentiating plane area sizes of the respective magnetoresistive effect elements which have the same film structure from each other so as to differentiate resistance change amounts caused by respective magnetization reversal and threshold current values required for respective magnetization reversal from each other.

Abstract: A method for fabricating a semiconductor device includes forming a magnetic tunnel junction (MTJ) element on a substrate, forming a first capping layer along the shape of the MTJ element, forming an insulating layer on the first capping layer, forming a trench exposing a portion of the first capping layer above the MTJ element by selectively etching the insulating layer, forming a second capping layer on sidewalls of the trench, removing the exposed portion of the first capping layer using the second capping layer as an etching mask to expose an upper surface of the MTJ element, and forming a conductive layer in the trench, wherein the conductive layer contacts the upper surface of the MTJ element.

Abstract: A semiconductor device includes a pinned layer having a magnetic direction permanently set to a first direction, a tunnel insulating layer arranged on the pinned layer, a free layer arranged on the tunnel insulating layer and having a changeable magnetic direction, and a magnetic induction layer formed to surround the pinned layer and have a magnetic direction permanently set to a second direction different from the first direction.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of layers which are stacked as a bottom layer, an MTJ layer, and a top layer, patterning the top layer and the MTJ layer using an etch mask pattern to form a top layer pattern and an MTJ pattern, forming a carbon spacer on the sidewalls of the MTJ pattern and the top layer pattern to protect the MTJ pattern and the top layer pattern, and patterning the bottom layer using the carbon spacer and the etch mask pattern as an etch mask to form a bottom layer pattern.

Abstract: BEOL memory cells are described that include one or more sidewall protection layers on the memory device (including, for example, an MTJ element) deposited prior to interconnect via etching to prevent the formation of electrical shorts between layers. One embodiment uses a single layer sidewall protection sleeve that is deposited after the memory device has been patterned. The layer material is vertically etched down to expose the upper surface of the top electrode while leaving a residual layer of protective material surrounding the rest of the memory device. The material for the protection layer is selected to resist the etchant used to remove the first dielectric material from the via in the subsequent interconnect process. A second embodiment uses dual-layer sidewall protection in which the first layer covers the memory element is preferably an oxygen-free dielectric and the second layer protects the first layer during via etching.

Abstract: A vertical magnetic memory device includes a pinned layer including a plurality of first ferromagnetic layers that are alternately stacked with at least one first spacer, wherein the pinned layer is configured to have a vertical magnetization, a free layer including a plurality of second ferromagnetic layers that are alternately stacked with at least one second spacer, and a tunnel barrier coupled between the pinned layer and the free layer.

Abstract: According to an embodiment, a magnetoresistive random access memory (MRAM) device comprises a bottom electrode, a stack, a dielectric material, a dielectric layer, and a conductive material. The bottom electrode is over a substrate, and the stack is over the bottom electrode. The stack comprises a magnetic tunnel junction (MTJ) and a top electrode. The dielectric material is along a sidewall of the stack, and the dielectric material has a height greater than a thickness of the MTJ and less than a stack height. The dielectric layer is over the stack and the dielectric material. The conductive material extends through the dielectric layer to the top electrode of the stack.

Abstract: A magnetic tunnel junction device includes a first electrode having a curved top surface, a magnetic tunnel junction layer formed along the top surface of the first electrode, and a second electrode formed on the magnetic tunnel junction layer.

Abstract: A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed therethrough and are formed on top of the access transistor. An magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ.

Abstract: The cost and size of an atomic magnetometer are reduced by attaching together a first die which integrates together a vapor cell, top and side photo detectors, and processing electronics, a second die which integrates together an optics package and a heater for the vapor cell, and a third die which integrates together a VCSEL, a heater for the VCSEL, and control electronics.

Abstract: Provided are a magnetic memory device and a method of forming the same. The method may include forming a pinning pattern on a substrate; forming a first interlayer insulating layer that exposes the pinning pattern on the substrate; forming a pinned layer, a tunneling barrier layer and a second magnetic conductive layer on the pinning pattern; and forming a pinned pattern, a tunnel barrier pattern and a second magnetic conductive pattern by performing a patterning process on the pinned layer, the tunnel barrier layer and the second magnetic conductive layer.

Abstract: In accordance with an embodiment, a magnetoresistive element includes a lower electrode, a first magnetic layer on the lower electrode, a first interfacial magnetic layer on the first magnetic layer, a nonmagnetic layer on the first interfacial magnetic layer, a second interfacial magnetic layer on the nonmagnetic layer, a second magnetic layer on the second interfacial magnetic layer; and an upper electrode layer on the second magnetic layer. Either the first magnetic and interfacial magnetic layers or the second magnetic and interfacial magnetic layers constitute a storage layer. The other layers of the first magnetic and interfacial magnetic layers and the second magnetic and interfacial magnetic layers constitute a reference layer. The lower electrode includes an alloy layer or mixture layer of a precious metal and a transition element or a rare earth element, or comprises a conductive oxide layer.

Abstract: A method for forming a memory device includes forming a cavity having an inner surface with an undulating profile in a substrate, depositing a ferromagnetic material in the cavity, forming a reading element on the substrate proximate to a portion of the ferromagnetic material, and forming a writing element on the substrate proximate to a second portion of the ferromagnetic material.

Abstract: In accordance with an embodiment, a magnetoresistive element includes a lower electrode, a first magnetic layer on the lower electrode, a first diffusion prevention layer on the first magnetic layer, a first interfacial magnetic layer on the first metal layer, a nonmagnetic layer on the first interfacial magnetic layer, a second interfacial magnetic layer on the nonmagnetic layer, a second diffusion prevention layer on the second interfacial magnetic layer, a second magnetic layer on the second diffusion prevention layer, and an upper electrode layer on the second magnetic layer. The ratio of a crystal-oriented part to the other part in the second interfacial magnetic layer is higher than the ratio of a crystal-oriented part to the other part in the first interfacial magnetic layer.

Abstract: A magnetic tunnel junction (MTJ) for a magnetic random access memory (MRAM) includes a magnetic free layer having a variable magnetization direction; an iron (Fe) dusting layer formed on the free layer; an insulating tunnel barrier formed on the dusting layer; and a magnetic fixed layer having an invariable magnetization direction, disposed adjacent the tunnel barrier such that the tunnel barrier is located between the free layer and the fixed layer; wherein the free layer and the fixed layer have perpendicular magnetic anisotropy and are magnetically coupled through the tunnel barrier.

Abstract: A method and system provide a magnetic junction. A free layer, a symmetry filter, and a pinned layer are provided. The free layer has a magnetic moment switchable between stable states when a write current is passed through the magnetic junction. The symmetry filter transmits charge carriers having a first symmetry with higher probability than charge carriers having another symmetry. The symmetry filter resides between the free layer and the pinned layer. The free layer and/or the pinned layer lies in a plane, has the charge carriers of the first symmetry in a spin channel at a Fermi level, lacks the charge carriers of the first symmetry at the Fermi level in another spin channel, and has a nonzero magnetic moment component perpendicular to the plane. The free layer and/or the pinned layer and the symmetry filter has at least one lattice mismatch of less than seven percent.

Abstract: An integrated circuit includes a magnetic field sensor and an injection molded magnetic material enclosing at least a portion of the magnetic field sensor.

Abstract: A method and system provide a magnetic junction usable in a magnetic device. The magnetic junction includes a first pinned layer having a first pinned layer magnetization, a first nonmagnetic spacer layer, and a free layer having an easy axis. The first nonmagnetic spacer layer is between the first pinned layer and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction and such that the free layer employs precessional switching.

Abstract: In a method of forming a magnetic pattern, a lower electrode layer is formed on a substrate. An insulating interlayer is formed on the lower electrode layer. The insulating interlayer is partially removed to form an opening. A first pinned layer pattern filling the opening is formed. A second pinned layer, a tunnel barrier layer, a free layer and an upper electrode layer are formed on the insulating interlayer and the first pinned layer pattern. The upper electrode layer, the free layer, the tunnel barrier layer and the second pinned layer are patterned to form a second pinned layer pattern, a tunnel barrier pattern, a free layer pattern and an upper electrode. The second pinned layer pattern covers an upper surface of the first pinned layer pattern.

Abstract: A method of forming a vinylidene fluoride (VDF) oligomer or co-oligomer film on a substrate is disclosed. The method comprises forming a VDF oligomer or co-oligomer precursor solution; depositing the VDF oligomer or co-oligomer precursor solution onto the substrate to form a preliminary VDF oligomer or co-oligomer film on the substrate; and applying uniaxial pressure on the preliminary VDF oligomer or co-oligomer film and the substrate at an elevated temperature to form the VDF oligomer or co-oligomer film on the substrate. The substrate may comprise a metal surface which may be used as a bottom electrode and a top electrode may be deposited on the VDF oligomer or co- oligomer film The VDF oligomer or co-oligomer film, the bottom electrode on the substrate and the top electrode on the VDF oligomer or co-oligomer film form an electrical device.

Abstract: A method of manufacturing a magnetic memory cell, including a magnetic tunnel junction (MTJ), includes using silicon nitride layer and silicon oxide layer to form a trench for depositing copper to be employed for connecting the MTJ to other circuitry without the use of a via.

Abstract: An apparatus includes a substrate with a planar surface, a multilayer of semiconductor layers located on the planar surface, a plurality of electrodes located over the multilayer, and a dielectric layer located between the electrodes and the multilayer. The multilayer includes a 2D quantum well. A first set of the electrodes is located to substantially surround a lateral area of the 2D quantum well. A second set of the electrodes is controllable to vary a lateral width of a non-depleted channel between the substantially surrounded lateral area of the 2D quantum well and another area of the 2D quantum well. A third set of the electrodes is controllable to vary an area of a non-depleted portion of the lateral area.

Abstract: A method of manufacturing a magnetoresistive element includes a tunnel barrier forming step. The tunnel barrier forming step comprises a metal layer forming step of forming a metal layer to have a first thickness, a plasma processing step of performing a plasma treatment which exposes the metal layer to a plasma of an inert gas to etch the metal layer to have a second thickness smaller than the first thickness, and an oxidation step of oxidizing the metal layer having undergone the plasma treatment to form a metal oxide which forms a tunnel barrier.

Abstract: The present invention provides a manufacturing method of a magneto-resistive element capable of obtaining a higher MR ratio, in a method of forming a metal oxide layer (e.g., MgO layer) by oxidation treatment of a metal layer (e.g., Mg layer). An embodiment of the present invention includes the steps of; providing a substrate having a first ferromagnetic layer; fabricating a tunnel barrier layer on the first ferromagnetic layer; and forming a second ferromagnetic layer on the tunnel barrier layer. The step of fabricating the tunnel barrier layer includes; the steps of; depositing a first metal layer on the first ferromagnetic layer; oxidizing the first metal layer; depositing a second metal layer on the oxidized first metal layer; and performing heating treatment on the oxidized first metal layer and the second metal layer at a temperature at which the second metal layer boils.

Abstract: A spin toque transfer magnetic random access memory (STTMRAM) element and a method of manufacturing the same is disclosed having a free sub-layer structure with enhanced internal stiffness. A first free sub-layer is deposited, the first free sub-layer being made partially of boron (B). Annealing is performed of the STTMRAM element at a first temperature after depositing the first free sub-layer to reduce the B content at an interface between the first free sub-layer and the barrier layer. Cooling down of the STTMRAM element to a second temperature that is lower than the first temperature is performed and a third free sub-layer is directly deposited on top of the second free layer, with the third free sub-layer being made partially of boron (B), wherein the amount of B in the third sub-free layer is less than the amount of B in the second free sub-layer.

Abstract: A channel layer is deposited on a first impurity layer, a second impurity layer is deposited on the channel layer, a gate electrode is placed to surround a circumference of the channel layer with a gate insulating film interposed therebetween, a spin-injection magnetization-reversal element is deposited on the second impurity layer, a bit line is placed on the spin-injection magnetization-reversal element, and a word line is placed on the bit line to be electrically connected to the gate electrode.

Abstract: According to one embodiment, a method of manufacturing a multilayer film, the method includes forming a first layer, forming a second layer on the first layer, and transcribing a crystal information of one of the first and second layers to the other one of the first and second layers by executing a GCIB-irradiation to the second layer.

Abstract: According to one embodiment, a method of manufacturing a magnetic memory, the method includes forming a first magnetic layer having a variable magnetization, forming a tunnel barrier layer on the first magnetic layer, forming a second magnetic layer on the tunnel barrier layer, the second magnetic layer having an invariable magnetization, forming a hard mask layer as a mask on the second magnetic layer, patterning the second magnetic layer by using the mask of the hard mask layer, and executing a GCIB-irradiation by using the mask of the hard mask layer, after the patterning.

Abstract: According to one embodiment, a memory device with magnetroresistive effect element is disclosed. The element includes first metal magnetic film (MMF) with nonmagnetic element and axis of easy magnetization perpendicular (EMP), first insulating film, first intermediate magnetic film between the first MMF and the first insulating film, second MMF on the first insulating film and including nonmagnetic elements, the second MMF having axis of EMP, second intermediate magnetic film between the first insulating film and the second MMF, and diffusion preventing film including metal nitride having barrier property against diffusion of the nonmagnetic elements between the first MMF and the first intermediate magnetic film.

Abstract: The pinning field in an MR device was significantly improved by using the Ru 4A peak together with steps to minimize interfacial roughness of the ruthenium layer as well as boron and manganese diffusion into the ruthenium layer during manufacturing. This made it possible to anneal at temperatures as high as 340° C. whereby a high MR ratio could be simultaneously achieved.

Abstract: An improved method of controlling topographical variations when milling a cross-section of a structure, which can be used to reduce topographical variation on a cross-section of a write-head in order to improve the accuracy of metrology applications. Topographical variation is reduced by using a protective layer that comprises a material having mill rates at higher incidence angles that closely approximate the mill rates of the structure at those higher incidence angles. Topographical variation can be intentionally introduced by using a protective layer that comprises a material having mill rates at higher incidence angles that do not closely approximate the mill rates of the structure at those higher incidence angles.

Abstract: An aspect of the present embodiment, there is provided magnetic random access memory device including a semiconductor substrate, a selection transistor on the semiconductor substrate, the selection transistor including a diffusion layer, a contact plug on diffusion layer, an amorphous film on the contact plug, a lower electrode provided on the amorphous film, a first magnetic layer, a nonmagnetic layer, a second magnetic layer, an upper electrode stacked in an order and a sidewall contact film on the contact plug, the sidewall contact film being in contact with a sidewall of the upper electrode.

Abstract: A method of packaging a magnetoresistive random access memory (MRAM) die includes providing a lead frame having a die pad and lead fingers. The MRAM die is attached to the die pad with a first die attach adhesive and bond pads of the MRAM die are electrically connected to the lead fingers of the lead frame with wires using a wire bonding process. A pre-formed composite magnetic shield is attached to a top surface of the MRAM die with a second die attach adhesive. The magnetic shield includes a magnetic permeable filler material dispersed within an organic matrix. An encapsulating material is dispensed onto a top surface of the lead frame, MRAM die and magnetic shield such that the encapsulating material covers the MRAM die and the magnetic shield. The encapsulating material is then cured.

Abstract: A method for fabricating a magnetic tunnel junction element includes forming a magneto resistance layer including a first magnetic layer, an insulation layer and a second magnetic layer on a substrate, forming a magnetic loss area by doping a magnetic loss impurity into a region of the magneto resistance layer to cause a magnetic loss, and etching the magnetic loss area to form a magnetic tunnel junction element.

Abstract: The present disclosure concerns a magnetic random access memory (MRAM) cell suitable for performing a thermally assisted write operation or a spin torque transfer (STT) based write operation, comprising a magnetic tunnel junction comprising a top electrode; a tunnel barrier layer comprised between a first ferromagnetic layer having a first magnetization direction, and a second ferromagnetic layer having a second magnetization direction adjustable with respect to the first magnetization direction; a front-end layer; and a magnetic or metallic layer on which the second ferromagnetic layer is deposited; the second ferromagnetic layer being comprised between the front-end layer and the tunnel barrier layer and having a thickness comprised between about 0.5 nm and about 2 nm, such that magnetic tunnel junction has a magnetoresistance larger than about 100%. The MRAM cell disclosed herein has lower power consumption compared to conventional MRAM cells.

Abstract: The present disclosure concerns memory device comprising magnetic tunnel junction comprising a tunnel barrier layer between a first ferromagnetic layer having a first magnetization with a fixed orientation and a second ferromagnetic layer having a second magnetization being freely orientable, and a polarizing layer having a polarizing magnetization substantially perpendicular to the first and second magnetization; the first and second ferromagnetic layers being annealed such that a tunnel magnetoresistance of the magnetic tunnel junction is equal or greater than about 150%. Also disclosed is a method of forming the MRAM cell.

Abstract: A spin torque oscillator and a method of making same. The spin torque oscillator is configured to generate microwave electrical oscillations without the use of a magnetic field external thereto, the spin torque oscillator having one of a plurality of input nanopillars and a nanopillar having a plurality of free FM layers.