Switching Materials Being Oxides Or Nitrides (epo) Patents (Class 257/E45.003)
  • Patent number: 8723152
    Abstract: A variable resistance memory according to an embodiment includes: a first wiring; a second wiring intersecting with the first wiring; a first electrode provided in an intersection region between the first wiring and the second wiring, the first electrode being connected to the first wiring; a second electrode connected to the second wiring, the second electrode facing to the first electrode; a variable resistance layer provided between the first electrode and the second electrode; and one of a first insulating layer and a first semiconductor layer formed at side portions of the second electrode. The one of the first insulating layer and the first semiconductor layer, and the second electrode form voids at the side portions of the second electrode.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: May 13, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshifumi Nishi, Hidenori Miyagawa, Daisuke Matsushita, Jun Fujiki, Takeshi Imamura
  • Patent number: 8723156
    Abstract: Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode comprising hafnium oxide and having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a material including metal titanium and having a second thickness that is less than 25 percent of the first thickness.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: May 13, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Ronald J. Kuse, Tony P. Chiang, Imran Hashim
  • Patent number: 8709834
    Abstract: A method of manufacturing a semiconductor device includes providing a wafer, forming a memory device which includes phase change material layer on the wafer, completing a wafer level process of manufacturing the semiconductor device, and performing a thermal treatment process on the wafer to densify the phase change material. To this end, the process temperature of the thermal treatment is higher than the crystallization temperature of the phase change material and lower than the melting point of the phase change material.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: April 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Hyun Hong, Jung-Hyuk Lee, Su-Jin Ahn, Dae-Won Ha
  • Patent number: 8710482
    Abstract: A memory component includes: a first electrode; a memory layer; and a second electrode in this order, wherein the memory layer includes a high resistance layer which includes tellurium (Te) as the chief component among anion components and is formed on the first electrode side; and an ion source layer which includes at least one kind of metal element and at least one kind of chalcogen element among tellurium (Te), sulfur (S) and selenium (Se) and is formed on the second electrode side.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: April 29, 2014
    Assignee: Sony Corporation
    Inventors: Shuichiro Yasuda, Katsuhisa Aratani, Kazuhiro Ohba, Hiroaki Sei
  • Patent number: 8710481
    Abstract: A non-volatile memory device includes a plurality of non-volatile memory cells. Each of the non-volatile memory cells includes a first electrode, a diode steering element, a storage element located in series with the diode steering element, a second electrode, and a nano-rail electrode having a width of 15 nm or less.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: April 29, 2014
    Assignee: SanDisk 3D LLC
    Inventors: James K. Kai, Henry Chien, George Matamis, Vinod R. Purayath
  • Patent number: 8705265
    Abstract: A device contains a first layer, a second layer; and a membrane between the first and second layers. Mobile ions are in at least one of the first and second layers, and the membrane is permeable to the ions. Interfaces of the conductive membrane with the first layer and the second layer are such that charge of a polarity of the ions collects at the interfaces.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: April 22, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Dmitri B. Strukov, Alexandre M. Bratkovski, R. Stanley Williams, Michael R. T. Tan
  • Publication number: 20140103282
    Abstract: Provided are resistive random access memory (ReRAM) cells having diffusion barrier layers formed from various materials, such as beryllium oxide or titanium silicon nitrides. Resistive switching layers used in ReRAM cells often need to have at least one inert interface such that substantially no materials pass through this interface. The other (reactive) interface may be used to introduce and remove defects from the resistive switching layers causing the switching. While some electrode materials, such as platinum and doped polysilicon, may form inert interfaces, these materials are often difficult to integrate. To expand electrode material options, a diffusion barrier layer is disposed between an electrode and a resistive switching layer and forms the inert interface with the resistive switching layer. In some embodiments, tantalum nitride and titanium nitride may be used for electrodes separated by such diffusion barrier layers.
    Type: Application
    Filed: October 16, 2012
    Publication date: April 17, 2014
    Applicant: INTERMOLECULAR INC.
    Inventors: Yun Wang, Imran Hashim
  • Patent number: 8698121
    Abstract: A resistive switching memory is described, including a first electrode comprising doped silicon having a first work function, a second electrode having a second work function that is different from the first work function by between 0.1 and 1.0 electron volts (eV), a metal oxide layer between the first electrode and the second electrode, the metal oxide layer switches using bulk-mediated switching using unipolar or bipolar switching voltages for switching from a low resistance state to a high resistance state and vice versa.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: April 15, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Prashant B. Phatak, Tony P. Chiang, Michael Miller, Wen Wu
  • Patent number: 8692222
    Abstract: A nonvolatile memory element according to the present disclosure includes: a variable resistance element including a first electrode layer, a second electrode layer, and a variable resistance layer which is located between the first electrode layer and the second electrode layer and has a resistance value that reversibly changes based on an electrical signal applied between the first electrode layer and the second electrode layer; and a fixed resistance layer having a predetermined resistance value and stacked together with the variable resistance element. The variable resistance layer includes (i) a first transition metal oxide layer which is oxygen deficient and (ii) a second transition metal oxide layer which has a higher oxygen content atomic percentage than the first transition metal oxide layer. The predetermined resistance value ranges from 70? to 1000? inclusive.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: April 8, 2014
    Assignee: Panasonic Corporation
    Inventors: Shinichi Yoneda, Takumi Mikawa
  • Publication number: 20140091271
    Abstract: A semiconductor structure includes a resistance variable memory structure. The semiconductor structure also includes a dielectric layer. A portion of the resistance variable memory structure is over the dielectric layer. The resistance variable memory structure includes a first electrode embedded in the dielectric layer. A resistance variable layer disposed over the first electrode and a portion of the dielectric layer. A second electrode disposed over the resistance variable layer.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Kuo-Chi TU
  • Publication number: 20140091270
    Abstract: Low energy memristors with engineered switching channel materials include: a first electrode; a second electrode; and a switching layer positioned between the first electrode and the second electrode, wherein the switching layer includes a first phase comprising an insulating matrix in which is dispersed a second phase comprising an electrically conducting compound material for forming a switching channel.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Jianhua Yang, Minxian Max Zhang, Gilberto Medeiros Ribeiro, R. Stanley Williams
  • Publication number: 20140092666
    Abstract: Low voltage embedded memory having conductive oxide and electrode stacks is described. For example, a material layer stack for a memory element includes a first conductive electrode. A conductive oxide layer is disposed on the first conductive electrode. The conductive oxide layer has a plurality of oxygen vacancies therein. A second electrode is disposed on the conductive oxide layer.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: Elijah V. Karpov, Brian S. Doyle, Charles C. Kuo, Robert S. Chau, Eric R. Dickey, Michael Stephen Bowen, Sey-Shing Sun
  • Publication number: 20140091272
    Abstract: A semiconductor structure includes a resistance variable memory structure. The semiconductor structure also includes a conductive structure. The resistance variable memory structure is over the conductive structure. The resistance variable memory structure includes a first electrode over the conductive structure. A resistance variable layer is disposed over the first electrode. A cap layer is disposed over the resistance variable layer. The cap layer includes a first metal material. A second electrode disposed over the cap layer. The second electrode includes a second metal material different from the first metal material.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Wen LIAO, Wen-Ting CHU, Chin-Chieh YANG, Kuo-Chi TU, Chih-Yang CHANG, Hsia-Wei CHEN
  • Patent number: 8686419
    Abstract: A memory device in a 3-D read and write memory includes a resistance-changing layer, and a local contact resistance in series with, and local to, the resistance-changing layer. The local contact resistance is established by a junction between a semiconductor layer and a metal layer. Further, the local contact resistance has a specified level of resistance according to a doping concentration of the semiconductor and a barrier height of the junction. A method for fabricating such a memory device is also presented.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: April 1, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Franz Kreupl, Deepak C Sekar
  • Patent number: 8686390
    Abstract: Provided is a nonvolatile memory element achieving a stable resistance change and miniaturization, and a method of manufacturing the same. The nonvolatile memory element includes: a first electrode formed above a substrate; an interlayer insulating layer formed above the substrate including the first electrode and having a memory cell hole reaching the first electrode; a barrier layer formed in the memory cell hole and composed of a semiconductor layer or an insulating layer connected to the first electrode; a second electrode formed in the memory cell hole and connected to the barrier layer; a variable resistance layer formed on the second electrode and having a stacked structure whose resistance value changes based on electric signals; and a third electrode connected to the variable resistance layer and formed on the interlayer insulating layer to cover the memory cell hole.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: April 1, 2014
    Assignee: Panasonic Corporation
    Inventor: Takeshi Takagi
  • Patent number: 8680505
    Abstract: A semiconductor memory device, including: plural parallel first lines; plural second lines disposed to intersect the first lines; and a memory cell array including memory cells, disposed at intersections of the first lines and the second lines, each of the memory cells configured by a rectifier element and a variable resistor connected in series. The rectifier element includes: a first semiconductor region including an impurity of a first conductivity type at a first impurity concentration; and a second semiconductor region including an impurity of a second conductivity type at a second impurity concentration lower than the first impurity concentration and including an impurity of the first conductivity type at a third impurity concentration lower than the second impurity concentration, the first and second semiconductor regions being formed by silicon.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: March 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroomi Nakajima
  • Publication number: 20140077149
    Abstract: A resistance memory cell including a variable resistance layer is provided. The variable resistance layer includes at least one dominant resistance layer and at least one auxiliary resistance layer. The dominant resistance layer(s) and the auxiliary resistance layer(s) in totality form a closed ion exchange system, the exchanged ions are comparably mobile in each of the dominant resistance layer(s) and the auxiliary resistance layer(s), and the maximum resistance of the at least one dominant resistance layer is higher than that of the at least one auxiliary resistance layer.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Frederick T. Chen, Heng-Yuan Lee, Yu-Sheng Chen, Wei-Su Chen, Tai-Yuan Wu, Pang-Hsu Chen
  • Patent number: 8674335
    Abstract: A memory component includes: a first electrode; a memory layer; and a second electrode in this order, wherein the memory layer includes a high resistance layer which includes tellurium (Te) as the chief component among anion components and is formed on the first electrode side; and an ion source layer which includes at least one kind of metal element and at least one kind of chalcogen element among tellurium (Te), sulfur (S) and selenium (Se) and is formed on the second electrode side.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: March 18, 2014
    Assignee: Sony Corporation
    Inventors: Shuichiro Yasuda, Katsuhisa Aratani, Kazuhiro Ohba, Hiroaki Sei
  • Patent number: 8674336
    Abstract: A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Insulative material is deposited over the first electrode. An opening is formed into the insulative material over the first electrode. The opening includes sidewalls and a base. The opening sidewalls and base are lined with a multi-resistive state layer comprising multi-resistive state metal oxide-comprising material which less than fills the opening. A second conductive electrode of the memory cell is formed within the opening laterally inward of the multi-resistive state layer lining the sidewalls and elevationally over the multi-resistive state layer lining the base. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: March 18, 2014
    Assignee: Micron Technology, Inc.
    Inventors: John Smythe, Bhaskar Srinivasan, Gurtej S. Sandhu
  • Publication number: 20140070159
    Abstract: An RRAM at an STI region is disclosed with a vertical BJT selector. Embodiments include defining an STI region in a substrate, implanting dopants in the substrate to form a well of a first polarity around and below an STI region bottom portion, a band of a second polarity over the well on opposite sides of the STI region, and an active area of the first polarity over each band of second polarity at the surface of the substrate, forming a hardmask on the active areas, removing an STI region top portion to form a cavity, forming an RRAM liner on cavity side and bottom surfaces, forming a top electrode in the cavity, removing a portion of the hardmask to form spacers on opposite sides of the cavity, and implanting a dopant of the second polarity in a portion of each active area remote from the cavity.
    Type: Application
    Filed: September 12, 2012
    Publication date: March 13, 2014
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Shyue Seng Tan, Eng Huat Toh, Elgin Quek
  • Patent number: 8664651
    Abstract: A switching device includes a first electrode (101), a second electrode (102), and a complex oxide ion conducting layer (103) interposed between the first electrode (101) and the second electrode (102). The complex oxide ion conducting layer (103) contains at least two oxides including a metal oxide. The first electrode (101) can supply electrons to the complex oxide ion conducting layer (103). The second electrode (102) contains a metal and can supply ions of the metal to the complex oxide ion conducting layer (103).
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: March 4, 2014
    Assignee: NEC Corporation
    Inventor: Naoki Banno
  • Patent number: 8659001
    Abstract: Embodiments of the present invention generally relate to a resistive switching nonvolatile memory element that is formed in a resistive switching memory device that may be used in a memory array to store digital data. The memory element is generally constructed as a metal-insulator-metal stack. The resistive switching portion of the memory element includes a getter portion and/or a defect portion. In general, the getter portion is an area of the memory element that is used to help form, during the resistive switching memory device's fabrication process, a region of the resistive switching layer that has a greater number of vacancies or defects as compared to the remainder of resistive switching layer. The defect portion is an area of the memory element that has a greater number of vacancies or defects as compared to the remainder of the resistive switching layer, and is formed during the resistive switching memory device's fabrication process.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: February 25, 2014
    Assignees: Sandisk 3D LLC, Kabushiki Kaisha Toshiba
    Inventors: Yun Wang, Tony Chiang, Imran Hashim
  • Patent number: 8658463
    Abstract: A method of making a memristor having an embedded switching layer include exposing a surface portion of a first electrode material within a via to a reactive species to form the switching layer embedded within and at surface of the via. The via is in contact with a first conductor trace. The method further includes depositing a layer of a second electrode material adjacent to the via surface and patterning the layer into a column aligned with the via. The method further includes depositing an interlayer dielectric material to surround the column and providing a second conductor trace in electrical contact with the second electrode material of the column.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: February 25, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Janice H. Nickel, Matthew D. Pickett
  • Patent number: 8637845
    Abstract: Optimized electrodes for ReRAM memory cells and methods for forming the same are discloses. One aspect comprises forming a first electrode, forming a state change element in contact with the first electrode, treating the state change element, and forming a second electrode. Treating the state change element increases the barrier height at the interface between the second electrode and the state change element. Another aspect comprises forming a first electrode in a manner to deliberately establish a certain degree of amorphization in the first electrode, forming a state change element in contact with the first electrode. The degree of amorphization of the first electrode is either at least as great as the degree of amorphization of the state change element or no more than 5 percent less than the degree of amorphization of the state change element.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: January 28, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Deepak C. Sekar, April Schricker, Xiying Chen, Klaus Schuegraf
  • Patent number: 8624219
    Abstract: A memory device can include at least one cathode formed in first opening of a first insulating layer; at least one anode formed in a second opening of second insulating layer, the second insulating layer being a different vertical layer than the first insulating layer; and a memory layer comprising an ion conductor layer extending laterally between the at least one anode and cathode on the first insulating layer, the ion conductor layer having a thickness in the vertical direction less than a depth of the first opening.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: January 7, 2014
    Assignee: Adesto Technologies Corporation
    Inventors: John Ross Jameson, Antonio R. Gallo, Foroozan Sarah Koushan, Michael A. Van Buskirk
  • Patent number: 8610098
    Abstract: Memory cells are described along with arrays and methods for manufacturing. An embodiment of a memory cell as described herein includes a second doped semiconductor region on a first doped semiconductor region and defining a pn junction therebetween. A first electrode on the second doped semiconductor region. An insulating member between the first electrode and a second electrode, the insulating member having a thickness between the first and second electrodes. A bridge of memory material across the insulating member, the bridge having a bottom surface and contacting the first and second electrodes on the bottom surface, and defining an inter-electrode path between the first and second electrodes across the insulating member, the inter-electrode path having a path length defined by the thickness of the insulating member, wherein the memory material has at least two solid phases.
    Type: Grant
    Filed: April 6, 2007
    Date of Patent: December 17, 2013
    Assignee: Macronix International Co., Ltd.
    Inventor: Hsiang-Lan Lung
  • Publication number: 20130320289
    Abstract: A resistance random access memory including a first electrode layer, a second electrode layer, and a stacked structure is provided. The stacked structure includes a HfZrON layer and a ZrON layer and is located between the first electrode layer and the second electrode layer. In addition, the disclosure further provides a method of fabricating a resistance random access memory.
    Type: Application
    Filed: September 13, 2012
    Publication date: December 5, 2013
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Wei-Su Chen, Tai-Yuan Wu, Frederick T. Chen, Pang-Hsu Chen
  • Patent number: 8581224
    Abstract: Some embodiments include memory cells which contain, in order; a first electrode material, a first metal oxide material, a second metal oxide material, and a second electrode material. The first metal oxide material has at least two regions which differ in oxygen concentration relative to one another. One of the regions is a first region and another is a second region. The first region is closer to the first electrode material than the second region, and has a greater oxygen concentration than the second region. The second metal oxide material includes a different metal than the first metal oxide material. Some embodiments include methods of forming memory cells in which oxygen is substantially irreversibly transferred from a region of a metal oxide material to an oxygen-sink material. The oxygen transfer creates a difference in oxygen concentration within one region of the metal oxide material relative to another.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: November 12, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Bhaskar Srinivasan
  • Publication number: 20130292625
    Abstract: Some embodiments include a memory cell having a data storage region between a pair of conductive structures. The data storage region is configured to support a transitory structure which alters resistance through the memory cell. The data storage region includes two or more portions, with one of the portions supporting a higher resistance segment of the transitory structure than another of the portions. Some embodiments include a method of forming a memory cell. First oxide and second oxide regions are formed between a pair of conductive structures. The oxide regions are configured to support a transitory structure which alters resistance through the memory cell. The oxide regions are different from one another so that one of the oxide regions supports a higher resistance segment of the transitory structure than the other.
    Type: Application
    Filed: May 4, 2012
    Publication date: November 7, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Gurtej S. Sandhu, Sumeet C. Pandey
  • Publication number: 20130292634
    Abstract: In some aspects, a memory cell is provided that includes a steering element, a metal-insulator-metal (“MIM”) stack coupled in series with the steering element, and a conductor above the MIM stack. The MIM stack includes a resistance switching element and a top electrode disposed on the resistance switching element, and the top electrode includes a highly doped semiconductor material. The memory cell does not include a metal layer between the MIM stack and the conductor. Numerous other aspects are provided.
    Type: Application
    Filed: May 7, 2012
    Publication date: November 7, 2013
    Inventors: Yung-Tin Chen, Kun Hou, Zhida Lan
  • Publication number: 20130292626
    Abstract: Resistive memory having confined filament formation is described herein. One or more method embodiments include forming an opening in a stack having a silicon material and an oxide material on the silicon material, and forming an oxide material in the opening adjacent the silicon material, wherein the oxide material formed in the opening confines filament formation in the resistive memory cell to an area enclosed by the oxide material formed in the opening.
    Type: Application
    Filed: May 7, 2012
    Publication date: November 7, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Eugene P. Marsh, Jun Liu
  • Patent number: 8575585
    Abstract: A memristive device includes a first electrode, a second electrode crossing the first electrode at a non-zero angle, and an active region disposed between the first and second electrodes. The active region has a controlled defect profile throughout its thickness.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: November 5, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jianhua Yang, Qiangfei Xia, Alexandre M. Bratkovski
  • Patent number: 8574958
    Abstract: This invention belongs to semiconductor device manufacturing field and discloses a method for manufacturing a gate-control diode semiconductor storage device. When the floating gate voltage is relatively high, the channel under the floating gate is of n type and a simple gate-control pn junction structure is configured; by controlling effective n-type concentration of the ZnO film through back-gate control, inverting the n-type ZnO into p-type through a floating gate and using NiO as a p-type semiconductor, an n-p-n-p doping structure is formed while the quantity of charges in the floating gate determines the device threshold voltage, thus realizing memory functions. This invention features capacity of manufacturing gate-control diode memory devices able to reduce the chip power consumption through advantages of high driving current and small sub-threshold swing.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: November 5, 2013
    Assignee: Fudan University
    Inventors: Pengfei Wang, Xiaoyong Liu, Qingqing Sun, Wei Zhang
  • Patent number: 8569728
    Abstract: A nonvolatile memory device includes: a first conductive layer; a second conductive layer; a first resistance change layer provided between the first conductive layer and the second conductive layer and having an electrical resistance changing with at least one of an applied electric field and a passed current; and a first lateral layer provided on a lateral surface of the first resistance change layer and having an oxygen concentration higher than an oxygen concentration in the first resistance change layer.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: October 29, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kensuke Takano, Yoshio Ozawa, Katsuyuki Sekine, Junichi Wada
  • Patent number: 8569105
    Abstract: A method and apparatus is provided for forming a resistive memory device having good adhesion among the components thereof. A first conductive layer is formed on a substrate, and the surface of the first conductive layer is treated to add adhesion promoting materials to the surface. The adhesion promoting materials may form a layer on the surface, or they may incorporate into the surface or merely passivate the surface of the first conductive layer. A variable resistance layer is formed on the treated surface, and a second conductive layer is formed on the variable resistance layer. Adhesion promoting materials may also be included at the interface between the variable resistance layer and the second conductive layer.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: October 29, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Siu F. Cheng, Deenesh Padhi
  • Publication number: 20130264533
    Abstract: A resistive random access memory (ReRAM) includes a first metal layer having a first metal and a metal-oxide layer on the first metal layer. The metal-oxide layer inlcudes the first metal. The ReRAM further includes a second metal layer over the metal-oxide layer and a first continuous conductive barrier layer in physical contact with sidewalls of the first metal layer and of the metal-oxide layer.
    Type: Application
    Filed: April 9, 2012
    Publication date: October 10, 2013
    Inventors: CHEONG Min HONG, Ko-Min Chang, Feng Zhou
  • Patent number: 8547721
    Abstract: Disclosed is a resistive memory device. In the resistive memory device, at least one variable resistance region and at least one switching device may be horizontally apart from each other, rather than being disposed on the same vertical axis. At least one intermediate electrode, which electrically connects the at least one variable resistance region and the at least one switching device, may be between the at least one variable resistance region and the at least one switching device.
    Type: Grant
    Filed: April 13, 2009
    Date of Patent: October 1, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seungeon Ahn, Kihwan Kim, Changjung Kim, Myungjae Lee, Bosoo Kang, Changbum Lee
  • Patent number: 8546780
    Abstract: According to one embodiment, a non-volatile memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction, and a variable resistance memory cell which is disposed at an intersection between the first wiring and the second wiring so as to be held between the first wiring and the second wiring and includes a variable resistive element and a rectifying element. In a space between the variable resistance memory cells adjacent to each other, at least a periphery of the variable resistive element is evacuated or filled with a gas.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: October 1, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jun Iijima, Yasuyoshi Hyodo, Akihiro Kajita
  • Publication number: 20130248814
    Abstract: A non-volatile memory device including a first electrode, a resistor structure, a diode structure, and a second electrode is provided. The resistor structure is disposed on the first electrode. The resistor structure includes a first oxide layer. The first oxide layer is disposed on the first electrode. The diode structure is disposed on the resistor structure. The diode structure includes a metal layer and a second oxide layer. The metal layer is disposed on the first oxide layer. The second oxide layer is disposed on the metal layer. The second electrode is disposed on the diode structure. A material of the metal layer is different from that of the second electrode. Furthermore, a non-volatile memory array including the foregoing memory devices is also provided.
    Type: Application
    Filed: March 20, 2012
    Publication date: September 26, 2013
    Applicant: WINBOND ELECTRONICS CORP.
    Inventors: Tuo-Hung Hou, Jiun-Jia Huang
  • Publication number: 20130250656
    Abstract: A memory device includes a first electrode, a second electrode, a third electrode, a first variable resistance layer between the first electrode and the third electrode, and a second variable resistance layer between the second electrode and the third electrode. The first, second, and third electrodes, and the first and second variable resistance layers are formed of materials that cause the first variable resistance layer to transition from a high resistance state to a low resistance state when a voltage is applied across the first and second electrodes and maintain the high resistance state when the voltage is cut off, and cause the second variable resistance layer to transition from a high resistance state to a low resistance state when the voltage is applied across the first and second electrodes and transition from the high resistance state to the low resistance state when the voltage is cut off.
    Type: Application
    Filed: September 6, 2012
    Publication date: September 26, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takayuki ISHIKAWA, Yoshifumi Nishi, Daisuke Matsushita, Masato Koyama
  • Publication number: 20130248797
    Abstract: Some embodiments include methods of forming memory cells. An opening is formed over a first conductive structure to expose an upper surface of the first conductive structure. The opening has a bottom level with a bottom width. The opening has a second level over the bottom level, with the second level having a second width which is greater than the bottom width. The bottom level of the opening is filled with a first portion of a multi-portion programmable material, and the second level is lined with the first portion. The lined second level is filled with a second portion of the multi-portion programmable material. A second conductive structure is formed over the second portion. Some embodiments include memory cells.
    Type: Application
    Filed: March 22, 2012
    Publication date: September 26, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Gurtej S. Sandhu, Scott E. Sills
  • Patent number: 8536562
    Abstract: Some embodiments include methods of forming memory structures. An electrically insulative line is formed over a base. Electrode material is deposited over the line and patterned to form a pair of bottom electrodes along the sidewalls of the line. Programmable material is formed over the bottom electrodes, and a top electrode is formed over the programmable material. The bottom electrodes may each contain at least one segment which extends at angle of from greater than 0° to less than or equal to about 90° relative to a planar topography of the base. Some embodiments include memory structures having a bottom electrode extending upwardly from a conductive contact to a programmable material, with the bottom electrode having a thickness of less than or equal to about 10 nanometers. Some embodiments include memory arrays and methods of forming memory arrays.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: September 17, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Scott E. Sills
  • Patent number: 8536015
    Abstract: In accordance with aspects of the invention, a method of forming a metal-insulator-metal stack is provided. The method includes forming a first conducting layer, forming a resistivity-switching carbon-based material above the first conducting layer, and forming a second conducting layer above the carbon-based material, wherein the carbon-based material has a thickness of not more than ten atomic layers. Other aspects are also described.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: September 17, 2013
    Assignee: SanDisk 3D LLC
    Inventors: Roy E. Scheuerlein, Alper Ilkbahar, April D. Schricker
  • Publication number: 20130234094
    Abstract: Methods and apparatuses for a resistive random access memory (RRAM) device are disclosed. The RRAM device comprises a bottom electrode, a resistive switching layer disposed on the bottom electrode, and a top electrode disposed on the resistive switching layer. The resistive switching layer is made of a composite of a metal, Si, and O. There may be an additional tunnel barrier layer between the top electrode and the bottom electrode. The top electrode and the bottom electrode may comprise multiple sub-layers.
    Type: Application
    Filed: March 9, 2012
    Publication date: September 12, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Chang Chang, Yong-En Syu, Fu-Yen Jian, Shih-Chieh Chang, Ying-Lang Wang
  • Patent number: 8530879
    Abstract: A semiconductor memory device in accordance with an embodiment comprises first lines, second lines, and a memory cell array including memory cells. Each of the memory cells is disposed at each of intersections of the first lines and the second lines and is configured by a rectifier element and a variable resistor connected in series. The rectifier element comprises a first semiconductor region of a first conductivity type including an impurity of a first impurity concentration, and a second semiconductor region of a second conductivity type including an impurity of a second impurity concentration lower than the first impurity concentration. The first semiconductor region and the second semiconductor region are formed by silicon. A junction interface of the first semiconductor region and the second semiconductor region is a pseudo-heterojunction formed by two layers that have different band gap widths and are formed of the same material.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: September 10, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroomi Nakajima
  • Patent number: 8530873
    Abstract: An electroforming free memristor includes a first electrode, a second electrode spaced from the first electrode, and a switching layer positioned between the first electrode and the second electrode. The switching layer is formed of a matrix of a switching material and reactive particles that are to react with the switching material during a fabrication process of the memristor to form one or more conductance channels in the switching layer.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: September 10, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jianhua Yang, Gilberto Medeiros Ribeiro, R Stanley Williams
  • Publication number: 20130228735
    Abstract: A nonvolatile resistive memory element includes a host oxide formed from an interfacial oxide layer. The interfacial oxide layer is formed on the surface of a deposited electrode layer via in situ or post-deposition surface oxidation treatments. The switching performance of a resistive memory device based on such an interfacial oxide layer is equivalent or superior to the performance of a conventional resistive memory element.
    Type: Application
    Filed: March 1, 2012
    Publication date: September 5, 2013
    Applicant: Intermolecular, Inc.
    Inventors: Randall Higuchi, Tony P. Chiang, Ryan Clarke, Vidyut Gopal, Imran Hashim, Robert Huertas, Yun Wang
  • Patent number: 8526213
    Abstract: Some embodiments include methods of programming a memory cell. A plurality of charge carriers may be moved within the memory cell, with an average charge across the moving charge carriers having an absolute value greater than 2. Some embodiments include methods of forming and programming an ionic-transport-based memory cell. A stack is formed to have programmable material between first and second electrodes. The programmable material has mobile ions which are moved within the programmable material to transform the programmable material from one memory state to another. An average charge across the moving mobile ions has an absolute value greater than 2. Some embodiments include memory cells with programmable material between first and second electrodes. The programmable material includes an aluminum nitride first layer, and includes a second layer containing a mobile ion species in common with the first layer.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: September 3, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Roy E. Meade, Bhaskar Srinivasan, Gurtej S. Sandhu
  • Publication number: 20130221308
    Abstract: Disclosed herein is a compact RRAM (Resistance Random Access Memory) device structure and various methods of making such an RRAM device. In one example, a device disclosed herein includes a gate electrode, a conductive sidewall spacer and at least one variable resistance material layer positioned between the gate electrode and the conductive sidewall spacer.
    Type: Application
    Filed: February 29, 2012
    Publication date: August 29, 2013
    Applicant: GLOBALFOUNDRIES SINGAPORE PTE LTD
    Inventors: Eng Huat Toh, Elgin Quek, Shyue Seng Tan
  • Publication number: 20130214232
    Abstract: Embodiments of the invention include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. The electrical properties of the current limiting component are configured to lower the current flow through the variable resistance layer during the logic state programming steps by adding a fixed series resistance in the resistive switching memory element of the nonvolatile memory device. In some embodiments, the current limiting component comprises a varistor that is a current limiting material disposed within a resistive switching memory element in a nonvolatile resistive switching memory device.
    Type: Application
    Filed: February 17, 2012
    Publication date: August 22, 2013
    Applicant: Intermolecular, Inc.
    Inventors: Mihir Tendulkar, Imran Hashim, Yun Wang