Abstract: A CNT channel layer of a transistor is cut along a direction perpendicular to the channel to form a plurality of CNT patches, which are used to connect between a source and a drain. The arrangement of the CNT channel layer formed of a plurality of CNT patches can increase the probability that part of CNT patches becomes a semiconductive CNT patch. Since part of a plurality of CNT patches forming the channel layer is formed of a semiconductive CNT patch, a transistor having a good on/off ratio can be provided.

Abstract: The present invention relates to a heat dissipator that includes a conductive substrate and a plurality of nanostructures supported by the conductive substrate. The nanostructures are at least partly embedded in an insulator. Each of the nanostructures includes a plurality of intermediate layers on the conductive substrate. At least two of the plurality of intermediate layers are interdiffused, and material of the at least two of the plurality of intermediate layers that are interdiffused is present in the nanostructure.

Abstract: An example of a carbon nanotube capacitor may include (i) a carbon nanotube film having carbon nanotubes and voids with dielectric material, (ii) conductive contacts and (iii) a dielectric layer. The carbon nanotube film may switch from a conductive state to a non-conductive state when a voltage is applied by creating an electrical break within the carbon nanotube film and providing a first conductive region and a second conductive region within the carbon nanotube film. The electrical break may separate the first conductive region from the second conductive region. The first and second conductive regions may store charge. An integrated device may include one or more transistors and one or more carbon nanotube capacitors. A method of making a carbon nanotube capacitor is also disclosed.

Abstract: A manufacturing method of the nano-wire field effect transistor, comprising steps of preparing an SOI substrate having a (100) surface orientation; processing a silicon crystal layer comprising the SOI substrate into a standing plate-shaped member having a rectangular cross-section; processing the silicon crystal layer by orientation dependent wet etching and thermal oxidation into a shape where two triangular columnar members are arranged one above the other with a spacing from each other so as to face along the ridge lines of the triangular columnar members; and processing the two triangular columnar members into a circular columnar member configuring a nano-wire by hydrogen annealing or thermal oxidation.

Abstract: A tape adhesive type material is directionally conductive. According to an example embodiment of the present invention, carbon nanotubes (212, 214, 216, 218) are configured in a generally parallel arrangement in a tape base type material (210). The carbon nanotubes conduct (e.g., electrically and/or thermally) in their generally parallel direction and the tape base type material inhibits conduction in a generally lateral direction. In some implementations, the tape base material is arranged between integrated circuit components (220, 230), with the carbon nanotubes making a conductive connection there between. This approach is applicable to coupling a variety of components together, such as integrated circuit dies (flip chip and conventional dies) to package substrates, to each other and/or to leadframes.

Abstract: A carbon nanotube solder is formed on a substrate of an integrated circuit package. The carbon nanotube solder exhibits high heat and electrical conductivities. The carbon nanotube solder is used as a solder microcap on a metal bump for communication between an integrated circuit device and external structures.

Abstract: The invention relates to a method for functionalizing a conductive or semiconductor material (M) by covalent grafting of receptor molecules (R) to its surface, said method comprising the following steps: (i) applying, across the terminals of a source electrode and a drain electrode located on either side of the material (M), sufficient potential difference to thermally activate the material (M) with respect to the grafting reaction of the molecules (R); and (ii) placing the material (M) thus activated in contact with a liquid or gaseous medium containing receptor molecules (R), thereby obtaining a material (M) functionalized by covalently grafted receptor molecules (R).

Abstract: A thin film transistor includes a multi-coaxial silicon nanowire unit including a plurality of coaxial silicon nanowires on a substrate, the multi-coaxial silicon nanowire unit including a central portion and end portions of the central portion; a gate electrode on the central portion; and a source electrode and a drain electrode on the respective end portions, respectively, so as to electrically connect to the multi-coaxial silicon nanowire unit.

Abstract: Disclosed are a carbon nano-tube (CNT) light emitting device and a method of manufacturing the same. Specifically, the CNT light emitting device comprises: a CNT thin film formed using a CNT dispersed solution; a n-doping polymer formed on one end of the CNT thin film; a p-doping polymer formed on the other end of the CNT thin film; and a light emitting part between the n-doping polymer and the p-doping polymer. In addition, the method of manufacturing a CNT light emitting device comprises steps of: mixing CNTs with a dispersing agent or dispersing solvent to prepare a CNT dispersed solution; forming a CNT thin film using the CNT dispersed solution; coating a n-doping polymer on one end of the CNT thin film; and coating a p-doping polymer on the other end of the CNT thin film.

Abstract: Field effect devices having channels of nanofabric and methods of making same. A nanotube field effect transistor is made to have a substrate, and a drain region and a source region in spaced relation relative to each other. A channel region is formed from a fabric of nanotubes, in which the nanotubes of the channel region are substantially all of the same semiconducting type of nanotubes. At least one gate is formed in proximity to the channel region so that the gate may be used to modulate the conductivity of the channel region so that a conductive path may be formed between the drain and source region. Forming a channel region includes forming a fabric of nanotubes in which the fabric has both semiconducting and metallic nanotubes and the fabric is processed to remove substantially all of the metallic nanotubes.

Abstract: A method for depositing graphene is provided. The method includes depositing a layer of non-conducting amorphous carbon over a surface of a substrate and depositing a transition metal in a pattern over the amorphous carbon. The substrate is annealed at a temperature below 500° C., where the annealing converts the non-conducting amorphous carbon disposed under the transition metal to conducting amorphous carbon. A portion of the pattern of the transition metal is removed from the surface of the substrate to expose the conducting amorphous carbon.

Abstract: Sensor platforms and methods of making them are described. A platform having a non-horizontally oriented sensor element comprising one or more nanostructures such as nanotubes is described. Under certain embodiments, a sensor element has or is made to have an affinity for an analyte. Under certain embodiments, such a sensor element comprises one or more pristine nanotubes. Under certain embodiments, the sensor element comprises derivatized or functionalized nanotubes. Under certain embodiments, a sensor is made by providing a support structure; providing one or more nanotubes on the structure to provide material for a sensor element; and providing circuitry to electrically sense the sensor element's electrical characterization. Under certain embodiments, the sensor element comprises pre-derivatized or pre-functionalized nanotubes. Under other embodiments, sensor material is derivatized or functionalized after provision on the structure or after patterning.

Abstract: A disposable material layer is first deposited on a graphene layer or a carbon nanotube (CNT). The disposable material layer includes a material that is less inert than graphene or CNT so that a contiguous dielectric material layer can be deposited at a target dielectric thickness without pinholes therein. A gate stack is formed by patterning the contiguous dielectric material layer and a gate conductor layer deposited thereupon. The disposable material layer shields and protects the graphene layer or the CNT during formation of the gate stack. The disposable material layer is then removed by a selective etch, releasing a free-standing gate structure. The free-standing gate structure is collapsed onto the graphene layer or the CNT below at the end of the selective etch so that the bottom surface of the contiguous dielectric material layer contacts an upper surface of the graphene layer or the CNT.

Abstract: An in situ approach toward connecting and electrically contacting vertically aligned nanowire arrays using conductive nanoparticles is provided. The utility of the approach is demonstrated by development of a gas sensing device employing the nanowire assembly. Well-aligned, single-crystalline zinc oxide nanowires were grown through a direct thermal evaporation process at 550° C. on gold catalyst layers. Electrical contact to the top of the nanowire array was established by creating a contiguous nanoparticle film through electrostatic attachment of conductive gold nanoparticles exclusively onto the tips of nanowires. A gas sensing device was constructed using such an arrangement and the nanowire assembly was found to be sensitive to both reducing (methanol) and oxidizing (nitrous oxides) gases. This assembly approach is amenable to any nanowire array for which a top contact electrode is needed.

Abstract: Example embodiments relate to an electrode having a transparent electrode layer, an opaque electrode layer formed on the transparent electrode layer and catalyst formed on an open surface on the transparent electrode layer, which open surface is not covered by the opaque electrode layer.

Abstract: A device and method for device fabrication includes forming a buried gate electrode in a dielectric substrate and patterning a stack comprising a high dielectric constant layer, a carbon-based semi-conductive layer and a protection layer over the buried gate electrode. An isolation dielectric layer formed over the stack is opened to define recesses in regions adjacent to the stack. The recesses are etched to form cavities and remove a portion of the high dielectric constant layer to expose the carbon-based semi-conductive layer on opposite sides of the buried gate electrode. A conductive material is deposited in the cavities to form self-aligned source and drain regions.

Abstract: Carbon transistor devices having channels formed from carbon nanostructures, such as carbon nanotubes or graphene, and having charged monolayers to reduce parasitic resistance in un-gated regions of the channels, and methods for fabricating carbon transistor devices having charged monolayers to reduce parasitic resistance.

Abstract: A problem of a switching element using for the active layer a carbon nanotube (CNT) dispersion film that can be manufactured at low temperature has been that sufficient electrical contact and thermal conductivity between the CNTs and the source and drain electrode surfaces are not obtained. The switching element of the present invention has a structure in which a mixed layer of carbon nanotubes and a metal material, and a metal layer of the metal material are laminated in this order on source and drain electrodes, and thereby, the CNT-dispersed film and the electrode surfaces can be in firm electrical, mechanical, and thermal contact with each other. Thus, a switching element exhibiting good and stable transistor characteristics is obtained with a low-temperature, convenient, and low-cost process.

Abstract: A field effect transistor (FET) includes a drain formed of a first material, a source formed of the first material, a channel formed by a nanostructure coupling the source to the drain, and a gate formed between the source and the drain and surrounding the nanostructure.

Abstract: Transistor devices having vertically stacked carbon nanotube channels and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; a bottom gate embedded in the substrate with a top surface of the bottom gate being substantially coplanar with a surface of the substrate; a stack of device layers on the substrate over the bottom gate, wherein each of the device layers in the stack includes a first dielectric, a carbon nanotube channel on the first dielectric, a second dielectric on the carbon nanotube channel and a top gate on the second dielectric; and source and drain contacts that interconnect the carbon nanotube channels in parallel. A method of fabricating a transistor device is also provided.

Abstract: Embodiments of the present invention are generally directed to a method for disposing nanoparticles on a substrate. In one embodiment, a substrate having a plurality of recesses is provided. In this embodiment, a plurality of nanoparticles is also provided. The nanoparticles include a catalyst material coupled to one or more ligands, and these nanoparticles are disposed within respective recesses of the substrate. In some embodiments, the substrate is processed to form nanostructures, such as nanotubes or nanowires, within the recesses. Devices and systems having such nanostructures are also disclosed.

Abstract: A graphene substrate is doped with one or more functional groups to form an electronic device.

Abstract: The invention relates to a device which makes it possible to establish a horizontal electrical connection between at least two bonding pads. This device comprises horizontal carbon nanotubes which link the vertical walls of said bonding pads and the bonding pads are made by stacking layers of at least two materials, one of which catalyzes growth of the nanotubes and the other of which acts as a spacer between the layers of material which catalyzes growth of the nanotubes.

Abstract: A light emitting chip includes a substrate, an epitaxial structure comprising a first semiconductor layer, a light emitting layer and a second semiconductor layer, a current conducting structure formed on a bottom side of the first semiconductor layer of the epitaxial structure, and heat conducting protrusions formed on a top side of the substrate. Each of the heat conducting protrusions includes a carbon nanotube layer vertically grown thereon. The heat conducting protrusions are embedded into the current conducting structure to thermally connect with the first semiconductor layer. A method for manufacturing the light emitting chip is also disclosed.

Abstract: Electronic devices having carbon-based materials and techniques for making contact to carbon-based materials in electronic devices are provided. In one aspect, a device is provided having a carbon-based material; and at least one electrical contact to the carbon-based material comprising a metal silicide, germanide or germanosilicide. The carbon-based material can include graphene or carbon nano-tubes. The device can further include a segregation region, having an impurity, separating the carbon-based material from the metal silicide, germanide or germanosilicide, wherein the impurity has a work function that is different from a work function of the metal silicide, germanide or germanosilicide. A method for fabricating the device is also provided.

Abstract: A method for manufacturing a biosensor includes forming a silicon nanowire channel, etching a first conductivity-type single crystalline silicon layer which is a top layer of a Silicon-On-Insulator (SOI) substrate to form a first conductivity-type single crystalline silicon line pattern, doping both sidewalls of the first conductivity-type single crystalline silicon line pattern with impurities of a second conductivity-type opposite to the first conductivity-type to form a second conductivity-type channel, forming second conductivity-type pads for forming electrodes at both ends of the first conductivity-type single crystalline silicon line pattern, forming, in an undoped region of the first conductivity-type single crystalline silicon line pattern, a first electrode for applying a reverse-bias voltage to insulate the first conductivity-type single crystalline silicon line pattern and the second conductivity-type channel from each other, and forming second electrodes for applying a bias voltage across the sec

Abstract: An exemplary image sensor package includes a base substrate, an image sensor, and a number of wires. The base substrate contains carbon nanotubes and alumina, and includes a number of base pads. The image sensor is mounted on the base substrate, and includes a sensing portion and a number of contacts. The wires electrically connect the base pads to the respective contacts.

Abstract: A method comprises applying a first electric field pulse to a nanowire comprising a channel and a charge trapping region configured to control conductivity of the channel, the first electric field pulse having a first polarity and a relatively large magnitude of integral of electric field during the pulse and, thereafter, applying at least one further electric field pulse to the nanowire, each further electric pulse having a second, opposite polarity and each respective further electric field pulse having a relatively small magnitude of integral of electric field during the pulse.

Abstract: The present disclosure provides a thin film transistor which includes a source electrode, a drain electrode, a semiconducting layer, an insulating layer and a gate electrode. The drain electrode is spaced apart from the source electrode. The semiconducting layer is electrically connected with the source electrode and the drain electrode. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconducting layer by the insulating layer. At least one of the gate electrode, the drain electrode, the source electrode includes a carbon nanotube composite layer.

Abstract: Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the carbon nanotube, forming a reverse biased junction of a hole-induced region and an electron-induced region of the carbon nanotube, or electrically biasing a region through a dielectric layer between two device regions of the carbon nanotube. The carbon nanotubes may be arranged such that hole-inducing material layer and electron-inducing material layer may be assigned to each carbon nanotube to form periodic structures such as a static random access memory (SRAM) array.

Abstract: A simplified method for fabricating a solar cell device is provided. The solar cell device has silicon nanowires (SiNW) grown on an upgraded metallurgical grade (UMG) silicon (Si) substrate. Processes of textured surface process and anti-reflection thin film process can be left out for further saving costs on equipment and manufacture investment. Thus, a low-cost Si-based solar cell device can be easily fabricated for wide application.

Abstract: The present invention provides for nanostructures grown on a conducting or insulating substrate, and a method of making the same. The nanostructures grown according to the claimed method are suitable for interconnects and/or as heat dissipators in electronic devices.

Abstract: In a semiconductor device, a through hole via extending through the substrate of the device may be formed on the basis of a carbon-containing material, thereby providing excellent compatibility with high temperature processes, while also providing superior electrical performance compared to doped semiconductor materials and the like. Thus, in some illustrative embodiments, the through hole vias may be formed prior to any process steps used for forming critical circuit elements, thereby substantially avoiding any interference of the through hole via structure with a device level of the corresponding semiconductor device. Consequently, highly efficient three-dimensional integration schemes may be realized.

Abstract: Embodiments of nanoelectronic sensors are described, including sensors for detecting analytes inorganic gases, organic vapors, biomolecules, viruses and the like. A number of embodiments of capacitive sensors having alternative architectures are described. Particular examples include integrated cell membranes and membrane-like structures in nanoelectronic sensors.

Abstract: The present invention proposes a method of readily and reliably forming CNTs independent of a substrate allowing a catalyst metal to deposit thereon, or an underlying material, even for the case where the substrate is not used, in which a titanium-cobalt composite particles are deposited, using a catalyst particle production system, on an insulating film formed on a silicon substrate, and CNTs are grown from the from titanium-cobalt composite particles by the CVD process.

Abstract: Disclosed are a biosensor, a method of producing the same, and a method of detecting a biomaterial through the biosensor. The biosensor includes a substrate, an insulating layer, source and drain electrodes formed on the insulating layer, a middle-discontinuous channel provided between the source and drain electrodes, and a detection area on which a detection target material is to be fixed, covering the middle-discontinuous channel.

Abstract: A method for making a liquid crystal display screen includes the steps of: providing a base comprising a surface; manufacturing a substrate, wherein manufacturing a substrate comprises: placing a carbon nanotube layer on the surface of the base, the carbon nanotube layer comprising a plurality of carbon nanotubes substantially aligned along a same direction; applying a fixing layer on a surface of the carbon nanotube layer, thereby obtaining a first substrate; and supplying a liquid crystal layer, wherein the carbon nanotubes of a first substrate are arranged perpendicular to that of a second substrate.

Abstract: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.

Abstract: A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire on a semiconductor substrate, forming a first gate structure on a first portion of the nanowire, forming a first protective spacer adjacent to sidewalls of the first gate structure and over portions of the nanowire extending from the first gate structure, removing exposed portions of the nanowire left unprotected by the first spacer, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a first source region and a first drain region.

Abstract: An integrated circuit device of the present invention includes a substrate on which at least two types of nano wire element are provided. These nano wire elements have functions and materials different from each other. The nano wire elements are constituted by nano wires having sizes differing depending on types of nano wire element. With this, it is possible to dramatically improve a function of the integrated circuit device, as compared with an integrated circuit device including a substrate on which one type of nano wire element is provided.

Abstract: A method for transferring a nano material formed on a first substrate through deposition techniques to a second substrate, includes: (A) contacting the second substrate with a free end of the nano material on the first substrate; (B) heating the first substrate so that heat is conducted substantially from the first substrate through the nano material to the second substrate to soften a contact portion of a surface of the second substrate that is in contact with the free end of the nano material; (C) after step (B), cooling the second substrate so as to permit hardening of the contact portion of the surface of the second substrate and solid bonding of the nano material to the second substrate; and (D) after step (C), removing the first substrate from the nano material.

Abstract: In an array R of field-effect transistors for detecting analytes, each transistor of the array comprises a gate G, a semiconductor nanotube or nanowire element NT connected at one end to a source electrode S and at another end to a drain electrode D, in order to form, at each end, a junction J1, J2 with the channel. At least transistors FET1,1, FET1,2 of the array are differentiated by a different conducting material (m1, m2) of the source electrode S and/or drain electrode D.

Abstract: Carbon nanotube template arrays may be edited to form connections between proximate nanotubes and/or to delete undesired nanotubes or nanotube junctions.

Abstract: A carbon nanotube based memory device comprises a set of three concentric carbon nanotubes having different diameters. The diameters of the three concentric carbon nanotubes are selected such that an inner carbon nanotube is semiconducting, and intershell electron transport occurs between adjacent carbon nanotubes. Source and drain contacts are made to the inner carbon nanotube, and a gate contact is made to the outer carbon nanotube. The carbon nanotube based memory device is programmed by storing electrons or holes in the middle carbon nanotube through intershell electron transport. Changes in conductance of the inner carbon nanotube due to the charge in the middle shell are detected to determine the charge state of the middle carbon nanotube. Thus, the carbon nanotube based memory device stores information in the middle carbon nanotube in the form of electrical charge.

Abstract: Graded artificial dielectrics using nanostructures, such as nanowires, are disclosed. The graded artificial dielectric includes a material (typically a dielectric) with a plurality of nanostructures, such as nanowires, embedded within the dielectric material. One or more characteristics of the nanostructures are spatially varied from a first region within the dielectric to a second region within the dielectric to produce permittivity of the graded artificial dielectric that is spatially varied. The characteristics that can be varied include, but are not limited to, nanostructure density, nanostructure length, nanostructure aspect ratio, nanostructure oxide ratio, and nanostructure alignment. Methods of producing graded artificial dielectrics are also provided. A wide range of electronic devices such as antennas can use graded artificial dielectrics with nanostructures to improve performance.

Abstract: The present invention provides a method for manufacturing a semiconductor nanowire device in mass production at a low cost without an additional complex nanowire alignment process or SOI substrate by forming a single crystal silicon nanowire with a simple process without forming an ultra fine pattern using an electron beam and transferring the nanowire separated from the substrate to another oxidation layer or insulation substrate. And also, the present invention suggests a method for simply manufacturing a nanowire device transferring the nanowire from a semiconductor substrate formed thereon the nanowire to another substrate formed thereon an insulation layer or the like.

Abstract: After a titanium nitride (TiN) thin film is formed on a silicon substrate, cobalt (Co) fine particles and nickel (Ni) fine particles are deposited in a mixed state on the titanium nitride (TiN) thin film, and CNTs are sequentially grown from the cobalt (Co) fine particles and the nickel fine particles by varying growth conditions.

Abstract: A multi-terminal electromechanical nanoscopic switching device which may be used as a memory device, a pass gate, a transmission gate, or a multiplexer, among other things.

Abstract: A silicon/carbon alloy may be formed in drain and source regions, wherein another portion may be provided as an in situ doped material with a reduced offset with respect to the gate electrode material. For this purpose, in one illustrative embodiment, a cyclic epitaxial growth process including a plurality of growth/etch cycles may be used at low temperatures in an ultra-high vacuum ambient, thereby obtaining a substantially bottom to top fill behavior.

Abstract: A method of producing silicon nanowires includes providing a substrate in the form of a doped material; formulating an etching solution; and applying an appropriate current density for an appropriate length of time. Related structures and devices composed at least in part from silicon nanowires are also described.