Abstract: A thin film transistor includes a multi-coaxial silicon nanowire unit including a plurality of coaxial silicon nanowires on a substrate, the multi-coaxial silicon nanowire unit including a central portion and end portions of the central portion; a gate electrode on the central portion; and a source electrode and a drain electrode on the respective end portions, respectively, so as to electrically connect to the multi-coaxial silicon nanowire unit.

Abstract: The present invention relates to a process for producing a carbon nanotube (CNT) mat on a conductive or semiconductor substrate. According to this process, a catalytic complex comprising at least one metal layer is firstly deposited on said substrate. Said metal layer then undergoes an oxidizing treatment. Finally, carbon nanotubes are grown from the metal layer thus oxidized. The present invention also relates to a process for producing a via using said CNT mat production process.

Abstract: Methods and devices for manufacturing carbon nanotube based field effect transistors are disclosed including providing a substrate; printing a gate electrode layer onto the substrate and sintering and/or UV curing; printing a gate isolation layer onto the gate electrode and air drying and/or UV curing; printing one or more carbon nanotube channel layers onto the gate isolation layer, wherein each carbon nanotube channel layer is air dried prior to subsequent printings; and printing a source and drain electrode layer onto the one or more carbon nanotube channel layers and sintering and/or UV curing. Other embodiments are described and claimed.

Abstract: In accordance with various embodiments, an organic electronic device includes an n-type dopant material including an imidazole-based material having a hydrogen-based material bonded between nitrogen atoms. The n-type dopant material n-dopes an organic material, and can be used to mitigate degradation in mobility due to conditions such as exposure to ambient atmosphere, which can effect an undesirable reduction in charge transport. Other embodiments are directed to carbon nanotubes or graphene structures with this type of n-type dopant, wherein the Fermi level for the carbon nanotubes or graphene structures is below ?2.5 eV to effect such n-type doping.

Abstract: A fluid transport method and fluid transport device are disclosed. Nanoscale fibers disposed in a patterned configuration allow transport of a fluid in absence of an external power source. The device may include two or more fluid transport components having different fluid transport efficiencies. The components may be separated by additional fluid transport components, to control fluid flow.

Abstract: The disclosure pertains to a method for making a nanoscale filed effect transistor structure on a semiconductor substrate. The method comprises disposing a mask on a semiconductor upper layer of a multi-layer substrate, and removing areas of the upper layer not covered by the mask in a nanowire lithography process. The mask includes two conductive terminals separated by a distance, and a nanowire in contact with the conductive terminals across the distance. The nanowire lithography may be carried out using a deep-reactive-ion-etching, which results in an integration of the nanowire mask and the underlying semiconductor layer to form a nanoscale semiconductor channel for the field effect transistor.

Abstract: Provided are a biosensor with a silicon nanowire and a method of manufacturing the same, and more particularly, a biosensor with a silicon nanowire including a defect region formed by irradiation of an electron beam, and a method of manufacturing the same. The biosensor includes: a silicon substrate; a source region disposed on the silicon substrate; a drain region disposed on the silicon substrate; and a silicon nanowire disposed on the source region and the drain region, and having a defect region formed by irradiation of an electron beam. Therefore, by irradiating a certain region of a high-concentration doped silicon nanowire with an electron beam to lower electron mobility in the certain region, it is possible to maintain a low contact resistance between the silicon nanowire and a metal electrode and to lower operation current of a biomaterial detection part, thereby improving sensitivity of the biosensor.

Abstract: Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the carbon nanotube, forming a reverse biased junction of a hole-induced region and an electron-induced region of the carbon nanotube, or electrically biasing a region through a dielectric layer between two device regions of the carbon nanotube. The carbon nanotubes may be arranged such that hole-inducing material layer and electron-inducing material layer may be assigned to each carbon nanotube to form periodic structures such as a static random access memory (SRAM) array.

Abstract: A multiple die structure includes a first die (110), a second die (120), a carbon nanotube (130) having a first end (131) in physical contact with the first die and having a second end (132) in physical contact with the second die, and an electrically conductive material (240) in physical contact with the first end of the carbon nanotube and in physical contact with the first die. Forming a connection between the first die and the second die can include providing a connection structure (400, 500, 600, 900) in which the electrically conductive material is adjacent to the carbon nanotube, placing the connection structure adjacent to the first die and to the second die, and bonding the first die and the second die to the connection structure.

Abstract: Provided is a method for manufacturing a field emission array with a carbon microstructure. The method includes: a photomask attachment step of attaching a photomask with a pattern groove to one surface of a transparent substrate; a photoresist attachment step of attaching a negative photoresist to one surface of the photomask; an exposure step of irradiating light toward the opposite surface of the transparent substrate from the photomask to cure a portion of the negative photoresist with the light irradiated on the negative photoresist through the pattern groove; a developing step of removing an uncured portion of the negative photoresist while leaving the cured portion of the negative photoresist as a microstructure; a pyrolysis step of heating and carbonizing the microstructure thus obtained; and a cathode attachment step of attaching a voltage-supplying cathode to the surface of the transparent substrate on which the microstructure is formed.

Abstract: A microarray apparatus is provided which contains at least one chip having source and drain electrodes positioned on an array of carbon nanotube transistors which allows for electronic detection of nucleic acid hybridizations, thereby affording both increased sensitivity and the capability of miniaturization.

Abstract: A switching element comprises a source electrode, a drain electrode arranged apart from the source electrode, an active layer in contact with the electrodes, and a gate electrode arranged apart from the source and drain electrodes and being in contact with the active layer with a gate insulating layer interposed therebetween. The active layer is formed of a dispersion film containing predetermined carbon nanotubes and a predetermined polyether compound.

Abstract: A composite of a base and an array of needle-like crystals formed on the surface of the base is provided, in which the base side and the opposite side to the base with respect to the array can be isolated in a satisfactory manner. A composite 10 includes a transparent electrode 2 serving as the base, an array 4 of needle-like crystals 3 formed thereon, and a coating film 15 covering the surface of the needle-like crystals 3. The needle-like crystals 3 are made of, for example, zinc oxide, and the coating film 15 contains, for example, titanium oxide. The array 4 includes a first region R1 on the transparent electrode 2 side and a second region R2 on the opposite side to the transparent electrode 2 with respect to the first region R1.

Abstract: The present invention relates to a new light emitters that exploit the use of semiconducting single walled carbon nanotubes (SWNTs). Experimental evidences are given on how it is possible, within the standard silicon technology, to devise light emitting diodes (LEDs) emitting in the infrared IR where light emission results from a radiative recombination of electron and holes on semiconducting single walled carbon nanotubes (SWNTs-LED). We will also show how it is possible to implement these SWNTs-LED in order to build up a laser source based on the emission properties of SWNTs. A description of the manufacturing process of such devices is also given.

Abstract: In accordance with some embodiments, logical circuits comprising carbon nanotube field effect transistors are disclosed herein.

Abstract: Carbon nanotube template arrays may be edited to form connections between proximate nanotubes and/or to delete undesired nanotubes or nanotube junctions.

Abstract: A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least two sublayers of oriented carbon nanotubes. A first sublayer is created by growing carbon nanotubes in a first direction parallel to the chip substrate from a catalyst in the presence of a reactant gas flow in the first direction, and a second sublayer is created by growing carbon nanotubes in a second direction parallel to the substrate and different from the first direction from a catalyst in the presence of a reactant gas flow in the second direction. The first and second directions are preferably substantially perpendicular. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal.

Abstract: A semiconductor nanowire having two semiconductor pads on both ends is suspended over a substrate. Stress-generating liner portions are formed over the two semiconductor pads, while a middle portion of the semiconductor nanowire is exposed. A gate dielectric and a gate electrode are formed over the middle portion of the semiconductor nanowire while the semiconductor nanowire is under longitudinal stress due to the stress-generating liner portions. The middle portion of the semiconductor nanowire is under a built-in inherent longitudinal stress after removal of the stress-generating liners because the formation of the gate dielectric and the gate electrode locks in the strained state of the semiconductor nanowire. Source and drain regions are formed in the semiconductor pads to provide a semiconductor nanowire transistor. A middle-of-line (MOL) dielectric layer may be formed directly on the source and drain pads.

Abstract: A method of forming a plurality of nanotubes is disclosed. Particularly, a substrate may be provided and a plurality of recesses may be formed therein. Further, a plurality of nanotubes may be formed generally within each of the plurality of recesses and the plurality of nanotubes may be substantially surrounded with a supporting material. Additionally, at least some of the plurality of nanotubes may be selectively shortened and at least a portion of the at least some of the plurality of nanotubes may be functionalized. Methods for forming semiconductor structures intermediate structures, and semiconductor devices are disclosed. An intermediate structure, intermediate semiconductor structure, and a system including nanotube structures are also disclosed.

Abstract: A method for making a liquid crystal display screen includes the following steps. Firstly, providing a base including a surface. Secondly, forming carbon nanotube structure on the surface of the base to obtain a first electrode plate preform, the carbon nanotubes of each carbon nanotube structure being oriented along the extending direction thereof. Thirdly, forming a fixing layer to cover the carbon nanotube structure, thereby obtaining a first electrode plate. Fourthly, repeating the above-described steps, thereby obtaining a second electrode plate. Lastly, forming a liquid crystal layer between the fixing layers of the first electrode plate and the second electrode plate, the carbon nanotubes of the first electrode plate being perpendicular to that of the second electrode plate, thereby forming the liquid crystal display screen.

Abstract: The present invention provides the multifunctional biological and biochemical sensor technology based on the integration of ZnO nanotips with bulk acoustic wave (BAW) devices, particularly, quartz crystal microbalance (QCM) and thin film bulk acoustic wave resonator (TFBAR). ZnO nanotips provide giant effective surface area and strong bonding sites. Furthermore, the controllable wettability of ZnO nanostructured surface dramatically reduces the liquid consumption and enhances the sensitivity of the biosensor device.

Abstract: An anthrylarylene derivative having a specific structure and an organic electroluminescence device comprising an organic thin film layer which comprises at least one layer comprising at least a light emitting layer and is disposed between a cathode and an anode, wherein at least one layer in the organic thin film layer comprises the anthrylarylene derivative singly or as a component of a mixture. The device exhibits a great efficiency of light emission and has a long life. The anthrylarylene derivative has a sufficient glass transition temperature and is greatly advantageous as the light emitting material used in the above organic electroluminescence device.

Abstract: A device includes an insulating layer on a substrate having a lower conductive pattern, the insulating layer having a contact hole that penetrates the insulating layer and exposes a portion of the lower conductive pattern, a catalytic pattern having a first portion on the exposed portion of the lower conductive pattern and a second portion on a sidewall of the contact hole, a spacer on the sidewall of the contact hole, wherein the second portion of the catalytic pattern is disposed between the spacer and the sidewall, and a contact plug in the contact hole and contacting the catalytic pattern, the contact plug being a carbon nanotube material.

Abstract: Disclosed are a semiconductor device and a manufacturing method thereof. The semiconductor device can include a recess formed in an active area of a semiconductor substrate, an insulating layer formed in the recess, a source electrode and a drain electrode spaced apart from the source electrode on the insulating layer, a carbon nanotube layer formed between the source and drain electrodes, an oxide layer pattern covering at least the carbon nanotube layer, and a gate electrode formed on the oxide layer pattern.

Abstract: The present invention provides for an array of nanostructures grown on a conducting substrate. The array of nanostructures as provided herein is suitable for manufacturing electronic devices such as an electron beam writer, and a field emission device.

Abstract: A carbon nanotube device in accordance with the invention includes a free-standing membrane that is peripherally supported by a support structure. The membrane includes an aperture that extends through a thickness of the membrane. At least one carbon nanotube extends across the aperture on a front surface of the membrane. The carbon nanotube is also accessible from a back surface of the membrane.

Abstract: A thin film device and compound having an anode, a cathode, and at least one light emitting layer between the anode and cathode, the at least one light emitting layer having at least one carbon nanotube and a conductive polymer.

Abstract: A method for making a thin film transistor, the method comprising the steps of: (a) providing a carbon nanotube array and an insulating substrate; (b) pulling out a carbon nanotube film from the carbon nanotube array by using a tool; (c) placing at least one carbon nanotube film on a surface of the insulating substrate, to form a carbon nanotube layer thereon; (d) forming a source electrode and a drain electrode; wherein the source electrode and the drain electrode being spaced therebetween, and electrically connected to the carbon nanotube layer; and (e) covering the carbon nanotube layer with an insulating layer, and a gate electrode being located on the insulating layer.

Abstract: A semiconductor device uses a carbon nanotube structure, which reduces an electric resistance and a thermal resistance by increasing a density of the carbon nanotubes. An insulation film covers a first electrically conductive material. A second electrically conductive material is provided on the insulation film. A plurality of carbon nanotubes extend through the insulation film by being filled in an opening part that exposes the first electrically conductive material. The carbon nanotubes electrically connect the first electrically conductive material and the second electrically conductive material to each other. Ends of the carbon nanotubes are fixed to a recessed part provided on a surface of the first electrically conductive material.

Abstract: A single-electron transistor comprising at least a substrate, a source electrode and a drain electrode formed on top of the substrate opposing to each other, and a channel arranged between the source electrode is disclosed wherein the channel is composed of ultra fine fibers. By having such a constitution, a sensor can have excellent sensitivity.

Abstract: A trench-type storage device includes a trench in a substrate (100), with bundles of carbon nanotubes (202) lining the trench and a trench conductor (300) filling the trench. A trench dielectric (200) may be formed between the carbon nanotubes and the sidewall of the trench. The bundles of carbon nanotubes form an open cylinder structure lining the trench. The device is formed by providing a carbon nanotube catalyst structure on the substrate and patterning the trench in the substrate; the carbon nanotubes are then grown down into the trench to line the trench with the carbon nanotube bundles, after which the trench is filled with the trench conductor.

Abstract: A stress-engineered microspring is formed generally in the plane of a substrate. A nanowire (or equivalently, a nanotube) is formed at the tip thereof, also in the plane of the substrate. Once formed, the length of the nanowire may be defined, for example photolithographically. A sacrificial layer underlying the microspring may then be removed, allowing the engineered stresses in the microspring to cause the structure to bend out of plane, elevating the nanowire off the substrate and out of plane. Use of the nanowire as a contact is thereby provided. The nanowire may be clamped at the tip of the microspring for added robustness. The nanowire may be coated during the formation process to provide additional functionality of the final device.

Abstract: A disclosed selective etching method comprises mixing a polymer with carbon nanotubes, applying the mixture to an etching target layer to form a carbon nanotube-polymer composite layer, forming a hard mask by patterning the carbon nanotube-polymer composite layer, such that a part of the etching target layer is selectively exposed, and selectively etching the etching target layer exposed through the hard mask. The polymer preferably includes a photoresist. Also disclosed is a method for forming an isolation structure of a memory device using the selective etching method.

Abstract: Under one aspect, non-volatile transistor device includes a source and drain with a channel in between; a gate structure made of a semiconductive or conductive material disposed over an insulator over the channel; a control gate made of a semiconductive or conductive material; and an electromechanically-deflectable nanotube switching element in fixed contact with one of the gate structure and the control gate structure and is not in fixed contact with the other of the gate structure and the control gate structure. The device has a network of inherent capacitances, including an inherent capacitance of an undeflected nanotube switching element in relation to the gate structure. The network is such that the nanotube switching element is deflectable into contact with the other of the gate structure and the control gate structure in response to signals being applied to the control gate and one of the source region and drain region.

Abstract: A capacitor having a first electrode made of an electroconductive nano-wire, a dielectric layer partly covering the peripheral face of the first electrode, and a second electrode covering the peripheral face of the dielectric layer. In a circuit device employing the capacitor, a plurality of the capacitors are arranged roughly perpendicularly to a substrate in the circuit device or in parallel to a substrate in the circuit device.

Abstract: A semiconductor nanowire having two semiconductor pads on both ends is suspended over a substrate. Stress-generating liner portions are formed over the two semiconductor pads, while a middle portion of the semiconductor nanowire is exposed. A gate dielectric and a gate electrode are formed over the middle portion of the semiconductor nanowire while the semiconductor nanowire is under longitudinal stress due to the stress-generating liner portions. The middle portion of the semiconductor nanowire is under a built-in inherent longitudinal stress after removal of the stress-generating liners because the formation of the gate dielectric and the gate electrode locks in the strained state of the semiconductor nanowire. Source and drain regions are formed in the semiconductor pads to provide a semiconductor nanowire transistor. A middle-of-line (MOL) dielectric layer may be formed directly on the source and drain pads.

Abstract: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.

Abstract: A device and method associated with carbon nanowires, such as single walled carbon nanowires having a high degree of alignment are set forth herein. A catalyst layer is deposited having a predetermined crystallographic configuration so as to control a growth parameter, such as an alignment direction, a diameter, a crystallinity and the like of the carbon nanowire. The catalyst layer is etched to expose a sidewall portion. The carbon nanowire is nucleated from the exposed sidewall portion. An electrical circuit device can include a single crystal substrate, such as Silicon, and a crystallographically oriented catalyst layer on the substrate having an exposed sidewall portion. In the device, carbon nanowires are disposed on the single crystal substrate aligned in a direction associated with the crystallographic properties of the catalyst layer.

Abstract: Diodes and method of fabricating diodes. A diode includes: an p-type single wall carbon nanotube; an n-type single wall carbon nanotube, the p-type single wall carbon nanotube in physical and electrical contact with the n-type single wall carbon nanotube; and a first metal pad in physical and electrical contact with the p-type single wall carbon nanotube and a second metal pad in physical and electrical contact with the n-type single wall carbon nanotube.

Abstract: A method for preparation of carbon nanotubes (CNTs) bundles for use in field emission devices (FEDs) includes forming a plurality of carbon nanotubes on a substrate, contacting the carbon nanotubes with a polymer composition comprising a polymer and a solvent, and removing at least a portion of the solvent so as to form a solid composition from the carbon nanotubes and the polymer to form a carbon nanotube bundle having a base with a periphery, and an elevated central region where, along the periphery of the base, the carbon nanotubes slope toward the central region.

Abstract: Provided is a field effect transistor having an organic semiconductor layer, in which crystal grains having a maximum diameter of 10 ?m or more account for 25% or more of the surface area of the organic semiconductor layer. The organic semiconductor layer preferably contains 7 to 200 crystal grains having a maximum diameter of 10 ?m or more per 0.01 mm2. The organic semiconductor layer preferably contains a porphyrin crystal.

Abstract: A method of forming a microelectronic device includes forming a groove structure having opposing sidewalls and a surface therebetween on a substrate to define a nano line arrangement region. The nano line arrangement region has a predetermined width and a predetermined length greater than the width. At least one nano line is formed in the nano line arrangement region extending substantially along the length thereof and coupled to the surface of the groove structure to define a nano line structure. Related devices are also discussed.

Abstract: The present polymer composite p-n junction includes an n-type polymer composite layer and a p-type polymer composite layer. The n-type composite polymer layer includes a first polymer material and a number of electrically conductive particles imbedded therein. The p-type composite polymer layer includes a second polymer material and a number of carbon nanotubes (CNTs) imbedded therein. A method for manufacturing the polymer composite p-n junction and a polymer composite diode incorporating the polymer composite p-n junction are also provided.

Abstract: A method of forming an aligned connection between a nanotube layer and a raised feature is disclosed. A substrate having a raised feature has spacers formed next to the side of the raised feature. The spacers are etched until the sidewalls of the raised feature are exposed forming a notched feature at the top of the spacers. A patterned nanotube layer is formed such that the nanotube layer overlies the top of the spacer and contacts a side portion of the raised feature in the notched feature. The nanotube layer is then covered with an insulating layer. Then a top portion of the insulating layer is removed to expose a top portion of the etched feature.

Abstract: A nonvolatile organic bistable memory device includes a substrate, a lower electrode disposed on the substrate, a lower charge injection layer disposed on the lower electrode, an insulating polymer layer including nanoparticles disposed on the lower charge injection layer, an upper charge injection layer disposed on the insulating polymer layer, and an upper electrode disposed on the upper charge injection layer. The lower and upper charge injection layers each include fullerenes and/or carbon nanotubes.

Abstract: Carbon nanotube template arrays may be edited to form connections between proximate nanotubes and/or to delete undesired nanotubes or nanotube junctions.

Abstract: Nanotube and metal composite interconnects are generally described. In one example, an apparatus includes an interlayer dielectric (ILD) and one or more interconnect structures coupled to the ILD, the one or more interconnect structures including a composite of metal and one or more nanotubes.

Abstract: Composition of carbon nanotubes (CNTs) are produced into inks that are dispensable via ink jet or other deposition processes. The CNT ink is dispensed into wells and allowed to dry so as to formed a cathode structure. It is important to note that after the CNT ink is deposited to form a cathode structure, no further post-deposition processes are performed, such as the removal of sacrificial layers, which could damage the CNT ink.

Abstract: A method of forming a single wall thickness (SWT) carbon nanotube (CNT) transistor with a controlled diameter and chirality is disclosed. A photolithographically defined single crystal silicon seed layer is converted to a single crystal silicon carbide seed layer. A single layer of graphene is formed on the top surface of the silicon carbide. The SWT CNT transistor body is grown from the graphene layer in the presence of carbon containing gases and metal catalyst atoms. Silicided source and drain regions at each end of the silicon carbide seed layer provide catalyst metal atoms during formation of the CNT. The diameter of the SWT CNT is established by the width of the patterned seed layer. A conformally deposited gate dielectric layer and a transistor gate over the gate dielectric layer complete the CNT transistor. CNT transistors with multiple CNT bodies, split gates and varying diameters are also disclosed.

Abstract: A nonvolatile carbon nanotube memory device using multiwall carbon nanotubes and methods of operating and fabricating the same are provided. The nonvolatile memory device may include a substrate, at least one first electrode on the substrate, first and second vertical walls on the at least one first electrode spaced from each other, a multiwall carbon nanotube on the at least one first electrode between the first and second vertical walls, second and third electrodes on the first and second vertical walls respectively and at least one fourth electrode spaced a variable distance D (where D?0) from the multiwall carbon nanotubes.