Abstract: The invented ink-jet printing method for the construction of thin film transistors using all SWNTs on flexible plastic films is a new process. This method is more practical than all of existing printing methods in the construction TFT and RFID tags because SWNTs have superior properties of both electrical and mechanical over organic conducting oligomers and polymers which often used for TFT. Furthermore, this method can be applied on thin films such as paper and plastic films while silicon based techniques can not used on such flexible films. These are superior to the traditional conducting polymers used in printable devices since they need no dopant and they are more stable. They could be used in conjunction with conducting polymers, or as stand-alone inks.

Abstract: An RF nanoswitch which can reduce a loss in RF signal. The RF nanoswitch includes a first electrode unit connected to one terminal of a driving power supply, a second electrode connected to the other terminal of the driving power supply, and a dielectric material selectively coming into contact with at least one of the first electrode unit and the second electrode, depending on whether or not power is applied from the driving power supply.

Abstract: Carbon nanotube template arrays may be edited to form connections between proximate nanotubes and/or to delete undesired nanotubes or nanotube junctions.

Abstract: The present invention is directed to systems and methods for nanowire growth and harvesting. In an embodiment, methods for nanowire growth and doping are provided, including methods for epitaxial oriented nanowire growth using a combination of silicon precursors, as well as us of patterned substrates to grow oriented nanowires. In a further aspect of the invention, methods to improve nanowire quality through the use of sacrificial growth layers are provided. In another aspect of the invention, methods for transferring nanowires from one substrate to another substrate are provided.

Abstract: Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the carbon nanotube, forming a reverse biased junction of a hole-induced region and an electron-induced region of the carbon nanotube, or electrically biasing a region through a dielectric layer between two device regions of the carbon nanotube. The carbon nanotubes may be arranged such that hole-inducing material layer and electron-inducing material layer may be assigned to each carbon nanotube to form periodic structures such as a static random access memory (SRAM) array.

Abstract: Carbon nanotube template arrays may be edited to form connections between proximate nanotubes and/or to delete undesired nanotubes or nanotube junctions.

Abstract: A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of the other layer. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal. In one embodiment, oriented carbon nanotubes are created by forming a series of parallel surface ridges, covering the top and one side of the ridges with a catalyst inhibitor, and growing carbon nanotubes horizontally from the uncovered vertical sides of the ridges. In another embodiment, oriented carbon nanotubes are grown on the surface of a conductive material in the presence of a directional flow of reactant gases and a catalyst.

Abstract: A semiconductor device and associated method for forming. The semiconductor device comprises an electrically conductive nanotube formed over a first electrically conductive member such that a first gap exists between a bottom side the electrically conductive nanotube and a top side of the first electrically conductive member. A second insulating layer is formed over the electrically conductive nanotube. A second gap exists between a top side of the electrically conductive nanotube and a first portion of the second insulating layer. A first via opening and a second via opening each extend through the second insulating layer and into the second gap.

Abstract: A molecular structure. In one embodiment, the molecular structure includes a nanotube formed with a plurality of carbon atoms having a first end, an opposite, second end, and a body portion defined therebetween, wherein the body portion has an interior surface defining a cavity, an opposite, exterior surface and a longitudinal axis therethrough the cavity, and a porphyrin molecule having a plurality of carbon atoms and a first plurality of hydrogen atoms, wherein at its original state the porphyrin molecule has a plurality of pyrrole units and each pyrrole unit is coupled to another pyrrole unit through a methine bridge so as to form a ring structure with a second plurality of hydrogen atoms positioned peripherally along the ring structure. The porphyrin molecule is chemically coupled to the interior surface of the nanotube such that at least one of the second plurality of hydrogen atoms positioned peripherally along the ring structure is replaced by a carbon atom of the nanotube.

Abstract: The present invention provides for nanostructures grown on a conducting or insulating substrate, and a method of making the same. The nanostructures grown according to the claimed method are suitable for interconnects and/or as heat dissipators in electronic devices.

Abstract: A semiconductor device has lateral conductors or traces that are formed of nanotubes such as carbon. A sacrificial layer is formed overlying the substrate. A dielectric layer is formed overlying the sacrificial layer. A lateral opening is formed by removing a portion of the dielectric layer and the sacrificial layer which is located between two columns of metallic catalysts. The lateral opening includes a neck portion and a cavity portion which is used as a constrained space to grow a nanotube. A plasma is used to apply electric charge that forms an electric field which controls the direction of formation of the nanotubes. Nanotubes from each column of metallic catalyst are laterally grown and either abut or merge into one nanotube. Contact to the nanotube may be made from either the neck portion or the columns of metallic catalysts.

Abstract: A nano-electrode or nano-wire may be etched centrally to form a gap between nano-electrode portions. The portions may ultimately constitute a single electron transistor. The source and drain formed from the electrode portions are self-aligned with one another. Using spacer technology, the gap between the electrodes may be made very small.

Abstract: A carbon nanotube transistor structure includes a number of carbon nanotubes extending vertically in a substrate material. A drain electrode of the transistor is connected to the carbon nanotubes at a first depth position, and a source electrode for the transistor structure connected to the carbon nanotubes at a second depth position. A gate electrode extends vertically along a side of the nanotubes, between the first and second depth positions. There may be multiple vertical side gate electrodes and multiple carbon nanotubes between these side gate electrodes.

Abstract: The present invention provides for an array of nanostructures grown on a conducting substrate. The array of nanostructures as provided herein is suitable for manufacturing electronic devices such as an electron beam writer, and a field emission device.

Abstract: The present invention relates to an epoxy resin composition for photosemiconductor element encapsulation, the epoxy resin composition including the following components (A) to (D): (A) an epoxy resin having two or more epoxy groups in one molecule thereof, (B) an acid anhydride curing agent, (C) a curing accelerator, and (D) an alcohol compound having three or more primary hydroxyl groups in one molecule thereof.

Abstract: Carbon nanotube apparatus, and methods of carbon nanotube modification, include carbon nanotubes having locally modified properties with the positioning of the modifications being controlled. More specifically, the positioning of nanotubes on a substrate with a deposited substance, and partially vaporizing part of the deposited substance etches the nanotubes. The modifications of the carbon nanotubes determine the electrical properties of the apparatus and applications such as a transistor or Shockley diode. Other applications of the above mentioned apparatus include a nanolaboratory that assists in study of merged quantum states between nanosystems and a macroscopic host system.

Abstract: A method for making transmission electron microscope gird is provided. An array of carbon nanotubes is provided and drawing a carbon nanotube film from the array of carbon nanotubes. A substrate has a plurality of spaced metal girds attached on the substrate. The metal girds are covered with the carbon nanotube film and treating the carbon nanotube film and the metal girds with organic solvent. A transmission electron microscope (TEM) grid is obtained by removing remaining CNT film.

Abstract: An image sensor and a method for manufacturing the same are provided. The image sensor can include transistor circuitry on a substrate, and a photodiode arranged above the transistor circuitry. The photodiode can include carbon nanotubes and a conductive polymer layer on the carbon nanotubes. A transparent conducting electrode can be provided on the carbon nanotubes.

Abstract: In accordance with an embodiment of the invention the method of manufacturing a semiconductor device is capable of forming a semiconductor substrate having an embossing structure. The method includes forming a layer having a plurality of hemispherical single crystal silicon elements, and forming one or more carbon nano tubes between adjacent hemispherical single crystal silicon elements, thereby, increasing a length of an effective channel of a transistor.

Abstract: An integrated circuit including a memory cell and methods of manufacturing the integrated circuit are described. The memory cell includes a resistive memory element including a top contact, a bottom contact, and a carbon storage layer disposed between the top contact and the bottom contact. The memory cell operates at a voltage in a range of approximately 0.5V to approximately 3V, and at a current in a range of approximately 1 ?A to approximately 150 ?A.

Abstract: A nanowire electronmechanical device with an improved structure and a method of fabricating the same prevent burning of two nanowires which are switched due to contact with each other while providing stable on-off switching characteristics.

Abstract: A phase change memory cell has a first electrode, a heater, a phase change material, and a second electrode. The heater is over the first electrode, and the heater includes a pillar. The phase change material is around the heater. The second electrode is electrically coupled to the phase change material. In some embodiments, a method includes forming a electrode layer over a substrate, depositing a first layer, providing nanoclusters over the first layer, and etching the first layer. The first layer comprises one of a group consisting of a heater material and a phase change material. The first layer may be etched using the nanocluster defined pattern to form pillars from the first layer.

Abstract: Embodiments of the present invention are generally directed to a method for disposing nanoparticles on a substrate. In one embodiment, a substrate having a plurality of recesses is provided. In this embodiment, a plurality of nanoparticles is also provided. The nanoparticles include a catalyst material coupled to one or more ligands, and these nanoparticles are disposed within respective recesses of the substrate. In some embodiments, the substrate is processed to form nanostructures, such as nanotubes or nanowires, within the recesses. Devices and systems having such nanostructures are also disclosed.

Abstract: In some embodiments of the invention, encapsulated semiconducting nanomaterials are described. In certain embodiments the nanostructures described are semiconducting nanomaterials encapsulated with ordered carbon shells. In some aspects a method for producing encapsulated semiconducting nanomaterials is disclosed. In some embodiments applications of encapsulated semiconducting nanomaterials are described.

Abstract: Field effect devices having a gate controlled via a nanotube switching element. Under one embodiment, a non-volatile transistor device includes a source region and a drain region of a first semiconductor type of material and each in electrical communication with a respective terminal. A channel region of a second semiconductor type of material is disposed between the source and drain region. A gate structure is disposed over an insulator over the channel region and has a corresponding terminal. A nanotube switching element is responsive to a first control terminal and a second control terminal and is electrically positioned in series between the gate structure and the terminal corresponding to the gate structure. The nanotube switching element is electromechanically operable to one of an open and closed state to thereby open or close an electrical communication path between the gate structure and its corresponding terminal.

Abstract: Carbon nanotube template arrays may be edited to form connections between proximate nanotubes and/or to delete undesired nanotubes or nanotube junctions.

Abstract: The electron device of the present invention has a carbon-based linear structural body including at least one conductive particle, a first electrode and a second electrode disposed at both end of the carbon-based linear structural body, so as to subject the carbon-based linear structural body including at least one conductive particle to connect between the first electrode and the second electrode. A process of manufacturing the electron device includes steps of: forming a carbon-based linear structural body including at least one conductive particle, using a catalyst of a first island and a second island selected from two or more of islands of the catalyst on a substrate; and forming a first electrode and a second electrode so as to connect the first electrode with the first island and one end of the carbon-based linear structural body, and the second electrode with the second island and the other end of the carbon-based linear structural body.

Abstract: The present invention is an object to provide a high-performance vertical field effect transistor having a microminiaturized structure in which the distance between the gate and the channel is made short not through a microfabrication process, having a large gate capacitance, and so elaborated that the gate can control the channel current with a low voltage, and a method for simply and efficiently manufacturing such a field effect transistor not through a complex process such as a microfabrication process.

Abstract: A field effect transistor and a method for making the same. In one embodiment, the field effect transistor comprises a source; a drain; a gate; at least one carbon nanotube on the gate; and a dielectric layer that coats the gate and a portion of the at least one carbon nanotube, wherein the at least one carbon nanotube has an exposed portion that is not coated with the dielectric layer, and wherein the exposed portion is functionalized with at least one indicator molecule. In other embodiments, the field effect transistor is a biochem-FET.

Abstract: Carbon nanotubes may be selectively opened and their exposed ends functionalized. Opposite ends of carbon nanotubes may be functionalized in different fashions to facilitate self-assembly and other applications.

Abstract: A structure and fabrication process for a carbon nanotube field effect transistor is disclosed herein. The structure employs an asymmetric gate which is closer to the source and farther from the drain, which helps to minimize “off current” drain leakage when the drain is biased and the gate is otherwise off. In an embodiment, the source and drain are preferably self aligned to the gate, and preferably the gate is first defined as a conductive sidewall to an etched pad. Dielectric sidewalls are then defined over the gate, which in turn defines the positioning of the source and drain in a predetermined spatial relationship to the gate. In a preferred embodiment, the source and drain comprise conductive sidewalls buttressing the dielectric sidewalls. The channel of the device preferably comprises randomly oriented carbon nanotubes formed on an insulative substrate and isolated from the gate by an insulative layer.

Abstract: The present invention provides for nanostructures grown on a conducting substrate, and a method of making the same. The nanostructures grown according to the claimed method are suitable for manufacturing electronic devices such as an electron beam writer, and a field emission display.

Abstract: A method of forming a single wall thickness (SWT) carbon nanotube (CNT) transistor with a controlled diameter and chirality is disclosed. A photolithographically defined single crystal silicon seed layer is converted to a single crystal silicon carbide seed layer. A single layer of graphene is formed on the top surface of the silicon carbide. The SWT CNT transistor body is grown from the graphene layer in the presence of carbon containing gases and metal catalyst atoms. Silicided source and drain regions at each end of the silicon carbide seed layer provide catalyst metal atoms during formation of the CNT. The diameter of the SWT CNT is established by the width of the patterned seed layer. A conformally deposited gate dielectric layer and a transistor gate over the gate dielectric layer complete the CNT transistor. CNT transistors with multiple CNT bodies, split gates and varying diameters are also disclosed.

Abstract: A device and method associated with carbon nanowires, such as single walled carbon nanowires having a high degree of alignment are set forth herein. A catalyst layer is deposited having a predetermined crystallographic configuration so as to control a growth parameter, such as an alignment direction, a diameter, a crystallinity and the like of the carbon nanowire. The catalyst layer is etched to expose a sidewall portion. The carbon nanowire is nucleated from the exposed sidewall portion. An electrical circuit device can include a single crystal substrate, such as Silicon, and a crystallographically oriented catalyst layer on the substrate having an exposed sidewall portion. In the device, carbon nanowires are disposed on the single crystal substrate aligned in a direction associated with the crystallographic properties of the catalyst layer.

Abstract: The present invention is directed to systems and methods for nanowire growth and harvesting. In an embodiment, methods for nanowire growth and doping are provided, including methods for epitaxial oriented nanowire growth using a combination of silicon precursors. In a further aspect of the invention, methods to improve nanowire quality through the use of sacrificial growth layers are provided. In another aspect of the invention, methods for transferring nanowires from one substrate to another substrate are provided.

Abstract: Carbon nanotube template arrays may be edited to form connections between proximate nanotubes and/or to delete undesired nanotubes or nanotube junctions.

Abstract: Methods for inputting a data-value pattern into a nanowire crossbar, for inputting a data-value pattern into a nanowire crossbar that support computer instructions stored in a computer-readable medium, and for distributing a received data value to each of a set of nanowires that support control logic implemented in logic circuits are provided. First and second nanoscale shift registers are employed, the first having output signal lines that form or interconnect with a first parallel set of nanowire-crossbar nanowires and the second having output signal lines that form or interconnect with a second parallel set of nanowire-crossbar nanowires. A first pattern of values is stored in the first shift register and a second pattern of values is stored in the second shift register using voltage signals below the WRITE voltage for junctions of the crossbar. Voltage signals greater than or equal to the WRITE threshold are applied for junctions of the crossbar to write the pattern of data values into the crossbar.

Abstract: A functional device which is composed of a nanometer-sized functional structure, which can reduce connection resistance in connecting the functional structure to an external electrode, and which includes a wiring section capable of minimizing constraints given to structural designs of various functional structures, and a method of manufacturing it are provided. A functional device in which a functional structure having contained sections in positions spaced from each other is retained by a carbon nanotube. A gap is formed in the carbon nanotube, and the carbon nanotube is segmented into a first carbon nanotube and a second carbon nanotube by the gap. One of the contained sections is contained in the first carbon nanotube at an opening of the first carbon nanotube facing the gap, and the other of the contained sections is contained in the second carbon nanotube at an opening of the second carbon nanotube facing the gap.

Abstract: Faceted catalytic dots are used for directing the growth of carbon nanotubes. In one example, a faceted dot is formed on a substrate for a microelectronic device. A growth promoting dopant is applied to a facet of the dot using an angled implant, and a carbon nanotube is grown on the doped facet of the dot.

Abstract: An RF nanoswitch which can reduce a loss in RF signal. The RF nanoswitch includes a first electrode unit connected to one terminal of a driving power supply, a second electrode connected to the other terminal of the driving power supply, and a dielectric material selectively coming into contact with at least one of the first electrode unit and the second electrode, depending on whether or not power is applied from the driving power supply.

Abstract: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.

Abstract: Carbon nanotube-based devices made by electrolytic deposition and applications thereof are provided. In a preferred embodiment, the present invention provides a device comprising at least one array of active carbon nanotube junctions deposited on at least one microelectronic substrate. In another preferred embodiment, the present invention provides a device comprising a substrate, at least one pair of electrodes disposed on the substrate, wherein one or more pairs of electrodes are connected to a power source, and a bundle of carbon nanotubes disposed between the at least one pair of electrodes wherein the bundle of carbon nanotubes consist essentially of semiconductive carbon nanotubes. In another preferred embodiment, a semiconducting device formed by electrodeposition of carbon nanotubes between two electrodes is provided. The invention also provides preferred methods of forming a semiconductive device by applying a bias voltage to a carbon nanotube rope.

Abstract: A nanowire (100) according to the present invention includes a plurality of contact regions (10a, 10b) and at least one channel region (12), which is connected to the contact regions (10a, 10b). The channel region (12) is made of a first semiconductor material and the surface of the channel region (12) is covered with an insulating layer that has been formed selectively on the channel region (12). The contact regions (10a, 10b) are made of a second semiconductor material, which is different from the first semiconductor material for the channel region (12), and at least the surface of the contact regions (10a, 10b) includes a conductive portion.

Abstract: A step wall is formed over a substrate. Catalytic material of different composition than the step wall is provided proximate thereto. A carbon nanotube is grown from the catalytic material along the step wall generally parallel to the substrate. A method of fabricating integrated circuitry includes forming a step wall over a semiconductor substrate. Catalytic material is provided proximate the step wall. An elevationally outer surface of the catalytic material is masked with a masking material. The catalytic material and the masking material are patterned to form an exposed end sidewall of the catalytic material proximate the step wall, with remaining of the elevationally outer surface of the catalytic material being masked. A carbon nanotube is grown from the exposed end sidewall of the catalytic material along the step wall generally parallel to the semiconductor substrate. The carbon nanotube is incorporated into a circuit component of an integrated circuit.

Abstract: A method can be adapted for design and preparation of a matrix nanocomposite sensing film for hydrogen sulphide SAW/BAW detection at room temperature. A matrix nanocomposite can be synthesized by incorporating both single-wall and multi-wall thiolated carbon nanotubes into conductive organic polymers or ceramic nanocrystalline in a properly functionalized manner. A thin organic sensing film can be prepared based on the matrix nanocomposite. The matrix nanocomposite sensing film can be prepared on a surface of a SAW/BAW device by an additive process or a direct printing process. Finally, the sensing film can be consolidated by thermal annealing or laser annealing under ambient conditions in order to obtain the stable sensing film with higher sensitivity and electrical properties for a SAW/BAW based H2S sensor.

Abstract: A method of assembling a circuit includes providing a template, enabling a semiconductor material to self assemble on the template, and enabling self-assembly of a connection between the semiconductor material and the template to form the circuit and a circuit created by self-assembly.

Abstract: In a circuit device having a field effect transistor and a capacitor, the capacitor is connected to at least one of a gate electrode, a source electrode and a drain electrode of a field effect transistor, the field effect transistor has a channel comprised of a first nano-wire, and the capacitor comprises a first electrode comprised of a second nano-wire having electroconductivity, a dielectric layer partly covering the peripheral face of the first electrode and a second electrode covering the peripheral face of the dielectric layer.

Abstract: An apparatus has multiple sets of independently addressable interdigitated nanowires. Nanowires of a set are in electrical communication with other nanowires of the same set and are electrically isolated from nanowires of other sets.

Abstract: A patterned array of metallic nanostructures and fabrication thereof is described. A plurality of nanowires is grown on a substrate, the plurality of nanowires being laterally arranged on the substrate in a predetermined array pattern. The plurality of nanowires is coated with a metal to generate a plurality of metal-coated nanowires. Vacancies between the metal-coated nanowires are filled in with a sacrificial material for stabilization, and the metal-coated nanowires are planarized. The sacrificial material is removed, the patterned array of metallic nanostructures being formed by the plurality of planarized metal-coated nanowires.

Abstract: A multilayer insulating structure including a first stop layer, a first insulating layer and a second stop layer is formed on the first conductive structure. A second conductive structure and a second insulating layer are formed on the first conductive structure. The second insulating layer and the second conductive structure are etched to form a first hole and a second hole having a first radius. A spacer is formed on sidewalls of the first and second holes. The second stop layer and the first insulating layer are etched using the spacer as an etch mask to form a third hole having a second radius smaller than the first radius. A sacrificial filler is formed on the first stop layer to fill the third hole. After removing the spacer, the sacrificial filler is removed. The first stop layer is etched. A carbon nano-tube is grown from the first conductive structure.