Abstract: A method for producing a polymer piezoelectric film, comprising: a process of moving and stretching a crystalline polar polymer sheet in contact with a conductive stretching roller having a diameter of at least 30 mm and a surface friction coefficient which has been reduced to such a level as to allow a relative displacement of the crystalline polar polymer sheet in contact with the conductive stretching roller: and a step in the process of applying a polarization voltage between an electrode disposed opposite to the crystalline polar polymer sheet and the conductive stretching roller to polarize the crystalline polar polymer sheet. As a result, it is possible to stably produce a polymer piezoelectric film exhibiting stable piezoelectricity over a large area. Especially, it is possible to obtain polymer piezoelectric film exhibiting a temperature-dispersion peak temperature of d31 piezoelectricity coefficient at least 120° C. and surface scratches extending in one direction.

Abstract: Provided is a substrate wherein wiring layers laminated onto the top and bottom surfaces of a core layer are connected to each other by a simple means. Also provided is a method for manufacturing said substrate. In the provided substrate (10A), a connection substrate (13) is placed in a removed region (12) which goes all the way through a part of a thick core layer (11). Said connection substrate (13) electrically connects a first wiring layer (16A) laminated onto the top surface of the core layer (11) to a second wiring layer (16B) laminated onto the bottom surface of the core layer (11). This eliminates the requirement of providing a through-hole through the core layer (11) for each connection, resulting in a small form-factor substrate (10A) with a high wiring density.

Abstract: In a method for manufacturing a module, a substrate is placed above a resin bath while a electronic component is directed downward. In addition, a resin thrown into the resin bath is softened until it becomes flowable. Then, a first surface of the substrate is brought into contact with a liquid surface of the softened resin. The softened resin is allowed to flow forcibly into a gap between the substrate and the electronic component. Then, the resin cures, and a resin portion is formed. Further, a metal thin film is formed on the surface of the resin portion by sputtering to form the shield metal film.

Abstract: A method for forming a lead or lead extension includes forming an arrangement of elongated conductors. Each of the conductors extends from a proximal end of the arrangement to a distal end of the arrangement. Each of the conductors includes a layer of insulation disposed over a conductive core. A conductor-separating element is disposed over either the proximal end or the distal end of the arrangement. The conductor-separating element includes a plurality of ablation windows defined in a body. An end of at least one of the elongated conductors is radially extended over a portion of the conductor-separating element such that a portion of the at least one elongated conductor extends across at least one of the ablation windows. Insulation from the portion of the at least one conductor extending across the ablation window is ablated to expose a portion of the conductive core of the elongated conductor.

Abstract: A space transformer for a semiconductor test probe card and method of fabrication. The method may include depositing a first metal layer as a ground plane on a space transformer substrate having a plurality of first contact test pads defining a first pitch spacing, depositing a first dielectric layer on the ground plane, forming a plurality of second test contacts defining a second pitch spacing different than the first pitch spacing, and forming a plurality of redistribution leads on the first dielectric layer to electrically couple the first contact test pads to the second contact test pads. In some embodiments, the redistribution leads may be built directly on the space transformer substrate. The method may be used in one embodiment to remanufacture an existing space transformer to produce fine pitch test pads having a pitch spacing smaller than the original test pads.

Abstract: A method for making a coaxial cable including an inner conductor, an outer conductor, and a dielectric material layer therebetween may include forming the inner conductor by at least forming a bimetallic strip into a tubular bimetallic layer having a pair of longitudinal edge portions at a longitudinal seam. The bimetallic strip may include an inner metal layer and an outer metal layer bonded thereto and coextensive therewith. Each of the longitudinal edge portions may be folded over. The method may also include forming a welded joint between adjacent portions of the folded over longitudinal edge portions and defining surplus material at the welded joint. The method may further include removing the surplus material at the welded joint and forming the dielectric material layer surrounding the inner conductor. The method may also include forming the outer conductor surrounding the dielectric material layer.

Abstract: A micro pin hybrid interconnect array includes a crystal anode array and a ceramic substrate. The array and substrate are joined together using an interconnect geometry having a large aspect ratio of height to width. The joint affixing the interconnect to the crystal anode array is devoid of solder.

Abstract: A process for manufacturing an electrical lead having one or more electrodes includes providing an elongate member having at least one polymeric region and further having at least one electrical conductor that extends along at least a part of a length of the elongate member and that is contained in a wall of the elongate member. A length of the at least one electrical conductor is accessed at the at least one polymeric region. An electrically conductive adhesive is applied to the length of the at least one electrical conductor that has been accessed.

Abstract: A dynamic quantity sensor includes a first substrate, a fixed part arranged in the first substrate, a spiral shaped movable electrode arranged separated from the first substrate, one end of the spiral shaped movable electrode being supported by the fixed part, a fixed electrode positioned on the periphery of the movable electrode and arranged in a detection direction of a dynamic quantity, and a first terminal electrically connected to the fixed part and a second terminal electrically connected to the fixed electrode.

Abstract: Provided is a wiring substrate, a semiconductor device package including the wiring substrate, and methods of fabricating the same. The semiconductor device package may include a wiring substrate which may include a base film. The base film may include a mounting region and a non-mounting region. The wiring substrate may further include first wiring patterns on the non-mounting region and extending into the mounting region, second wiring patterns on the first wiring patterns of the non-mounting region, and an insulating layer on the non-mounting region, and a semiconductor device which may include bonding pads. At least one of side surfaces of the second wiring patterns adjacent to the mounting region may be electrically connected to at least one of the bonding pads of the semiconductor device.

Abstract: A semiconductor device includes a substrate, a die assembly attachable to the substrate and a flexible strip extending over the substrate and the die assembly. The flexible strip has one or more routing circuits carried thereon. The die assembly and the substrate are arranged to be electrically connected through the one or more routing circuits carried on the flexible strip.

Abstract: The invention provides a method of manufacturing an electronic connector including the steps of: (a) providing an insulating body made of a fiberboard having a thermal deformation degree which is close to the printed circuit board, and a plurality of terminal receiving apertures penetrating a top surface and a under surface of the insulating body being deposed on the insulating body; (b) forming a plurality of conducting terminals respectively comprising a soldering portion soldering to the printed circuit board and a contacting arm electrically contacting with an electronic device; and (c) setting the conducting terminals into the insulating body.

Abstract: A method for fabricating a circuit board includes providing a first substrate, forming a circuit on the first substrate, the circuit having a first electrode, a second electrode and at least one nanostructure, and transferring the circuit from the first substrate to a surface of a second substrate made of a polymer.

Abstract: A method for manufacturing a printed wiring board includes filling material in through holes formed in first lands on a first substrate, forming projection portions projecting from the first lands on the surface of the material of the through holes, placing a conductive material on the first lands, and electrically connecting the first lands of the first substrate and second lands of second substrate by pressing the conductive material under melting filled between the first and second lands in the lamination direction of the substrates by the projection portions when laminating the substrates in such a manner that the lands of the other substrate face the lands of the substrate for aggregation of the conductive material.

Abstract: In a flat panel display apparatus having improved sealing and a method of manufacturing the same, the flat panel display apparatus comprises: a substrate; a display unit disposed on the substrate; a sealing substrate facing the display unit; a sealing member interposed between the substrate and the sealing substrate and surrounding the display unit; and a plurality of wiring groups comprising areas overlapping the sealing member between the substrate and the sealing substrate; wherein the wiring groups are disposed so as to surround the display unit, are spaced apart from an area corresponding to an edge of the display unit, and receive voltage from an external power source.

Abstract: A sheet in an electronic display is composed of a substrate containing an array of wire electrodes. The wire electrodes are preferably electrically connected to patterned transparent conductive electrode lines. The wire electrodes are used to carry the bulk of the current. The wire electrodes are capable of being extended away from the substrate and connected directly to the printed circuit board. The transparent conductive electrode (TCE) is used to spread the charge or voltage from the wire electrode across the pixel. The TCE is a patterned film and must be at least 50% transparent, and, for most applications, is preferably over 90% transparent. In most applications, the electroded surface of the electroded sheet has to be flattened. Use of a thin polymer substrate yields a light, flexible, rugged sheet that may be curved, bent or rolled.

Abstract: Some embodiments of the inventive subject matter are directed to a first circuit board configured to include an electronic component. The electronic component includes a plurality of leads. The first circuit board includes first wires configured to connect to a first portion of the plurality of leads. The second circuit board is affixed to the first circuit board. The second circuit board includes second wires. The second circuit board is smaller in size than the first circuit board. A plurality of electrical connectors extend through a thickness of the first circuit board and are configured to connect a second portion of the plurality of leads to the second wires.

Abstract: An embedded structure of circuit board is provided. The embedded structure includes a substrate, a first patterned conductive layer disposed on the substrate and selectively exposing the substrate, a first dielectric layer covering the first patterned conductive layer and the substrate, a pad opening disposed in the first dielectric layer, and a via disposed in the pad opening and exposing the first patterned conductive layer, wherein the outer surface of the first dielectric layer has a substantially even surface.

Abstract: A wiring board including a first rigid wiring board including a conductor and having an accommodation portion, the accommodation portion having wall surfaces, a second rigid wiring board accommodated in the accommodation portion and including a conductor electrically connected to the conductor of the first rigid wiring board, the second rigid wiring board having side surfaces, an insulation layer formed on the first rigid wiring board and the second rigid wiring board, and a metal film having a solid pattern formed directly on a boundary portion formed between the wall surfaces of the accommodation portion and the side surfaces of the second rigid wiring board.

Abstract: A method for making a circuit board includes separating a plurality of versatile circuit boards from a collective board by cutting a connecting portion of the collective board, the plurality of versatile circuit boards being connected each other via the connecting portion, and cutting a part of a wiring formed on each of the plurality of versatile circuit boards to produce the circuit board. The cutting of the part of the wiring is conducted within the separating of the plurality of versatile circuit boards.

Abstract: A method of forming a substrate support comprises providing a body having a groove, inserting a heater element into the groove, disposing an insert into the groove, and inserting a cap into the groove. The heater element comprises a resistive element inside a sheath encased in a malleable cladding. The insert is disposed over the cladding, and the cap is substantially flush with an outer surface of the body.

Abstract: A wired circuit board includes an insulating layer, and a first conductive pattern and a second conductive pattern formed on the insulating layer. The first conductive pattern includes a first outer terminal on which a metal plating layer is provided, a first inner terminal to be solder connected, and a first wire which connects the first outer terminal and the first inner terminal. The second conductive pattern includes a second outer terminal to be solder connected, a second inner terminal to be solder connected, and a second wire which connects the second outer terminal and the second inner terminal. The first inner terminal and the second inner terminal are arranged in opposed relation with each other so as to be solder connected to the common electric component and preflux processing is performed thereon, and a metal plating layer is provided on the second wire.

Abstract: Methods for fabricating a coplanar waveguide structure. The method may include forming first and second ground conductors and a signal conductor in a coplanar arrangement between the first and second ground conductors, forming a first coplanar array of substantially parallel shield conductors above the signal conductor and the first and second ground conductors, and forming a second coplanar array of substantially parallel shield conductors below the signal conductor and the first and second ground conductors. The method further includes forming a first plurality of conductive bridges located laterally between the signal conductor and the first ground conductor, and forming a second plurality of conductive bridges located laterally between the signal conductor and the second ground conductor. Each of the first plurality of conductive bridges connects one of the shield conductors in the first array with one of the shield conductors in the second array.

Abstract: A target layer with holes is formed on a bottom conducting layer. Nanotubes are formed in the holes from the bottom conducting layer. A flat insulating layer is then deposited on the target layer, the nanotubes passing through the insulating layer. Air gaps are then formed by selective decomposition of the target layer. The decomposition agent and/or decomposition by-products use the walls and the central holes of the nanotubes to pass between the target layer and the outside. After decomposition, the top conducting layer is formed on the insulating layer. The nanotubes then electrically connect the conducting layers.

Abstract: A smart card inlay and method for assembling the same are provided. The method includes attaching a first trace to a substrate, attaching a second trace to the substrate, attaching an antenna wire to the substrate, coupling a first end of the antenna wire to a first area of the first trace, and coupling a second end of the antenna wire to a first area of the second trace. A second area of the first trace and a second area of the second trace are configured to be coupled to an integrated circuit (IC) or IC module, and the first area of the first trace is located away from the second area of the first trace and the first area of the second trace is located away from the second area of the second trace.

Abstract: The invention provides a method for producing a connection grid with integrated fuse includes the steps of forming a concave portion that is suitable for forming a cradle for receiving one of the longitudinal ends of a fuse on each of the arms of a pair of arms of a connection grid in order to fix the fuse to the grid via these longitudinal ends, and molding a support formed by molding plastic onto the connection grid after the concave portions of the arms have been produced, wherein the support has a housing that is suitable for receiving a portion of the fuse in a space formed between the at least one pair of arms.

Abstract: Disclosed is a multilayer wiring board in which a copper foil is bonded by a thermocompression bonding onto an insulating layer having a bump for interlayer connection buried therein, and the copper foil and the bump are electrically connected to each other. The copper foil is provided with an oxide film having a thickness of 50 ? to 350 ? on a surface in contact with the bump and an insulating layer. In a manufacturing process, for example, an oxide coating of the copper foil to be subject to the thermocompression bonding is removed by acid cleaning, and then an oxide film having an appropriate thickness is formed by irradiating the copper foil with ultraviolet light. Consequently, reliability in electrical connection between the copper foil and the burn is adequately ensured, while achieving sufficient mechanical connection strength between the copper foil and the insulating layer.

Abstract: In a circuit module having components that are fastened to a substrate, the substrate includes a carrier layer made of metal and having a first surface, a first insulating layer bordering directly on the carrier layer being situated on the first surface. The substrate also includes a first wiring layer bordering directly on the first insulating layer, which conducts electrically and is situated on the first insulating layer. The substrate includes a first contact plane, which runs along the first surface, at least one of the components being directly connected electrically to the carrier layer in the first contact plane.

Abstract: A multilayered wiring substrate and a manufacturing method thereof are disclosed.

Abstract: The invention is to provide a metal circuit wiring having an organic adhesive layer, the metal circuit wirings comprising: an organic adhesive layer formed with a resin selected from the group consisting of acrylic resin, chloroprene rubber and silicone rubber resin; and metal wiring patterns formed with an ink composition including metal nanoparticles, in which the metal wiring exhibits excellent adhesive between metal nano materials and the substrate and electrical property.

Abstract: There are provided a multilayer wiring board and a method of manufacturing the same. The multilayer wiring board according to an aspect of the invention may include: a main body having a plurality of insulting layers stacked upon each other, including a first layer provided as an inner layer and a second layer provided as an outer layer; a first resistor provided on the first layer; and a second resistor provided on the second layer, connected in parallel with the first resistor, and having a smaller area than the first resistor. The multilayer wiring board obtains a target resistance value using the first and second resistors formed on the first and second layers. The second resistor, formed on the outer layer, can have a smaller area than the first resistor. Accordingly, the usable area of the outer layer is increased to thereby reduce the size of the multilayer wiring board.

Abstract: A conductor circuit and method of manufacturing a conductor circuit. The method includes forming a continuous conductor pattern on an insulating substrate, and connecting a short-circuit wire at a first position on the continuous conductor pattern such that two or more points on the continuous conductor pattern are short-circuited to each other by the short-circuit wire at the first position. An electrolytic plating film is formed on the continuous conductor pattern while the short-circuit wire is connected to the continuous conductor pattern at the first position, and the short-circuit wire is removed from the first position on the continuous conductor pattern to uncover a first exposed portion of the continuous conductor pattern.

Abstract: A method of making an electronic label including a chip (1) provided with two contact strips (2, 3) onto which a conducting wire (4) is welded in a single operation. The segment of conducting wire (4) forming the antenna is then cut between the two contact strips (2, 3) of chip (1). The group of chip and antenna thus realized may then be encapsulated between two sheets of a fibrous or plastic material.

Abstract: In a method of manufacturing an inspection apparatus for inspecting an electronic device, a sacrificial substrate is formed into a substrate pattern including a through-hole. A principal substrate including an internal wiring penetrating from a first surface to a second surface thereof is combined with the substrate pattern in such a configuration that the through-hole is positioned over the internal wiring, thereby forming a combined structure. A filling structure is formed in the through-hole of the substrate pattern, and the filling structure is electrically connected to the internal wiring of the principal substrate. The substrate pattern is removed from the combined structure, and thus the filling structure is formed into a probe structure on the principal substrate. The probe structure may be connected to the principal substrate without any adhesives such as a solder, to thereby prevent electrical resistance increase and excessive thermal stress.

Abstract: There is provided a bank structure which partitions off a pattern formation region in which a functional liquid is to be disposed and flow. The pattern formation region includes a first pattern formation region, and a second pattern formation region which is continuously connected to the first pattern formation region and which has a larger width than the first pattern formation region. The second pattern formation region is provided with at least one partition bank which partitions off the second pattern formation region to regulate the flow direction of the functional liquid. A partition width substantially orthogonal to the flow direction of the functional liquid which is regulated by the partition bank is less than ±20% of the width of the first pattern formation region.

Abstract: Disclosed herein is a wiring board including: a shield layer; and n layers (n is an integer of two or more) of inductor wiring formed above the shield layer and forming an inductor; wherein of the n layers of inductor wiring, the inductor wiring closest to the shield layer has a smallest wiring area.

Abstract: A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact.

Abstract: A printed wiring board and a method for manufacturing the same are provided. The printed wiring board includes a resin insulation layer having a first surface and a second surface opposite the first surface, and includes an opening for a first via conductor. An electronic-component mounting pad is formed on the first surface of the resin insulation layer. The electronic-component mounting pad includes a portion embedded in the resin insulation layer and a portion protruding from the resin insulation layer. The protruding portion covers the embedded portion and a portion of the first surface of the resin insulation layer that surrounds the embedded portion. A first conductive circuit is formed on the second surface of the resin insulation layer. A first via conductor is formed in the opening of the resin insulation layer and connects the electronic-component mounting pad and the first conductive circuit.

Abstract: At least one electronic component having a plurality of terminals on one of surfaces is temporarily fixed to a surface of a first support with a first adhesive layer in such a manner that the terminal side of the electronic component faces the first support. A second support having a second adhesive layer is fixed to the electronic component in order to interpose the electronic component between the first support and the second support. The first support and the first adhesive layer are peeled. The electronic component on the second support is sealed with a sealing resin in such a manner that at least a part of the terminals of the electronic component is exposed. An insulating resin layer and a wiring layer to be electrically connected to the terminal of the electronic component are stacked on the electronic component and the sealing resin.

Abstract: A wiring board (package) has a structure in which multiple wiring layers are stacked one on top of another with insulating layers each interposed between corresponding two of the wiring layers, and the wiring layers are connected to each other through vias formed in the insulating layers. In the peripheral region around the chip mounting area of the outermost insulating layer on one of both surfaces of the board, a pad is formed in a bump shape to cover a surface of a portion of the outermost insulating layer, the portion being formed to protrude, and a pad whose surface is exposed from the insulating layer is arranged in the chip mounting area. A chip is flip-chip bonded to the pad of the package, and another package is bonded to the bump shaped pad in a peripheral region around the chip (package-on-package bonding).

Abstract: A wiring board with lead pins includes: connection pads formed on a wiring board, and lead pins bonded through a conductive material to the connection pads, wherein each of the lead pins has a head portion that is formed in one end of a shaft portion to be larger in diameter than the shaft portion, the head portions are bonded to the connection pads by the conductive material, a face of the wiring board on which the connection pads are formed is resin-sealed by a first resin to be thicker than the head portions, except portions to which the head portions are bonded, and sides of faces of the head portions to which the shaft portions are connected are sealed to be in close contact with the first resin by a second resin.

Abstract: A multilayer wiring substrate is manufactured through a recess forming step, a gold-diffusion-prevention-layer forming step, a terminal forming step, resin-insulating-layer forming step, a conductor forming step, and a metal-layer removing step. In the recess forming step, a copper foil layer is half-etched so as to form recesses. In the gold-diffusion-prevention-layer forming step, a gold diffusion prevention layer is formed in each recess. In the terminal forming step, a gold layer, a nickel layer, and a copper layer are stacked in sequence on the gold diffusion prevention layer to thereby form a surface connection terminal. In the resin-insulating-layer forming step, a resin insulating layer is formed, and, in the conductor forming step, via conductors and conductor layers are formed. In the metal-layer removing step, the copper foil layer and the gold diffusion prevention layer are removed so that the gold layer projects from the main face of the laminated structure.

Abstract: A wiring substrate includes a substrate body including first and second surfaces on opposite sides and a substrate side surface; a penetration electrode penetrating through the substrate body; a first wiring pattern on the first surface and including a first pad; a second wiring pattern on the second surface and including a second pad; a first insulating resin layer covering the first wiring pattern except for an area corresponding to the first pad and having a first resin side surface; a second insulating resin layer covering the second wiring pattern except for an area corresponding to the second pad and having a second resin side surface that is flush with the first resin side surface; a notch part encompassing at least apart of the substrate body and having a resin material provided therein. The substrate side surface is located more inward than the first and second resin side surfaces.

Abstract: Embodiments of the present invention provide a printed wiring board in which solder bumps of a mounted semiconductor chip are less prone to be ruptured. The printed wiring board includes a coreless substrate which includes: a dielectric layer having a main surface and a connecting pad embedded in the dielectric layer. The connecting pad is shaped like a brimmed hat. That is, the connecting pad includes a plate portion whose diameter ?1 is about 95 ?m and a contact portion whose diameter ?c is about 75 ?m. The main surface of the contact portion is exposed at the main surface of the dielectric layer. Since diameter ?c of the contact portion is substantially the same as diameter ?2 of an under bump metal at the semiconductor chip side, even if mechanical stress is applied in a direction in which the semiconductor chip is peeled off from the coreless substrate, the stress disperses evenly to both of the connecting pad and the under bump metal, and thus rupture is less prone to occur.

Abstract: A multilayer printed wiring board includes one or more resin layers having via-holes and a core layer having via-holes. The via-holes formed in the one or more resin layers are open in the direction opposite to the direction in which the via-holes formed in the core layer are open. A method for manufacturing a multilayer printed wiring board includes a step of preparing a single- or double-sided copper-clad laminate; a step of forming lands by processing the copper-clad laminate; a step of forming a resin layer on the upper surface of the copper-clad laminate, forming openings for via-holes in the resin layer, and then forming the via-holes; and a step of forming openings for via-holes in the lower surface of the copper-clad laminate and then forming the via-holes.

Abstract: The multilayer wiring board is provided with a lower layer wiring (8), and an upper layer wiring (10) formed on the lower layer wiring (8) through an interlayer insulating layer (9). On the interlayer insulating layer (9), a contact hole (11) is provided for interconnecting the upper layer wiring (8) with the lower layer wiring (10). A region surrounded by an inner wall (13) which forms the contact hole (11) is permitted to have a linewidth region wherein a wide line region (13A) and protruding regions (13B, 13C) as regions having different linewidths are connected. Thus, film thickness distribution of an ink baked product (12) formed at the contact hole (11) rises at the protruding regions (13B, 13C), and highly reliable multilayer interconnection can be performed between the lower layer wiring (8) and the upper layer wiring (10).

Abstract: A shielded flexible cable having a plurality of shielded electronic circuits in close proximity to one another such that signals transmitted on one of said plurality of shielded electronic circuits do not substantially interfere with signals transmitted on the other of said plurality of electronic circuits comprising a polyimide support member supporting a plurality of etched copper traces on a first side of said polyimide support member and a copper layer on a second side of said polyimide support member. Said polyimide support member is flexible along at least one axis, and said plurality of etched copper traces and said copper layer substantially as flexible as said polyimide support member.

Abstract: A method for manufacturing a semiconductor device that improves the reliability of a metal cap layer and productivity. The method includes an insulation layer step of superimposing an insulation layer (11) on a semiconductor substrate (2) including an element region (2b), a recess step of forming a recess (12) in the insulation layer (11), a metal layer step of embedding a metal layer (13) in the recess (12), a planarization step of planarizing a surface of the insulation layer (11) and a surface of the metal layer (13) to be substantially flush with each other, and a metal cap layer step of forming a metal cap layer (16) containing at least zirconium element and nitrogen element on the surface of the insulation layer (11) and the surface of the metal layer (13) after the planarization step.

Abstract: A multilayer printed wiring board includes a mounting portion supporting a semiconductor device and a layered capacitor portion including first and second layered electrodes and a ceramic high-dielectric layer therebetween. The first layered electrode is connected to a ground line and the second layered electrode is connected to a power supply line. The ratio of number of via holes, each constituting a conducting path part electrically connecting a ground pad to the ground line of a wiring pattern and passing through the second layered electrode in non-contact, to number of ground pads is 0.05 to 0.7. The ratio of number of second rod-shaped conductors, each constituting a conducting path part electrically connecting a power supply pad to the power supply line of the wiring pattern and passing through the first layered electrode in non-contact, to number of power supply pad is 0.05 to 0.7.

Abstract: Disclosed is a wiring board comprising a plurality of conductors (11) having a conductive member including first conductive material (1) and second conductive material (2), and insulating member (3) covering the conductive member. A plurality of conductors (11) are arranged lattice-like and are weaved like a woven cloth, and sections intersecting with each other are electrically connected.