Abstract: The invention pertains to systems where DC power is supplied by a PSE to a PD, such as over differential data wire pairs. IEEE standards require a minimum current to be drawn from the PD in order for the PSE to continue supplying the DC voltage. If the PD is in a low power mode, the PSE will normally discontinue supplying the DC voltage, which then requires a new detection and classification routine for powering up again. To avoid this, a “maintain power signature” controller provides a periodic current pulse by a current source connected between the PD input and the PD's full bridge rectifier. Any droop in the DC voltage that reverse biases the full bridge rectifier while the PD is in its low power mode will not affect the current pulse, so the PSE continues to supply the DC voltage.

Abstract: Provided is a cascode circuit including first and second transistors connected between a drain terminal and a source terminal in cascode form, a level sifter configured to change a voltage level of a switching control signal applied to a gate terminal and provide the changed switching control signal to a gate of the first transistor, a buffer configured to delay the switching control signal and provide the delayed switching control signal to a gate of the second transistor, and a first resistor connected between the level shifter and the gate of the first transistor.

Abstract: A switched capacitor converter and a method for configuring the switched capacitor converter are disclosed. The switched capacitor converter includes a capacitance resource with a cathode and an anode and a switching matrix with a first terminal, a second terminal, a third terminal, and at least one switch configured to switch among two or more connections selected from the group consisting of a connection of the first terminal to the anode and the second terminal to the cathode and a connection of the second terminal to the anode and the third terminal to the cathode.

Abstract: A bias circuit includes a first transistor, a second transistor, a first resistor and a second resistor. The first end of the first transistor is coupled to a first voltage source. One end of the first resistor is coupled to the second end of the first transistor, and the other end of the first resistor is coupled to the control terminal of the first transistor. The first end of the second transistor is coupled to a second voltage source, and the second end of the second transistor is coupled to the control terminal of the first transistor. One end of the second resistor is coupled to the other end of the first resistor, and the other end of the second resistor is coupled to the control terminal of the second transistor.

Abstract: Apparatus and methods are disclosed, including an apparatus having a first transistor configured to be coupled to a first bit line, and a control circuit configured to supply a gate of the first transistor with a first voltage to turn on the first transistor, and to supply the gate of the first transistor with a second voltage higher than the first voltage to strengthen a current drive capability of the first transistor.

Abstract: A circuit including a first PMOS (p-channel metal oxide semiconductor) transistor, a first NMOS (n-channel metal oxide semiconductor) transistor, a second PMOS transistor, and a second NMOS transistor. A source, a gate, and a drain of the first PMOS transistor connect to a first node, a second node, and a third node, respectively. A source, a gate, and a drain of the first NMOS transistor connect to a fourth node, the third node, and the second node, respectively. A source, a gate, and a drain of the second PMOS transistor connect to the third node, the fourth node, and the second node, respectively. Finally, a source, a gate, and a drain of the second NMOS transistor connect to the second node, the first node, and the third node, respectively.

Abstract: A current limiting circuit includes a current sensing module that is configured to sense an output current of a power transistor and to generate a corresponding sensing current which is proportional to the output current. A first current limiting module coupled to the current sensing module is configured to generate a first limiting current based on the sensing current when a variation of the output current of the power transistor exceeds a first current level. A second current limiting module coupled to the current sensing module is configured to generate a second limiting current based on the sensing current when a variation of the output current of the power transistor exceeds a second current level. A converting module coupled to the first and second current limiting modules and the power transistor controls a gate voltage of the power transistor based at least on the first and second limiting currents.

Abstract: Disclosed is an inspection apparatus for inspecting a chip for noise, including an inspection circuit that is connected to a first power line of the chip and that receives a signal to be inspected, wherein the first voltage is applied to the first power line and the signal to be inspected includes noise having a second voltage, and a voltage doubler that is connected to the first power line and boosts a voltage of driving power having the first voltage, wherein the inspection circuit may be driven by the driving power, the voltage of the driving power is boosted by the voltage doubler, and the inspection circuit inspects the chip for the noise of the signal to be inspected.

Abstract: A method of measuring an output resistance of a DUT includes determining an initial output resistance of an n-type transistor, thereby determining an initial gate voltage for the n-type transistor, and determining an initial output resistance of a p-type transistor, thereby determining an initial gate voltage for the n-type transistor. A resistance for a cascode arrangement of the n-type transistor and the p-type transistor is determined, and the output resistance of the DUT using the cascode arrangement is measured by biasing the n-type transistor with the initial gate voltage for the n-type transistor and biasing the p-type transistor with the initial gate voltage for the p-type transistor.

Abstract: A phase locked loop (PLL) circuit and a method for providing a transconductance in the PLL involve forming an input voltage to an operational amplifier by a loop filter. A voltage output of the operational amplifier controls a plurality of current mirrors. A current is formed through a first one of the current mirrors as a function of the input voltage, a resistance of a resistor, and a reference voltage. The reference voltage is directly provided by, or derived from, a reference signal. A second voltage formed in the first current mirror is fed back to the operational amplifier to maintain the current through the first current mirror, which current is then mirrored into at least a second one of the current mirrors to form an output current proportional to a difference between the input voltage and the reference voltage.

Abstract: In some embodiments, a powered device includes a powered device circuit, which may include a maintain power signature (MPS) circuit configured to compare a sense current to a reference current. In a first mode, the MPS circuit may be configured to automatically generate an MPS signal when the sense current is less than the reference current.

Abstract: An apparatus is provided which includes: a first power supply node; a second power supply node; a memory bit-cell coupled to the second power supply node; a circuitry coupled to the first and second power supply nodes, the circuitry to operate in a diode-connected mode; and a transistor coupled in parallel to the circuitry, wherein the transistor is controllable by a digital signal such that when the transistor is to turn on, it is to apply voltage and/or current stress to the memory bit-cell.

Abstract: The present invention is directed to electrical circuits and techniques thereof. More specifically, an embodiment of the present invention provides a line driver with transistors directly coupled to the ground, and a bias voltage is coupled common mode resistors of the line driver. There are other embodiments as well.

Abstract: The invention provides a voltage stabilizing device. In the voltage stabilizing device, a signal detecting and amplifying circuit detects an operating voltage of the functional circuit, amplifies the detected operating voltage and outputs the amplified voltage signal to a logic processing circuit; the logic processing circuit adjusts a first control signal according to the amplified voltage signal and outputs the adjusted first control signal to a feedback voltage signal generating circuit; the feedback voltage signal generating circuit adjusts a feedback voltage signal according to the adjusted first control signal and outputs the adjusted feedback voltage signal to the logic processing circuit. Moreover, the logic processing circuit further adjusts a second control signal according to the adjusted feedback voltage signal and outputs the adjusted second control signal to the functional circuit, and thereby controls an output voltage of the functional circuit to be kept stable.

Abstract: Voltage level shifting in a switching output stage is presented. The circuit may include a switching output stage configured to receive an analog input signal and provide a responsive digital output signal, the switching output stage having a first switching device coupled to a first supply voltage and a second switching device coupled to a second supply voltage, the first switching device and the second switching device being coupled to a common output node. The apparatus may also include a voltage level shifter circuit coupled to a switching control node of the second switching device, the voltage level shifter configured to shift a voltage level at the switching control node of the second switching device relative to the analog input signal, wherein the digital output signal at the common output node transitions as the input signal reaches a predetermined threshold value.

Abstract: An on chip temperature independent current generator for generating a temperature independent current, said temperature independent current generator including: an on chip current generator having an output to provide an electrical current being proportional to an absolute temperature of a chip in which the temperature independent current generator is embedded; and an on chip transistor having a base connected to a temperature independent reference voltage generator, a collector connected to a current mirror, and an emitter connected to the output of the on chip current generator and connected via an on chip resistor to a reference potential, wherein the current mirror is adapted to mirror a collector current flowing to the collector of said on chip transistor to generate the temperature independent current.

Abstract: Method and device for controlling an inductive load by pulse width modulation, on the basis of a periodic set point control signal having a given set point duty cycle. The set point control signal is, in each period of the set point control signal, in a first logic state determined from the high and low logic states for at least a first duration, and is in the other logic state during the rest of the period. Control signals are generated for activating the inductive load, on the basis of the set point control signal. With the aid of a first counter, the first duration (t0) is determined on the basis of the set point control signal. Via a second counter, a second duration (t0?td2) is determined, for which a logic signal corresponding to an effective control signal observed in the load is in the first determined logic state.

Abstract: A testing structure includes a first transistor having a first dopant type connected to a current source. The testing structure further includes a second transistor having a second dopant type, opposite to the first dopant type. The second transistor is connected to a device under test (DUT). The second transistor is connected in series with the first transistor in a cascode arrangement. The cascode arrangement is capable of measuring an output resistance of the DUT of greater than 1 mega-ohm (M?).

Abstract: A transmitter according to the disclosure includes: three first driver sections; three first pre-driver sections that are provided corresponding to the respective three first driver sections, and each drive corresponding one of the first driver sections on a basis of corresponding one of three first control signals that are different from one another and each including predetermined number of signals; a second pre-driver section that operates on a basis of a second control signal that includes predetermined number of signals; and a controller that controls transition of the predetermined number of signals included in the second control signal to allow number of signals to be subjected to the transition out of the plurality of signals included in the three first control signals and the plurality of signals included in the second control signal to be same between timings of the transition.

Abstract: A feed-forward bias circuit biases body bias terminals of transistors of another circuit to compensate for PVT variations in the other circuit. In some aspects, the feed-forward bias circuit compensates for transistor process corners in a circuit by enabling the generation of different bias signals under different corner conditions. In some implementations, the feed-forward bias circuit is used to bias a delay circuit so that the delay circuit exhibits relatively constant delay characteristics over different PVT conditions.

Abstract: A voltage regulator may include an error amplifier configured to amplify a difference between a reference voltage and a feedback voltage and generate a first amplified voltage based thereon; a power transistor between a second voltage supply node and an output node of the voltage regulator, the power transistor including a gate configured to receive a gate voltage; a buffer between a first voltage supply node and a ground, the buffer configured to generate the gate voltage based on the first amplified voltage; a voltage divider between the output node and the ground, the voltage divider configured to generate the feedback voltage based on the output voltage; and a control circuit configured to connect the output node to the ground through the gate of the power transistor based on the output voltage and the gate voltage.

Abstract: Apparatus and methods for voltage regulation are provided. In some implementations, a voltage regulator circuit includes a field-effect transistor including a source that receives a battery voltage from an input node and a drain coupled to an output node, an amplifier including an output coupled to a gate of the field-effect transistor, and a voltage generator that receives the battery voltage from the input node and provides a reference voltage and one or more bias voltages to the amplifier. The voltage generator controls the amplifier to operate the voltage regulator circuit in a regulation mode or in a bypass mode based on a voltage level of the battery voltage. The amplifier and the field-effect transistor regulate the battery voltage in the regulation mode to provide a regulated voltage at the output node, and the amplifier turns on the field-effect transistor in the bypass mode to provide a bypass voltage substantially equal to the battery voltage at the output node.

Abstract: A power supply noise reduction circuit and a power supply noise reduction method are provided. An integrated circuit includes an input node configured to receive a signal via a transmission line. The integrated circuit also includes termination circuitry configured to electrically couple the input node to a power rail of the integrated circuit. The integrated circuit further includes a circuit component coupled to the power rail. The circuit component is configured to bleed off a portion of current on the power rail based on a determination that a voltage on the power rail meets or exceeds a high voltage threshold. The circuit component is also configured to bleed off a smaller portion of the current on the power rail based on a determination that the voltage on the power rail is less than the high voltage threshold.

Abstract: There is disclosed a controller for a DC-DC converter comprising a series arrangement of a high-side switch and low-side switch with a half-bridge node therebetween, the controller comprising a high-side part for driving the high-side switch and configured to be powered, when the low-side switch is open, by a rechargeable power supply connected between the half-bridge node and a power supply node, the high-side part comprising a level shifter, driver, latch part comprising a latch having set and reset inputs and configured to latch the driver to either an on-state or an off-state, and a further circuit, wherein the latch part is configured and adapted to prevent the further circuit from drawing current from the power supply unless at least one of the set input is high and the driver is in the on-state. A DC-DC converter having such a controller is also disclosed, as are methods of operating a converter.

Abstract: An example method includes outputting, by a device, a first current through a temperature sensor that is that is external to the device; determining, by the device and based on a voltage drop across the temperature sensor while the first current is flowing through the temperature sensor, a current level; outputting, by the device, a second current at the determined current level through the temperature sensor; determining, by an analog-to-digital converter (ADC) of the device, a value that corresponds to a voltage drop across the temperature sensor while the second current is flowing through the temperature sensor; outputting, by the device, a third current through a reference resistor that is external to the device; and determining, based on the value and a voltage drop across the reference resistor while the third current is flowing through the reference resistor, a temperature of the temperature sensor.

Abstract: A reference voltage generation circuit includes a voltage dividing circuit, a transistor, and a capacitor. The voltage dividing circuit divides a power-supply voltage into a specified level to generate a predetermined voltage. The transistor has a gate applied with the predetermined voltage and a drain outputting, as a reference voltage, a voltage obtained by adding the predetermined voltage and a threshold voltage of the transistor. The capacitor bypasses the gate and source of the transistor. Moreover, one end of the capacitor is connected to the gate of the transistor, and the other end of the capacitor is connected to the source of the transistor and ground. Furthermore, an electric charge output source which outputs an electric charge is connected to the drain of the transistor.

Abstract: An optical interconnect device is provided that includes a first vertical cavity of surface emitting laser (VCSEL), connected in parallel with a second VCSEL, an optical coupler that is configured to direct the light output from the first VCSEL and the second VCSEL to a single optical fiber, where a common connection of each VCSEL is controlled using a MOSFET/inverter, where in normal operation only one of the first VCSEL or the second VCSEL is enabled, where a common connection of each VCSEL is not directly connected to a ground, and a microcontroller that is configured to switch output from the first VCSEL to the second VCSEL in the event of failure by the first VCSEL, where a failure of the first VCSEL does not result a communication in link failure.

Abstract: A power-on reset circuit includes a first resistor having one end connected to a power source node; a first capacitor connected to another end of the first resistor; a second resistor having one end connected to the power source node; a second capacitor connected to another end of the second resistor; a first inverter having a power source terminal connected to the other end of the first resistor and an input terminal connected to the other end of the second resistor; and a second inverter having a power source terminal connected to the other end of the first resistor, an input terminal connected to an output terminal of the first inverter, and an output terminal electrically connected to a reset signal output terminal.

Abstract: A memory circuit includes a first column of memory cells arranged along a first direction, a first supply voltage line extending along the first direction in a first conductive layer of the memory circuit, a second supply voltage line, a first resistive device electrically connecting the first supply voltage line and the second supply voltage line, and a supply voltage source. Each memory cell of the first column of memory cells includes a supply voltage line segment. The first supply voltage line is made of at least the supply voltage line segments of the first column of memory cells. The supply voltage source is electrically coupled with first supply voltage line through one or more conductive paths, and the second supply voltage line and the first resistive device is in a lowest resistance path of the one or more conductive paths.

Abstract: Systems and methods for ultra-precision regulated voltage are provided. In one embodiment, a voltage regulated power supply device comprises: a precision reference voltage generator comprising a current regulator network supplying current into a voltage reference node, and a voltage regulator network applying a voltage potential to the voltage reference node, wherein at least one of the current regulator network or the voltage regulator network comprise a random variance statistical mitigation architecture; and a power amplifier coupled to voltage reference node, where the voltage reference node provides a constant voltage reference to the power amplifier.

Abstract: A circuit arrangement comprises a first terminal for connection to a voltage source, a second terminal for connection to a first current sink and a third terminal for supplying a potential signal. A first diode string can be connected to the voltage source on the anode side and to the first current sink on the cathode side. The third terminal can be coupled to the cathode side of the first diode string by a resistor. An adjustable reference current sink is coupled to the third terminal, for generating a reference current, and comparison unit coupled to the third terminal on the input side for providing a short-circuit detection signal in dependence on a difference between the potential signal and an adjustable reference voltage. The potential signal can be supplied in dependence on a first short-circuit voltage across the first diode string and in dependence on the reference current.

Abstract: Systems, methods, and apparatus for generating a reference current. A reference current source can include a current generator circuit; a first resistance circuit that has a positive temperature dependence; and a second resistance circuit that has a negative temperature dependence. The first resistance circuit and the second resistance circuit can be connected in parallel to the current generator circuit.

Abstract: A payment object reader configured to delay reading data of an integrated circuit payment object in the payment object slot of the payment object reader until the rest of the payment object reader is ready to read data off of the integrated circuit payment object. The payment object reader can be configured to include a microcontroller configured to monitor and manage the payment object contact switch and the integrated circuit payment object interface of the payment object slot of the payment object reader.

Abstract: A voltage regulator includes an input terminal to receive an input voltage, an output terminal to supply an output voltage, a power transistor, a differential amplifier, a driver, a dropout detector and a bias current limiter. The differential amplifier provides a drive signal based on a difference between a voltage reference and a feedback signal corresponding to the output voltage. The driver includes an impedance device, and a driver transistor that receives the drive signal so as to vary a bias current to a control terminal of the power transistor. The dropout detector and the bias current limiter is coupled to the input terminal, the impedance device, and the output terminal and includes first and second transistors coupled together, and a bias current generator coupled to the second transistor.

Abstract: A liquid crystal display panel is disclosed and has a driving circuit, a plurality of data lines, a plurality of scanning lines, and a plurality of pixel units. The driving circuit further includes a programmable DC current source being used to output a corresponding shaping electric current according to a reference voltage, and a shaping resistor being used to generate a corresponding shaping voltage according to the outputted shaping electric current. A liquid crystal display apparatus is also disclosed. The apparatus is able to output shaping voltages with different voltage levels at the same time, thus having a better 3D display effect.

Abstract: A voltage generator is provided which is reliable, self starting and only requires a few components. The voltage generator comprises a first stage that provides a current to a second stage. The first stage has a temperature coefficient of one sign, such as positive, and the second stage has an opposing temperature coefficient, e.g. negative. The responses are summed such that the overall temperature coefficient is reduced.

Abstract: Systems and methods for load current compensation for analog input buffers. In various embodiments, an input buffer may include a first transistor (Q1) having a collector terminal coupled to a power supply node and a base terminal coupled to a first input node (vinp); a second transistor (Q2) having a collector terminal coupled to an emitter terminal of the first transistor (Q1); a third transistor (Q3) having an emitter terminal coupled to an emitter terminal of the second transistor (Q2) and to a ground node, a collector terminal coupled to a current source (Ibias), and a base terminal coupled the collector terminal and to a base terminal of the second transistor (Q2); and a capacitor (C1) coupled to the base terminals of the second and third transistors (Q2 and Q3) and to a second input node (vinn), wherein the first and second input nodes (vinp and vinn) are differential inputs.

Abstract: A current reference includes a tracking voltage generator. The tracking voltage generator includes a flipped gate transistor and a first transistor, the first transistor having a first leakage current, wherein the first transistor is connected with the flipped gate transistor in a Vgs subtractive arrangement. The tracking voltage generator further includes an output node configured to output a tracking voltage; and a second transistor connected to the output node, the second transistor having a second leakage current. The current reference further includes an amplifier configured to receive the tracking voltage and to output an amplified signal. The current reference further includes a control transistor configured to receive the amplified signal and to conduct a reference current therethrough. The current reference further includes a control resistor connected in series with the control transistor.

Abstract: A bias circuit for a transistor amplifier, the bias circuit comprising a low-pass filter block, a reference transistor, a sum node, a reference current source, and a current difference block, wherein the low-pass filter block is configured to sense a DC bias voltage at a control terminal of the transistor amplifier and provide the DC bias voltage to a control terminal of the reference transistor; the reference transistor is configured to output a bias current in response to the DC bias voltage and provide the bias current to the sum node; the sum node is configured to receive a reference current from the reference current source and combine the reference current with the bias current from the reference transistor to provide a difference current; and the current difference block is configured to receive the difference current from the sum node and provide the difference current to the control terminal of the transistor amplifier.

Abstract: A differential operational amplifier, which comprises: a voltage adjusting module, coupled between a first predetermined voltage source and a second predetermined voltage source, for adjusting a first voltage via a first voltage adjusting value to generate a first adjusted voltage, and for adjusting a second voltage via a second voltage adjusting value to generate a second adjusted voltage, wherein the first voltage adjusting value and the second voltage adjusting value change corresponding to a temperature; and a differential signal computing module, coupled between the first predetermined voltage source and the second predetermined voltage source, for generating an output voltage according the first adjusted voltage and the second adjusted voltage.

Abstract: A biasing circuit includes a differential communication line comprising a first signal line and a second signal line. The biasing circuit further includes a first current source coupled between a power supply and the first signal line. The biasing circuit further includes a first high-precision voltage reference coupled to the first current source, wherein the first high-precision voltage reference outputs a reference voltage that drives a current produced by the first current source. The biasing circuit further includes a second current source coupled to the second signal line and a system ground, wherein the second current source is driven by a voltage supplied by the power supply.

Abstract: A driver circuit configured to produce a pair of output signals from a pair of input signals. The proposed solution brings improvements over conventional LVDS and subLVDS driver circuits because it enables the use of a single driver circuit (also known as “buffer”) which is compliant with both LVDS and subLVDS transmission standards. This allows flexibility with MCUs for instance the automotive industry. Further, proposed solution has the advantage of saving die size in comparison to a solution where two buffers would have been used for different transmission standards. Further, high speed transmission rate is maintained since transmission is performed for one standard at the time. An integrated circuit, a printed circuit and a data processing circuit are also claimed.

Abstract: In a bandgap voltage reference with low package shift, a proportional to absolute temperature (PTAT) voltage is generated using a single diode biased at two different current levels at two different times. Using the same diode for both current density measurements removes the absolute value of the base-emitter junction voltage (Vbe) and any package shift in the PTAT voltage. The bandgap voltage reference can be implemented in a single or differential circuit topology. In some implementations, the bandgap voltage reference can include circuitry for curvature correction.

Abstract: An energy storage apparatus has developed for railway vehicles by adopting a bidirectional DC-DC converter to increase the efficiency of charge/discharge, comprising that; a power receiving unit, filter unit, charging unit storage unit having a plurality of super-capacitors, capacitor monitoring unit, a plurality of bidirectional DC-DC converters arranged in parallel, and voltage detector electrically connected to the filter unit, current detector for detecting the currents flowing. The controller further comprises; an analog interface board, signal identifying board, signal control board, digital output contact unit, communicating board, PWM control board, optical output board, external gate driver. The PWM control board includes; a sensor input circuit, A/D converter, calculation unit, calculation control processor, and power monitoring unit.

Abstract: The present invention provides a voltage generation circuit which outputs high-precision output voltage in a wide temperature range. A semiconductor device has a voltage generation circuit. The voltage generation circuit has a reference voltage generation circuit which outputs reference voltage, and a plurality of correction circuits for generating a correction current and making it fed back to the reference voltage generation circuit. The correction circuits generate sub correction currents which monotonously increase from predetermined temperature which varies among the correction circuits toward a low-temperature side or a high-temperature side. The correction current is sum of a plurality of sub correction currents.

Abstract: A DC-DC power converter used in an electromagnetic flowmeter supplies a constant current from a capacitive output to an excitation coil during a measurement portion of the operating cycle. During a relatively longer charging portion of the operating cycle the capacitive output is charged from an unregulated supply. When the unregulated supply voltage of the of the DC-DC converter is less than the regulated output voltage repeated high voltage pulses are generated by the excitation coil to charge the output capacitor.

Abstract: The present invention provides a voltage generation circuit which outputs high-precision output voltage in a wide temperature range. A semiconductor device has a voltage generation circuit. The voltage generation circuit has a reference voltage generation circuit which outputs reference voltage, and a plurality of correction circuits for generating a correction current and making it fed back to the reference voltage generation circuit. The correction circuits generate sub correction currents which monotonously increase from predetermined temperature which varies among the correction circuits toward a low-temperature side or a high-temperature side. The correction current is sum of a plurality of sub correction currents.

Abstract: A voltage regulator is provided which can suppress an occurrence of overshooting in an output voltage at the time of starting a power source with a source voltage or the like. The voltage regulator includes an error amplifier circuit, an overshooting control circuit that is connected to the gate of an output transistor, and an ON/OFF circuit that controls ON and OFF states of at least the error amplifier circuit. Here, the ON/OFF circuit controls the overshooting control circuit so as to turn on the output transistor when a predetermined time passes after at least the error amplifier circuit is turned on at the time of starting the voltage regulator.

Abstract: In one embodiment, an integrated circuit current mirror circuit is disclosed. The integrated circuit current mirror circuit includes a reference circuit, an output circuit and a mode selector circuit. The reference circuit includes an input terminal that receives a reference current. The output circuit generates an output current that is proportional to the reference current. The output circuit is coupled to a load circuit. The output current is provided to the load circuit. The mode selector circuit is coupled to the reference circuit and the output circuit. The mode selector circuit receives a plurality of mode control signals having different voltage levels. The mode selector circuit selects one of the mode control signals. The selected mode control signal is routed to the reference circuit and the output circuit to place the current mirror circuit in a desired mode.

Abstract: A circuit is provided, including a first resistor, a second resistor which may have an adjustable resistance, and a control unit. The control unit may be configured to adjust the second resistor to have a first resistance at which a voltage due to a first current flowing through the first resistor is equal to a voltage due to a second current flowing through the second resistor. The control unit may be further configured to adjust the second resistor to have a second resistance at which a voltage due to another first current different from the first current and flowing through the first resistor is equal to the voltage due to the second current flowing through the second resistor. The control unit may be further configured to adjust the second resistor to have a third resistance based on at least a difference of the first resistance and the second resistance.