With Additional Stage Patents (Class 323/314)
  • Patent number: 10175711
    Abstract: In some examples, a device includes a curvature-correction circuit including a first current source configured to generate a PTAT electrical current. In some examples, the curvature-correction circuit also includes three or more programmable current sources configured to generate three or more programmable electrical currents. In some examples, the curvature-correction circuit is configured to generate a PWL electrical current based on the PTAT electrical current and the three or more programmable electrical currents. In some examples, the device also includes a reference voltage circuit configured to generate a reference voltage signal based on the PWL electrical current.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: January 8, 2019
    Assignee: Infineon Technologies AG
    Inventors: Luca Petruzzi, Anthony Candage
  • Patent number: 10139883
    Abstract: A power system includes a voltage detection IC which outputs a reset signal to a microcomputer when an input voltage is equal to or lower than a reset release voltage, releases outputting of the reset signal when the input voltage exceeds the reset release voltage, and outputs the reset signal to the microcomputer again after the input voltage exceeds the reset release voltage when the input voltage is equal to or lower than a reset detection voltage which is lower than the reset release voltage and a voltage conversion circuit which sets a first voltage associated with a change of a power voltage as the input voltage before start of operation of the microcomputer and sets a second voltage which is associated with a change of the power voltage and is lower than the first voltage as the input voltage after the start of operation the microcomputer.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: November 27, 2018
    Assignee: Alpine Electronics, Inc.
    Inventor: Hideaki Sato
  • Patent number: 10141924
    Abstract: A semiconductor circuit including a PMOS transistor that includes a first source connected to a power supply, a first drain, and a first gate to which a fixed potential is supplied; an output circuit that outputs a first output signal, which is a reset signal or a power-on signal, and that outputs a second output signal according to a potential of the first drain; a constant current source connected to the first drain; and an NMOS transistor that includes a second source to which a fixed potential is supplied, a second drain connected to the first drain, and a second gate to which the second output signal from the output circuit is applied.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: November 27, 2018
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Takashi Takemura
  • Patent number: 10135615
    Abstract: Systems and methods for providing assistance for performing a physically unclonable function (PUF) are provided. Disclosed systems can include a PUF bitcell including at least two voltage-compensated proportional-to-absolute (PTAT) generators, each of which can be configured to generate a first voltage and a second voltage that is different from the first voltage by a voltage difference. The voltage difference can be resistant to temperature variations and variations, if any, in the supply voltage. The system can further include a comparator, which can be electrically coupled to each of the at least two PTAT generators, and can be configured to receive the first voltage and the second voltage generated therefrom, determine a polarity of each of the voltage differences, and generate a random bit.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: November 20, 2018
    Assignee: THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK
    Inventors: Mingoo Seok, Jiangyi Li
  • Patent number: 10133293
    Abstract: A circuit can have a low mirror input voltage and fast settling while providing a large current mirror gain. The circuit can include a current source, a first current mirror device having a first transistor and a second transistor and electrically coupled with the current source, a third transistor electrically coupled with the first transistor, a second current mirror device having a fourth transistor and a fifth transistor and electrically coupled between the third transistor and the second transistor, and an output device electrically coupled with the first and second current mirror devices.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: November 20, 2018
    Assignee: Avnera Corporation
    Inventors: Garry N. Link, Wai Lee
  • Patent number: 10113982
    Abstract: Technologies including NMR logging apparatus and methods are disclosed. Example NMR logging apparatus may include surface instrumentation and one or more downhole probes configured to fit within an earth borehole. The surface instrumentation may comprise a power amplifier, which may be coupled to the downhole probes via one or more transmission lines, and a controller configured to cause the power amplifier to generate a NMR activating pulse or sequence of pulses. Impedance matching means may be configured to match an output impedance of the power amplifier through a transmission line to a load impedance of a downhole probe. Methods may include deploying the various elements of disclosed NMR logging apparatus and using the apparatus to perform NMR measurements.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: October 30, 2018
    Assignee: VISTA CLARA INC.
    Inventors: David O. Walsh, Peter Turner
  • Patent number: 10095251
    Abstract: A voltage regulating circuit provides a feedback voltage and an output voltage based on a power voltage. The voltage regulating circuit includes a reference voltage generator and a compensating circuit. The reference voltage generator receives the power voltage, produces the feedback voltage, and includes an impedance having first and second terminals. The second terminal is coupled to a ground voltage and a first current flows through the impedance at the first terminal to produce the feedback voltage. The compensating circuit includes a negative threshold voltage (NVT) transistor having a source terminal, a drain terminal and a gate terminal. The source terminal receives a power voltage, the drain terminal is connected to the gate terminal and coupled to the first terminal of the impedance through a path to add a second current to the first current when the NVT transistor is turned on under an operational condition at the FF corner.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: October 9, 2018
    Assignee: United Microelectronics Corp.
    Inventors: Chai-Wei Fu, Cheng-Hsiao Lai, Ying-Ting Lin, Yuan-Hui Chen, Ya-Nan Mou, Yung-Hsiang Lin, Hsueh-Chen Cheng
  • Patent number: 10095260
    Abstract: A start-up circuit arranged to initialize a circuit portion with a zero stable point and a non-zero stable point. The start-up circuit includes: a capacitive voltage divider including a first capacitor and a second capacitor that generate a divider bias voltage at a divider node; a differential amplifier including first and second amplifier inputs and an amplifier output connected to the divider node; a first driver transistor with its gate terminal connected to the divider node, and its drain terminal connected to a first start-up output and the first amplifier input; and a second driver transistor with its gate terminal connected to the divider node, and its drain terminal connected to a second start-up output and the second amplifier input. The differential amplifier controls the divider bias voltage and drives the circuit portion to the non-zero stable point.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: October 9, 2018
    Assignee: Nordic Semiconductor ASA
    Inventors: Phil Corbishley, Sebastian Ioan Ene
  • Patent number: 10084402
    Abstract: A stepper motor control system includes stepper motor error reduction. For example, first and second power switches respectively energize and de-energize a stepper motor coil during each cycle for pulse-width modulating (PWM) the coil current. During a cycle including a zero crossing microstep, a calibrator detects a type of a body diode effect that occurs in the second power switch when the second switch stops de-energization of the coil. A selected offset is adjusted in response to the type of detection of the body diode effect of the second power switch. Adjusting the selected offset controls the trigger time for a comparator for comparing an offset reference voltage to a motor voltage developed in response to the coil current. Progressively adjusting the selected offset over successive cycles compensates for delays of components in the PWM control loop and reduces errors resulting from, for example, process, voltage, and temperature variations.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: September 25, 2018
    Assignee: Texas Instruments Incorporated
    Inventors: Sooping Saw, Anuj Jain, Jeffrey Okyere, Wen Chao Qu
  • Patent number: 10054968
    Abstract: An integrated circuit includes a reference voltage circuit. The reference voltage circuit includes a bipolar junction transistor (BJT) configured to receive a first current during a first phase of a clock cycle to generate a first base-emitter junction voltage, and receive a second current during a second phase of the clock cycle to generate a second base-emitter junction voltage. The reference voltage circuit includes a switched capacitor circuit configured to provide a reference voltage associated with the first base-emitter junction voltage and the second base-emitter junction voltage.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: August 21, 2018
    Assignee: XILINX, INC.
    Inventors: Umanath R. Kamath, John K. Jennings
  • Patent number: 10038426
    Abstract: A current reference circuit includes a voltage generating device, a resistor, one or more diodes, and a thermal bridge including one or more metal alloy contacts disposed on a substrate. The voltage generating device and the resistor have similar temperature coefficients. The diodes are thermally connected to the voltage generating device through the substrate. The metal alloy contacts are coupled between the diodes and the resistor. The diodes form a reverse bias junction when the compensation circuit is energized such that the thermal bridge may provide thermal conduction between the voltage generating device and the resistor.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: July 31, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Jacques Jean Bertin
  • Patent number: 10027291
    Abstract: A power amplification circuit that includes: a capacitor element in which a first metal layer, a first insulating layer, a second metal layer, a second insulating layer and a third metal layer are sequentially stacked, the capacitor element including a first capacitor in which the first metal layer serves as one electrode thereof and the second metal layer serves as another electrode thereof, and a second capacitor in which the second metal layer serves as one electrode thereof and the third metal layer serves as another electrode thereof; and a transistor that amplifies a radio-frequency signal. The radio-frequency signal is supplied to the one electrode of the first capacitor. The other electrode of the first capacitor and the one electrode of the second capacitor are connected to a base of the transistor, and the other electrode of the second capacitor is connected to the emitter of the transistor.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: July 17, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Satoshi Goto
  • Patent number: 10013013
    Abstract: One example discloses a voltage reference, including: a bandgap circuit core having a first intermediate bandgap voltage output, a second intermediate bandgap voltage output, and a bandgap voltage reference output; an amplifier having a first input, a second input, an input offset, an output, and an input_offset_trim; a trim controller; a switch matrix coupled between the bandgap circuit, the amplifier and the trim controller; wherein the switch matrix has a functional configuration and a calibration configuration; wherein in the functional configuration of the switch matrix, the first intermediate bandgap voltage output is coupled to the first input of the amplifier and the second intermediate bandgap voltage output is coupled to the second input of the amplifier; and wherein in response to the calibration configuration of the switch matrix, the trim controller is coupled to adjust the input offset of the amplifier using the input_offset_trim.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: July 3, 2018
    Assignee: NXP B.V.
    Inventors: Klaas Wortel, Jan Inghels, Henri Verhoeven
  • Patent number: 10007289
    Abstract: A high precision voltage reference circuit is disclosed which replaces two current bias sources, with a single current mirror. Curvature-error correction is established with a modified current mirror circuit. Another object of this disclosure is the addition of a MOSFET device, to alleviate the output voltage variation, due to the channel modulation effect of the origin of the voltage reference.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: June 26, 2018
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Susumu Tanimoto, Soichiro Ohyama
  • Patent number: 10001793
    Abstract: An apparatus is described comprising a bandgap reference circuit comprising: an amplifier including first and second inputs and an output; and a bandgap transistor coupled to the output of the amplifier at a control electrode thereof, the bandgap transistor being further coupled commonly to the first and second inputs of the amplifier at a first electrode thereof to form a feedback path. The apparatus further comprises a resistor coupled to the first electrode of the bandgap transistor.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: June 19, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Wei Lu Chu, Dong Pan
  • Patent number: 9984624
    Abstract: A semiconductor device includes first to fourth terminals, a switch circuit, and an integrating circuit. The integrating circuit includes an amplifier circuit having a (?) terminal, a first (+) terminal, and a second (+) terminal. The integrating circuit is configured to integrate an input signal of the (?) terminal using an average voltage of a voltage of the first (+) terminal and a voltage of the second (+) terminal as a reference voltage. The switch circuit is configured to electrically connect the (?) terminal to the second terminal, the first (+) terminal to the first terminal, the second (+) terminal to the third terminal the (?) terminal to the third terminal, the first (+) terminal to the second terminal, and the second (+) terminal to the fourth terminal. The present semiconductor device is used as a semiconductor device sensing a current flowing through a pixel in a display panel.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: May 29, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kei Takahashi, Roh Yamamoto
  • Patent number: 9983614
    Abstract: A reference circuit includes a bandgap core circuit and a cascode amplifier. The bandgap core circuit includes a first bipolar junction transistor (BJT), a second BJT having a control electrode coupled to a control electrode of the first BJT, a first resistor coupled to the first BJT and the second BJT, and a second resistor coupled to the second BJT. The cascode amplifier circuit includes a first branch coupled to the first BJT and a second branch coupled to the second resistor.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: May 29, 2018
    Assignee: NXP USA, INC.
    Inventors: John M. Pigott, Ivan Victorovich Kochkin, Hamada Ahmed
  • Patent number: 9966048
    Abstract: A memory is provided, which comprises an electrically erasable and programmable read only memory (EEPROM) configured to store an operation system and to be rewritable in response to a write operation signal, an address comparator configured to be connected to Inter Integrated Circuit (I2C) lines and output the write operation signal to the EEPROM in response to an external signal, a digital-to-analog converter (DAC) unit configured to determine whether to connect a DAC resistor and the I2C lines in response to the external signal and a pull-up resistor unit configured to be connected to the I2C lines.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: May 8, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yun Mi Kim, Ki Hyun Pyun, Sung Jun Kim, Min Young Park, Jeong Doo Lee, Kyung Hwa Lim
  • Patent number: 9953980
    Abstract: In an output amplifier stage of an operational amplifier circuit, the first p-well of the first nMOSFET and the second p-well of the second nMOSFET are connected to the fourth node. Further, the first n-well of the first pMOSFET and the second n-well of the second pMOSFET are connected to the fifth node. At least one of the fourth node and the fifth node is connected to an output terminal VOUT.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: April 24, 2018
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Takayuki Nakai
  • Patent number: 9886047
    Abstract: As one example of the invention disclosed herein, a reference voltage generation circuit has: a first reference voltage source generating a first reference voltage; a second reference voltage source generating a second reference voltage having a temperature response different from that of the first reference voltage; a first comparator comparing the first and second reference voltages to generate a first comparison signal; and a selector selectively outputting one of the first and second reference voltages as a reference voltage according to the first comparison signal.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: February 6, 2018
    Assignee: Rohm Co., Ltd.
    Inventors: Yusuke Yoshii, Yuki Inoue
  • Patent number: 9851739
    Abstract: Circuits for generating a PTAT voltage as a base-emitter voltage difference between a pair of bipolar transistors. The circuits may form unit cells in a cascading voltage reference circuit that increases the PTAT voltage with each subsequent stage. The bipolar transistors are controlled using a biasing arrangement that includes an MOS transistor connected to a current mirror that provides the base current for the bipolar transistors. A voltage reference is formed by combining a PTAT voltage and a CTAT voltage at the last stage. The voltage reference may be obtained from the voltage at an emitter of one of the bipolar transistors in the last stage.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: December 26, 2017
    Assignee: ANALOG DEVICES, INC.
    Inventor: Stefan Marinca
  • Patent number: 9851731
    Abstract: A bandgap voltage generator includes a plurality of calibration transistors. A test circuit measures the bandgap reference voltage generated by the bandgap voltage generator and enables a subset of the calibration transistors to correct to the bandgap reference voltage.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: December 26, 2017
    Assignee: STMicroelectronics International N.V.
    Inventors: Rajeev Jain, Chandrajit Debnath
  • Patent number: 9811107
    Abstract: A bias current generators that may be implemented in low power environments is described. The current generator can be implemented without using resistors and may be used to generate reference currents and voltages. It may also be used to generate voltage references where the output of the circuit is to at least a first order temperature independent.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: November 7, 2017
    Assignee: Analog Devices Global
    Inventor: Stefan Marinca
  • Patent number: 9785178
    Abstract: A current reference generator includes a first voltage reference configured to generate a first current through a first resistor; a second voltage reference configured to generate a second current; a first current mirror configured to subtract the second current from the first current to generate a temperature invariant current; a third voltage reference configured to generate a third current via a second resistor; and a second current mirror configured to: subtract the temperature invariant current from the third current to produce a process-temperature invariant current, and output the process-temperature invariant current.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: October 10, 2017
    Assignee: KING ABDULAZIZ CITY FOR SCIENCE AND TECHNOLOGY
    Inventors: Mohammed Sulaiman BenSaleh, Syed Arsalan Jawed, Yasir Mehmood Siddiqi, Abdulfattah Mohammad Obeid, Ahmed Kassem, Shahab Ahmed Najmi, Syed Manzoor Qasim
  • Patent number: 9755628
    Abstract: A driving circuit includes a main output terminal electrically coupled to a switch element, a first voltage generating circuit and a second voltage generating circuit. The first voltage generating circuit is electrically coupled with the main output terminal. The first voltage generating circuit comprises a first comparator and a voltage divider circuit. The first voltage generating circuit is configured to generate a first voltage at the main output terminal during a predetermined time interval of a turn-on duration of a switching period. The second voltage generating circuit is electrically coupled with the main output terminal. The second voltage generating circuit is configured to generate a second voltage at the main output terminal during a remaining time interval of the turn-on duration of the switching period. The predetermined time interval is ahead of the remaining time interval, and the first voltage is higher than the second voltage.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: September 5, 2017
    Assignee: DELTA ELECTRONICS, INC.
    Inventor: Chih-I Hu
  • Patent number: 9746871
    Abstract: A current mirror circuit provides a current to drive a load. A noise cancelling circuit is provided to keep the load current constant in spite of variations in the supply voltage. The noise cancelling circuit includes an auxiliary current path which branches from the load current path. The length-to-width ratios of transistors of the circuit are selected to provide the desired noise cancellation while maintaining device stability.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: August 29, 2017
    Assignee: STMicroelectroinics International N.V.
    Inventors: Nitin Gupta, Abhirup Lahiri
  • Patent number: 9658637
    Abstract: A proportional to absolute temperature (PTAT) circuit is provided. By judiciously combining circuit elements into two or more cell it is possible to effectively dump bias current into impedance resistive element of a first cell from other cells of the circuit. As a result the circuit as a whole can operate with smaller resistive elements and therefore occupy less area when implemented in silicon. It is also possible to reduce the supply current that is required for providing specific output currents or voltages.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: May 23, 2017
    Assignee: Analog Devices Global
    Inventor: Stefan Marinca
  • Patent number: 9608630
    Abstract: Devices and methods for operating devices are provided, such as those that include a memory device having a reference voltage (Vref) circuit that has substantially similar paths and impedances as an on-die termination (ODT) circuit. One such Vref circuit tracks supply variations and temperature changes in a manner substantially similar to the ODT circuit. In some embodiments an update scheme is provide for the ODT circuit and the Vref circuit to enable simultaneous update of each circuit through the same digital codes.
    Type: Grant
    Filed: May 6, 2009
    Date of Patent: March 28, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Timothy M. Hollis
  • Patent number: 9588538
    Abstract: A reference voltage generation circuit, including a first current source in series with a first bipolar transistor; a second current source in series with a first resistor; a third current source in series with a second bipolar transistor, the third current source being assembled as a current mirror with the first current source; a second resistor between the base of the second bipolar transistor and the junction point between the current source and the first resistor; and a fourth current source in series with a third resistor, the junction point between the fourth current source and the third resistor defining a reference voltage terminal.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: March 7, 2017
    Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Jean-Pierre Blanc, Pratap Narayan Singh
  • Patent number: 9584133
    Abstract: An oscillator system addresses power supply noise and temperature dependence. The system includes a multi-stage regulator circuit that receives a supply voltage and generates a lower voltage oscillator supply voltage that is less noisy than the supply voltage. A charge pump circuit receives the oscillator supply voltage and the oscillator output signal and supplies the regulator circuit with a boosted voltage. A reference generator circuit supplies a reference signal that is used to determine the oscillator supply voltage. The reference signal varies with temperature and is used to offset the temperature coefficient of the oscillator.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: February 28, 2017
    Assignee: Silicon Laboratories Inc.
    Inventors: Volodymyr Kratyuk, Jeffrey L. Sonntag, Aaron J. Caffee
  • Patent number: 9568935
    Abstract: A current detection circuit includes a first detection circuit, a second detection circuit, and a control selection circuit. The first detection circuit electrically connects between an input terminal and an output terminal and outputs a first detection signal. The second detection circuit electrically connects between the input terminal and the output terminal and outputs a second detection signal. The control selection circuit electrically connects the output terminal, the first detection circuit, and the second detection circuit and selects one of the first and second detection signals as a detection signal.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: February 14, 2017
    Assignee: Fitipower Integrated Technology, Inc.
    Inventors: Chih-Ho Lin, Wen-Yen Lee, Yi-Sheng Liu, Chio-Yi Ho
  • Patent number: 9564888
    Abstract: A voltage generation apparatus may include an external voltage sensing circuit configured to generate a first start signal and a second start signal by sensing the magnitude of a first external voltage and the magnitude of a second external voltage. The voltage generation apparatus may include an internal voltage sensing circuit configured to generate a voltage generation signal by comparing an internal voltage with a target voltage. The voltage generation apparatus may include a voltage pumping circuit configured to be activated in response to the first start signal, configured to perform a pumping operation based on the voltage generation signal, and configured to generate the internal voltage. The voltage generation apparatus may include a voltage regulating circuit configured to be activated in response to the first and second start signals, and configured to generate the internal voltage based on the voltage generation signal.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: February 7, 2017
    Assignee: SK HYNIX INC.
    Inventors: Hyun Ju Ham, Kee Teok Park, Hyung Sik Won
  • Patent number: 9547320
    Abstract: A power supply circuit includes: a depression mode transistor that includes a field plate; an enhancement mode transistor to which a source electrode and a drain electrode of the depression mode transistor are coupled; and a constant current source that is coupled to a connection node between the depression mode transistor and the enhancement mode transistor.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: January 17, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Tadahiro Imada
  • Patent number: 9465057
    Abstract: A current measuring circuit for providing a current flow signal indicative of current flow between a first terminal and a second terminal includes a main transistor, a sense transistor, a bypass switch, an output amplifier for providing a current flow signal, and a controller for enabling current flow through each of respective drain-source paths of the main and sense transistors or a controllable conduction path of the bypass switch.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: October 11, 2016
    Assignee: NXP B.V.
    Inventor: Steven Aerts
  • Patent number: 9442502
    Abstract: A voltage regulator includes an operational amplifier, a transistor, a first resistor, a second resistor, an output voltage delaying circuit and a selecting circuit. The output voltage delaying circuit receives an output voltage and generates a delayed output voltage. A first input terminal of the selecting circuit receives a reference voltage. A second input terminal of the selecting circuit receives the delayed output voltage. An output terminal of the selecting circuit generates a control voltage to a first input terminal of the operational amplifier. If the reference voltage is larger than the delayed output voltage, the selecting circuit selects the delayed output voltage as the control voltage. If the reference voltage is smaller than the delayed output voltage, the selecting circuit selects the reference voltage as the control voltage.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: September 13, 2016
    Assignee: Faraday Technology Corp.
    Inventor: Chi-Yang Chen
  • Patent number: 9436204
    Abstract: A band-gap referenced voltage circuit with smaller parasitic resistance which brings reduced band-gap error is disclosed. This reduced error stems from the unique configuration of stacked diode and a shorter wiring line to a resistor. The band-gap referenced voltage circuit includes two diodes, an operational amplifier with non-inverting and inverting inputs and an output for the band-gap voltage output, and three resistors. Employing the stacked configuration of the diode with the top anode electrode, the wiring line which connects the non-inverting input of the operational amplifier and the voltage reference diode is made short. Then the resistance of the wiring line, called also parasitic resistance, would be small.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: September 6, 2016
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Terukazu Nagakura, Tadashi Matsuoka, Fuminori Morisawa
  • Patent number: 9401188
    Abstract: Examples of devices and systems including enabling circuits are described. Two voltage supplies may be used to operate different portions of the devices, including peripheral circuits and I/O circuits. When the voltage supply to the peripheral circuits of one or more devices is disabled, the I/O circuits of that device may be disabled. In some examples, power may advantageously be saved in part by eliminating or reducing a DC current path through the I/O circuits.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: July 26, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Toru Tanzawa, Ali Feiz Zarrin Ghalam
  • Patent number: 9377805
    Abstract: Embodiments may include a method, system and apparatus for providing a reference voltage supply. A series resistor is provided between a power supply and a bandgap circuit coupled to an amplifier. A shunt transistor circuit is operatively coupled to the series resistor. A programmable output voltage is provided based upon the shunt transistor circuit and a first value of the series resistor.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: June 28, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Raymond Louis Barrett, Jr., Mark Chirachanchai
  • Patent number: 9372496
    Abstract: The invention relates to an electronic device with a bandgap reference generator including a first path with series connection of a first bipolar transistor, a first resistor and a second resistor, and a second path with series connection of a second bipolar transistor and a third resistor. The first and second paths are supplied current via a common node through a fourth resistor controlled by an amplifier sensing voltage drops within the first and second paths. A curvature compensation stage compensates for a variation of base emitter voltage of the bipolar transistors by drawing a compensation current from the common resistor node.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: June 21, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Matthias Arnold
  • Patent number: 9356563
    Abstract: An analog baseband filter for a radio transceiver is provided. An analog baseband filter for a multi-mode multi-band radio transceiver includes a current-voltage conversion amplifier converting a current received at the analog baseband filter into a voltage and adjusting a gain of an output voltage of the current-voltage conversion amplifier using a plurality of resistors, and a source follower circuit compensating for temperature for the output voltage of the current-voltage conversion amplifier.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: May 31, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Kwon Kim, Jong-Woo Lee, Jae-Hyun Lim
  • Patent number: 9323274
    Abstract: A reference voltage generator is provided. In an example, the reference voltage generator includes a temperature-dependent device, a processing module configured to process a digital representations of first and second voltages derived from the temperature-dependent device and a reference voltage to determine a value, and a digital to analog converter (DAC) configured to generate a reference voltage based on the value. The first voltage is proportional to absolute temperature (PTAT) and the second voltage is complementary to absolute temperature (CTAT) and the reference voltage is substantially independent of absolute temperature in an operating temperature range of the reference voltage generator.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: April 26, 2016
    Assignee: ATI Technologies ULC
    Inventors: Grigori Temkine, Filipp Chekmazov, Oleg Drapkin
  • Patent number: 9300248
    Abstract: A wiring pattern for oscillation input signal and a wiring pattern for oscillation output signal are provided on a printed circuit board, and a wiring pattern for ground power source voltage is arranged in a region therebetween. A quartz crystal unit is connected between the wiring pattern for oscillation input signal and the wiring pattern for oscillation output signal and one ends of capacitors serving as load capacitors thereof are connected to the wiring pattern for ground power source voltage. Further, a wiring pattern for VSS is arranged so as to enclose these wiring patterns, and a wiring pattern for VSS is arranged also in a lower layer in addition thereto. By this means, reduction of a parasitic capacitance between an XIN node and an XOUT node, improvement in noise tolerance of these nodes and others can be achieved.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: March 29, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Osamu Ozawa, Masashi Horiguchi, Yuichi Okuda, Akihito Anzai
  • Patent number: 9162615
    Abstract: A direction indicator circuit for controlling a direction indicator may include: a first terminal for connecting to a supply voltage terminal; a second terminal for connecting to a direction indicator switch and a lighting means; a third terminal for connecting to a capacitor; wherein the direction indicator circuit is designed to provide the lighting means with a current during an on state and with no current during an off state, wherein the duration of the on state and the duration of the off state are determined by a voltage at the capacitor; wherein the direction indicator circuit has a first and a second circuit, wherein the capacitor provides the supply voltage for the first and second circuits during the on state; wherein the current which flows through the first circuit has a negative temperature coefficient, and the current which flows through the second circuit has a positive temperature coefficient.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: October 20, 2015
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Gebhart Dippold, Robert Illing, Alexander Mayer, Albino Pidutti
  • Patent number: 9141019
    Abstract: A power-supply device includes: a rectifier circuit configured to output a rectified voltage by rectifying an output from a transformer; a comparator circuit configured to compare a comparison voltage corresponding to an output voltage or an output current that are generated based on the rectified voltage with the indicator voltage and to control an operation of the transformer drive circuit so as to reduce the difference between the comparison voltage and the indicator voltage; a constant voltage element configured to limit the output voltage or the output current by operating as a constant voltage source when the value of the output voltage or the output current reaches a threshold; and a current mirror circuit. The current mirror circuit is configured to lower the indicator voltage by allowing a current proportional to the current flowing through the constant voltage element to flow through the current path.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: September 22, 2015
    Assignee: Oki Data Corporation
    Inventor: Toru Kosaka
  • Patent number: 9130452
    Abstract: There is provided a gate driving device, including: an inverter arm including a high-side switch and a low-side switch; a gate driving unit receiving an instruction signal to provide switching control to the inverter arm, outputting a control signal to control switching of the inverter arm, and including a plurality of gate drivers; and a balancing unit causing voltage applied to the plurality of gate drivers to be divided to be supplied to respective gate drivers among the plurality of gate drivers, according to the switching of the inverter arm based on the control signal.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: September 8, 2015
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Won Jin Cho, Dong Hwan Kim, Min Hyuk Jung, Bum Seok Suh, Ji Yeon Oh
  • Patent number: 9122290
    Abstract: A circuit for generating a temperature-stabilized reference voltage on a semiconductor chip includes a differential amplifier having a first input, a second input and an output. The circuit further includes a CTAT circuit configured to generate a CTAT voltage at an output thereof. A first resistor is coupled between the output of the differential amplifier and the output of the CTAT circuit. Further, the first resistor is connected between the first input and the second input of the differential amplifier.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 1, 2015
    Assignee: Intel Deutschland GmbH
    Inventor: Matthias Eberlein
  • Patent number: 9110485
    Abstract: A band-gap voltage reference circuit having first and second branches respectively including first and second groups of transistors of different emitter current conduction areas and current sources for running the first and second groups of transistors at different emitter current densities to generate respective base-emitter voltages, and output terminals connected to receive a regulated voltage (Vout) which is a function of the base-emitter voltages of the first and second groups of transistors. Each of the first and second groups includes at least one npn-type transistor and at least one pnp transistor connected with their emitter-collector paths in series in the respective one of the branches so as to present cumulated base-emitter voltages across the respective group.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: August 18, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Thierry Sicard
  • Patent number: 9104217
    Abstract: The invention relates to an electronic device with a bandgap reference generator including a first path with series connection of a first bipolar transistor, a first resistor and a second resistor, and a second path with series connection of a second bipolar transistor and a third resistor. The first and second paths are supplied current via a common node through a fourth resistor controlled by an amplifier sensing voltage drops within the first and second paths. A curvature compensation stage compensates for a variation of base emitter voltage of the bipolar transistors by drawing a compensation current from the common resistor node.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: August 11, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Matthias Arnold
  • Patent number: 9092045
    Abstract: Startup circuits with native transistors. In some embodiments, a startup circuit may include a first inverter configured to receive a bandgap voltage (Vbg) from a bandgap reference circuit and to produce an output voltage (VOUT), and a second inverter operably coupled to the first inverter to form a latch, the latch configured to maintain a value of VOUT, the second inverter including a native transistor, the native transistor having a gate terminal coupled to VOUT and a source terminal coupled to Vbg. In other embodiments, a method may include receiving Vbg at a startup circuit and outputting VOUT configured to change in response to Vbg rising above Vtrig or falling below Vtrig, where the power consumption of the startup circuit is based at least in part upon a voltage value applied to a source terminal of a native transistor within the startup circuit.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: July 28, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Ivan Carlos Ribeiro Nascimento
  • Patent number: 9069369
    Abstract: A voltage regulator is disclosed. The voltage regulator includes an operational amplifier (op-amp) and a voltage trim circuit. The op-amp is operable to receive a reference voltage at a first terminal. The op-amp also includes an output terminal. The voltage trim circuit is coupled between the output terminal and a second terminal of the op-amp. The voltage trim circuit is operable to modify an output voltage to be substantially equivalent with the reference voltage. The modification is performed by selecting an electrical current propagating pathway. An IC and a method to operate the voltage regulator is also disclosed.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: June 30, 2015
    Assignee: Altera Corporation
    Inventors: Ping-Chen Liu, Justin Jon Philpott, Arvind Sherigar