Abstract: Systems and methods are disclosed that may be employed to calibrate current sense circuitry of CPU core voltage (Vcore) DC/DC voltage regulation circuitry by coupling an individual Vcore phase of a VR as a current source to a VSA phase of the same VR so that the Vcore phase acts as a current sink for the coupled Vcore phase during calibration of the current sense circuitry of the individual Vcore phase.

Abstract: Disclosed herein is a device comprising a pulse trigger switch module configured to generate a first control signal in response to a first input signal value and generate the second control signal in response to a second input signal value. An on pulse generator module provides a first pulse signal having a first predetermined pulse duration in response to the first control signal and an off pulse generator module provides a second pulse signal having a second predetermined pulse duration in response to the second control signal. An on pulse switch module connects a power signal to an output in response to the first pulse signal and an off pulse switch module connects the power signal to the output in response to the second pulse signal.

Abstract: Disclosed is a voltage-current characteristic generator that includes: a voltage source; a current source; a selector for selecting and outputting the output of either the voltage source or the current source; a sensing portion, connected to an output of the selector, for outputting the output of the selector and for sensing, and feeding back, the voltage and current of the output; and a controller for receiving the voltage and current detected by the sensing portion and for setting the subsequent outputs in the voltage source and the current source, wherein, in addition to setting the subsequent outputs, the controller evaluates an operating mode wherein the subsequent output from the selector is to be from either the voltage source or the current source.

Abstract: A semiconductor device arrangement comprising a functional circuit comprising a plurality of timing components and a reference module comprising a plurality of reference components is described. Each reference component comprises a reference timing component corresponding to a timing component of the plurality of timing components and a controllable timing component. The controllable timing component is arranged to provide a delay in dependence on an applied light stimulus. A method of analyzing a performance of a functional circuit on a semiconductor device is also described. A device analysis system for analyzing a functional circuit comprising a plurality of timing components is also described.

Abstract: A high speed tuning and measuring algorithm is used for production level testing on-wafer a large number of chips. It applies to a hybrid active injection load pull test system. Using a pre-calibration of the passive tuner and the amplitude and phase settings of the active power injection signal and employing fast harmonic receiver VNA the test system is capable of executing frequency and time domain load pull measurement sets including more than 50 impedance points in a total of 1 second for quantities such as delivered input and output power, PAE, power gain and other. Overall test time, including device hoping and biasing on the automatic probe station is less than 1.5 seconds. This enables production level load pull operations.

Abstract: A jumper has a connector and a housing. The housing at least partially encloses a processor in data communication with a non-transitory memory, a global positioning system, a rechargeable battery, and a networking device. The memory comprises software instructions that, when executed by the processor, perform steps for wirelessly transmitting data to a mobile device over a network. The data indicates a jumper identification number, a location of the jumper, and a duration after which the jumper will automatically deactivate. The steps performed include the step of wirelessly outputting an alert to the mobile device when the mobile device is at a first distance from the jumper. The first distance is settable using the mobile device. The alert causes the mobile device to at least one of vibrate and ring.

Abstract: A system for analyzing a probe card comprises a signal generator adapted to generate a radio frequency test signal. a connector for inputting into the probe card the radio frequency test signal, and a detector assembly. The detector assembly comprises an RF chuck for receiving a radio frequency signal from the probe card, and a sensor configured to receive the radio frequency signal from the RF chuck. The sensor is configured to measure a magnitude of the radio frequency signal and to output a measurement signal that represents only the magnitude of the radio frequency signal. The RF chuck and the sensor are mechanically coupled.

Abstract: A device for supplying power to an inductive load includes a switching structure designed to control a current in the load, and elements for detecting anomalies designed to generate information on detection or information on non-detection of an anomaly of the short-circuit type able to occur in the cabling toward the load, in combination with information on validity of the information on non-detection of anomalies. The information on anomaly non-detection is delivered without setting the validity information if the measured current at the end of an appropriate time window is less than a given value of current.

Abstract: A readout circuit for use in an image sensor includes a sense amplifier circuit coupled to a bitline to sense analog image data from a pixel cell of the image sensor. An analog to digital converter is coupled to the sense amplifier circuit to convert the analog image data to digital image data. A ramp generator circuit is coupled to generate a first ramp signal. The analog to digital converter is coupled to generate the digital image data in response to the analog image data and the first ramp signal. A first capacitive voltage divider is coupled to the ramp generator. The first capacitive voltage divider is coupled to reduce an output voltage swing of the first ramp signal coupled to be received by the analog to digital converter to reduce noise in the first ramp signal.

Abstract: A multi-axis motor driving apparatus includes: a plurality of drivers individually connected to corresponding ones of the plurality of motors, for supplying electric power to the corresponding ones of the plurality of motors for driving; and an integrated controller for sequentially supplying electric power to the plurality of motors via the plurality of drivers, and based on detection signals of the encoders, determining for each driver whether or not there is miswiring of at least either of a motor wire that connects one of the plurality of drivers to one of the plurality of motors or a detector wire from the encoder.

Abstract: Method and apparatus for use with systems including networked resources where communication between resources is via dual packet protocols wherein a first protocol includes a frame that specifies a destination device/resource and a data field and the second protocol specifies a final destination device/resource and includes a data field, where the second packets are encapsulated in the first protocol packet frames, the method including specifying access control information for resources, for each first protocol packet transmitted on the network, intercepting the first protocol packet prior to the first protocol destination resource, examining a subset of the additional embedded packet information to identify one of the intermediate path resources and the final destination resource, identifying the access control information associated with the identified at least one of the intermediate path resources and the final destination resource and restricting transmission of the first protocol packet as a function of

Abstract: The present invention describes a method and system for optimizing a test flow within each ATE (Automated Test Equipment) station. The test flow includes a plurality of test blocks. A test block includes a plurality of individual tests. A computing system schedule the test flow based one or more of: a test failure model, test block duration and a yield model. The failure model determines an order or sequence of the test blocks. There are at least two failure models: independent failure model and dependant failure model. The yield model describes whether a semiconductor chip is defective or not. Upon completing the scheduling, the ATE station conducts tests according to the scheduled test flow. The present invention can also be applied to software testing.

Abstract: An approach for cancelling reverse reflections in very-fast transmission line pulse (VFTLP) testing of an electrostatic discharge (ESD) device in a semiconductor is provided. A method includes generating an incident pulse in a VFTLP system for applying to a device under test (DUT). The method also includes generating a delayed replica of the incident pulse. The method also includes cancelling a portion of a reverse reflection of the incident pulse by combining the delayed replica with the reverse reflection at a power divider.

Abstract: A three-dimensional integrated circuit includes a plurality of perpendicular stacked chips. Each chip of the plurality of perpendicular stacked chips includes at least one transistor, a sensing coil, and a magnetic sensor, wherein the magnetic sensor is installed above the at least one transistor and the sensing coil and the sensing coil is installed between the magnetic sensor and the at least one transistor. The chip utilizes the sensing coil to generate a magnetic field including data, and a first chip of the plurality of perpendicular stacked chips adjacent to the chip utilizes a magnetic sensor of the first chip to receive the data generated by the sensing coil of the chip through the magnetic field generated by the sensing coil of the chip.

Abstract: A system adapted to measure electrical performance of a device under test (DUT) having two or more ports includes a plurality of signal sources synchronized and configured to generated signals simultaneously, a plurality of first signal paths to obtain transmitted and reflected signals from the DUT, a plurality of second signal paths to obtain incident signals from the signal sources, and a receiver for receiving the reflected, transmitted and incident signals obtained at the first signal paths and the second signal paths. The receiver is adapted to separate the reflected and the transmitted signals obtained from each of the first signal paths. The signal sources are configured to each generate a signal having a frequency offset from each of the others of the signal sources by a known frequency delta.

Abstract: An exemplary embodiment relates to a method for detecting a failure on a differential bus comprising the steps: detecting a first signal between the bus lines, detecting a second signal between the bus lines, and detecting the failure in case the first signal and the second signal do not show the same absolute value or in case the first signal and the second signal do not show nearly the same absolute value.

Abstract: An IC, a circuitry, and an RF BIST system are provided. The RF BIST system includes a test equipment, a module circuitry, and an IC. The IC is arranged to communicate with the module circuitry by an RF signal in response to a command signal from the test equipment, determine a test result by the RF signal, and report the test result to the test equipment, wherein the module circuitry is external to the IC and the test equipment.

Abstract: A method for performing test site synchronization within automated test equipment (ATE) is presented. The method comprises controlling a plurality of test program controllers (TPCs) using a plurality of bridge controllers (BCs), wherein each TPC can initiate multiple asynchronous events. For an asynchronous event initiated by a TPC, raising a busy flag while the asynchronous event is not yet complete and de-asserting the busy flag when the asynchronous event is complete, wherein the asynchronous event corresponds to a task requiring an indeterminate amount of time. It also comprises generating a busy signal in the first BCs in response to receiving a busy flag from any of the plurality of TPCs, wherein the busy signal remains asserted while any of the plurality of TPCs asserts a busy flag. Finally, it comprises transmitting the busy signal to the plurality of TPCs, wherein the TPCs use the busy signal to synchronize operations.

Abstract: A front-end converter circuit may allow devices, e.g. oscilloscopes and digitizers, to receive input signals having a wide range of possible amplitudes while maintaining a high standardized input impedance. The converter may selectively couple, using low-voltage switches, a selected input network of two or more input networks to a virtual ground node, and a selected feedback network of two or more feedback networks to a transconductance stage input. The selected input network and selected feedback network together define a respective input signal amplitude range. The converter may also controllably adjust an AC gain of the converter to match a DC gain of the converter, and selectively couple non-selected input networks to signal ground. Output referred integrated resistor thermal noise may be reduced to a desired value by lowering the value of the transconductance stage coupled across the input of the converter (through an input resistance) and the virtual ground node.

Abstract: A semiconductor device-under-test (DUT) may be tested by an automated test system that processes test programs specifying a number of edges per tester cycle that may be greater than the number of edges the tester is capable of generating. The test system may include circuitry that reduces the number of edges in each cycle of a test program based on data specifying operation of the tester in that cycle and/or a prior cycle. Such a reduction simplifies the circuitry required to implement an edge generator by reducing the total number of timing verniers per channel. Nonetheless, flexibility in programming the test system is retained.

Abstract: Some embodiments provide methods, process, systems and apparatus for use in testing multi-axis Micro Electro Mechanical Systems (MEMS) devices. In some embodiments, methods of testing are provided, comprising: selecting, according to a test specification and a test program, at least a first MEMS device on a substrate comprising a plurality of MEMS formed relative to the substrate and applying one or more electrical probes to the first MEMS device; providing power to the first MEMS device through the one or more electrical probes; measuring output signals of the first MEMS device; applying a force to the first MEMS device using a force actuator; measuring a set of output signals of the first MEMS device based on the applied force; and processing test data and generating output test results according to the test specification and test program.

Abstract: An automatic testing equipment, an automatic testing system, an a method for controlling automatic testing thereof are disclosed. The automatic testing equipment is used for receiving a control signal to test a durability of a connecting port of a device under test (DUT). The automatic testing equipment includes a testing platform, a testing unit, and a power control unit. The testing platform is used for disposing the DUT. The testing unit includes a main body, an assembly unit, and a height adjustment unit. The assembly unit is used for assembling a test connector. The height adjustment unit is connected with the main body and works with the assembly unit to adjust a height of the assembly unit. The power control unit drives the testing unit to test the connecting port via the test connector after receiving the control signal.

Abstract: A touch testing system for a capacitive touch device and a method thereof are provided. The system includes a test fixture, at least one magnetization component, at least one magnetic induction component and a driving unit. The fixture is disposed on the touch device and has at least one chute on a position corresponding to the touching area. The magnetization component is disposed on the fixture and enabled by a driving signal to produce a magnetic force. The magnetic induction component is slidably disposed in the chute and inducts the magnetic force to slide along the chute, such that the sensing unit produces a touch testing information. The driving unit is coupled to the magnetization component and the sensing unit, provides the driving signal to enable the magnetization component and receives the touch testing information to feed back a testing result on the capacitive touch device accordingly.

Abstract: An over voltage protection testing apparatus is applied for testing an over voltage protection function of a power supply apparatus. The over voltage protection testing apparatus mainly includes a voltage boost-storage unit and an energy release unit. The voltage boost-storage unit boosts an original output voltage outputted from the power supply apparatus into a testing voltage. Therefore, no extra testing voltage source is required for testing the over voltage protection function of the power supply apparatus. Moreover, the extra energy would be released to the energy release unit after the testing of the over voltage protection function of the power supply apparatus is finished. Therefore, the energy releasing of the present invention is faster than the energy releasing of a related art.

Abstract: To verify robustness with respect to electrical overstresses of an electronic circuit under test, the latter is exposed to electrical overstresses, and the behavior thereof is monitored. In particular, both the testing of the electronic circuit in dynamic conditions is performed by causing it to be traversed by the currents that characterize operation thereof, and by exposing at least one supply line of the electronic circuit under test to electrical overstresses and the testing of the electronic circuit under test in static conditions, without causing it to be traversed by the currents that characterize operation thereof, and by exposing to electrical overstresses both the supply and the input and/or output lines of the electronic circuit under test. The device for generating the overstresses can be mounted on a circuit board, which can be coupled as daughter board to a mother board, on which the electronic circuit under test is mounted.

Abstract: A hard disk drive system including a controller and a plurality of slave testing modules located in respective components of the hard disk drive system. The controller is arranged on a printed circuit board of the hard disk drive system and is configured to transmit information from the hard disk drive system to a host device, receive information from the host device, and, using a master testing module located in the controller, provide test configuration data corresponding to the information received from the host device. Each of the plurality of slave testing modules is configured to receive the test configuration data from the master testing module and test operation of the respective component of the hard disk drive system using the test configuration data.

Abstract: A pixel array module with a self-test function including a test circuit unit, a plurality of test lines, and a pixel array is provided. The test circuit unit provides the self-test function. The test lines are connected between the test circuit unit and the pixel array. The pixel array is connected to the test circuit unit through the test lines and includes a plurality of pixels. Each pixel includes a transistor. Each transistor has a first terminal and a second terminal. Regarding each of the pixels, a driving signal of the transistor is transmitted from the first terminal to the second terminal thereof under a normal mode, and a test signal of the transistor is transmitted from the second terminal to the first terminal thereof under a test mode. Furthermore, a self-test method of the foregoing pixel array module is also provided.

Abstract: Methods and systems are disclosed that may be implemented to complete individual phase current sense calibration of a multi-phase voltage regulator (VR) and/or to detect any and all individual bad phases of such a VR by utilizing the reconfiguration capability of a digital VR controller-based VR in conjunction with an improved test process. The disclosed systems and methods may be employed in one example to identify that all individual phases of the multi-phase VR are operational to contribute to the output of the multi-phase VR using a rotating single phase operation testing mode. Individual phase current sense calibration may also be additionally or alternatively completed while the VR is operating under the rotating single phase operation mode.

Abstract: A test structure may characterize the properties of a transistor including a DC test structure for testing DC properties of the transistor, and an AC test structure for testing AC properties of the transistor. The DC and AC test structures may have common test pads.

Abstract: A test system including an embodiment having a sensor array adapted to test one or more devices under test in learning modes as well as evaluation modes. An exemplary test system can collect a variety of test data as a part of a machine learning system associated with known-good samples. Data collected by the machine learning system can be used to calculate probabilities that devices under test in an evaluation mode meet a condition of interest based on multiple testing and sensor modalities. Learning phases or modes can be switched on before, during, or after evaluation mode sequencing to improve or adjust machine learning system capabilities to determine probabilities associated with different types of conditions of interest. Multiple permutations of probabilities can collectively be used to determine an overall probability of a condition of interest which has a variety of attributes.

Abstract: A de-embed probe, including two inputs configured to connect to a device under test, a memory, a signal generator configured to output a signal, a plurality of load components, a plurality of switches, and a controller. Each load component is configured to provide a different load. A first switch of the plurality of switches is associated with the signal generator and the other switches of the plurality of switches are each associated with one load component. The controller is configured to control the plurality of switches to connect combinations of the loads from the plurality of load components and the signal from the signal generator across the two inputs.

Abstract: A test and measurement system including a device under test, two de-embed probes connected to the device under test, and a test and measurement instrument connected to the two de-embed probes. The test and measurement instrument includes a processor configured to determine the S-parameter set of the device under test based on measurements from the device under test taken by the two de-embed probes.

Abstract: A branch circuit monitoring system (BCMS) for monitoring branch circuit currents in one or more electrical circuit panels is described. The system is comprised of a data center server, one or more panel processors, each with one or more collection devices, and one or more current sensors per collection device. The BCMS is designed to be installed entirely inside the panel without the need for a dedicated enclosure or power supply to facilitate ease of installation and low-cost. The BCMS also allows for future upgradability through standard software updates so that the system can be updated or patched easily. The BCMS data center server collects, aggregates, stores, and serves historical branch circuit current data from the panel processors to networked users via a web server to provide visualization of data such as tables, charts, and gauges.

Abstract: The prediction of hardware failure is obtained by operating two redundant circuit modules while one circuit module is artificially aged. The output of the two circuit modules is compared and a discrepancy between outputs indicates a projected failure of the aged modules. Aging may be accomplished by one or a combination of lowering operating voltages and re-phasing a sampling clock to reduce slack time both of which provide increased sensitivity to gate delay.

Abstract: Test systems for characterizing devices under test (DUTs) are provided. A test system for testing a DUT in a shunt configuration may include a signal generator and a matching network that is coupled between the signal generator and the DUT and that is optimized to apply desired voltage/current stress to the DUT with reduced source power. The matching network may be configured to provide matching and desired stress levels at two or more frequency bands. In another suitable embodiment, a test system for testing a DUT in a series configuration may include a signal generator, an input matching network coupled between the DUT and a first terminal of the DUT, and an output matching network coupled between the DUT and a second terminal of the DUT. The input and output matching network may be optimized to apply desired voltage/current stress to the DUT with reduced source power.

Abstract: An apparatus for testing a cable or other capacitive load object with a VLF alternating cosine square, rectangular or trapezoidal test voltage, includes one or two DC voltage sources and a switching arrangement controlled by a measuring and control unit, to produce the test voltage with alternating switched polarity. The apparatus further includes a choke coil serving as an energy store, which is controlled by a switching element to be activated if the voltage/time slope arising during the switch-over after a respective half-wave of the test voltage falls below a defined threshold value.

Abstract: A test device includes a test unit and a voltage selection circuit. The test unit is configured to detect a voltage at a test pad of a semiconductor device under test by applying a test current to the test pad. The voltage selection circuit is configured to apply a selection voltage to a ground pad of the semiconductor device under test by selecting one of a plurality of voltages according to a test mode.

Abstract: Manufacturing of magnetometer units (20?) employs a test socket (41) having a substantially rigid body (43) with a cavity (42) therein holding an untested unit (20) in a predetermined position (48) proximate electrical connection (50) thereto, wherein one or more magnetic field sources (281, 332, 333, 334, 335, 336) fixed in the body (43) provide known magnetic fields at the position (48) so that the response of each unit (20) is measured and compared to stored expected values. Based thereon, each unit (20) can be calibrated or trimmed by feeding corrective electrical signals back to the unit (20) through the test socket (41) until the actual and expected responses match or the unit (200) is discarded as uncorrectable. In a preferred embodiment, the magnetic field sources (281, 332, 333, 334, 335, 336) are substantially orthogonal coil pairs (332, 333, 334) arranged so that their centerlines (332-1, 333-1, 334-1) coincide at a common point (46) within the predetermined position (48).

Abstract: A method for testing a multi-chip system including multiple ports is provided. The method comprises determining a test path formed by connecting the multiple ports, in which the test path is determined in such a way that the internal logic circuit of each chip in the multi-chip system is bypassed, injecting a test traffic to the test path, and receiving the test traffic from the test path.

Abstract: A circuit board includes a main part on which a processor is mounted, a cut part to be cut off from the main part at a cut section before the board is reused, and a conductor pattern wired through the cut part via the cut section and to be cut off into a plurality of patterns at the cut section as the cut part is cut off. The processor detects a difference in signal level between a level of a signal output from the conductor pattern before the cut part is cut off, and a level of the signal output from the conductor pattern after the cut part is cut off, to determine a number of times the board is reused.

Abstract: Embodiments of the invention relate to automatic test equipment for testing a circuit having an oscillating crystal and to a method for operating such automatic test equipment. A generator generates a first signal comprising an oscillating part having at least one predetermined frequency. A first terminal couples the first signal to the oscillating crystal. At least one predetermined frequency is located inside a predetermined window around one of the resonance frequencies of the oscillating crystal. An analyzer has a second terminal coupled to the oscillating crystal for detecting a second signal and a rectifier connected in series with a low-pass filter for rectifying and filtering the second signal. A detector for detects a DC-signal at the output of the low-pass filter and for signals a valid test result for the oscillating crystal if the DC-signal exceeds a certain threshold value.

Abstract: A method for pulsed behavior modeling of a device under test (DUT) using steady state conditions is disclosed. The method includes providing an automated test system (ATS) programmed to capture at least one behavior of the DUT. The ATS then generates a DUT input power pulse that transitions from a predetermined steady state level to a predetermined pulse level and back to the predetermined steady state level. At least one behavior of the DUT is then captured by the ATS while the input power is at the predetermined pulse level. The ATS then steps the predetermined pulse level to a different predetermined pulse level, and the above steps are repeated until a range of predetermined pulse levels is swept. The ATS then steps the predetermined steady state level to a different steady state level, and the above steps are repeated until a range of predetermined steady state levels is swept.

Abstract: Provided is a switching apparatus that switches a connection state between two terminals, comprising a switch that switches the connection state between the two terminals according to a control voltage supplied thereto; a driving section that provides the switch with the control voltage corresponding to a control signal supplied thereto; and a changing section that changes the control voltage output from the driving section, according to a designated switching time. The changing section may change power supplied as a power supply to the driving section, according to the designated switching time. The changing section may change the control voltage output from the driving section prior to switching of the switch.

Abstract: A method and apparatus for power glitch detection in IC's is disclosed. In one embodiment, a method includes a detection circuit in an IC detecting a voltage transient wherein a value of a supply voltage has at least momentarily fallen below a reference voltage value. Responsive thereto, the detection circuit may cause a logic value to be stored in a register indicating that the detection circuit has detected the supply voltage falling below the reference voltage. The IC may include a number of detection circuits coupled to the register, each of which may provide a corresponding indication of detecting the supply voltage falling below the reference voltage. The detection circuits may be placed at different locations, and thus reading the register may yield information indicating the locations where, if any, such voltage transients occurred.

Abstract: The Configurable Vertical Integration [CVI] invention pertains to methods and apparatus for the enhancement of yields of 3D or stacked integrated circuits and herein referred to as a CVI Integrated Circuit [CVI IC]. The CVI methods require no testing of circuit layer components prior to their fabrication as part of a 3D integrated circuit. The CVI invention uses active circuitry to configure the CVI IC as a means to isolate or prevent the use of defective circuitry. CVI circuit configuration method can be predominately described as a large grain method.

Abstract: The present invention relates to a test system for high-voltage technology devices, in particular shunt reactors, as defined in the preamble of independent patent claim 1. The invention also relates to a method which can be carried out with this test system and is intended to test high-voltage technology devices according to coordinate patent claim 5. The general idea of the test system according to the invention is to provide a continuously adjustable inductance and a capacitance, which can be adjusted in in discrete steps, on the secondary side of the test transformer in such a manner that said components form a series resonant circuit together with the test object in the form of an inductance.

Abstract: An apparatus and a method for automated testing of electrostatic discharge of a Device Under Test (DUT) are provided. In the apparatus and the method, an electrostatic pulse is applied to the DUT, a malfunction type is detected from the DUT, and a control command is transmitted to the DUT to return a test mode of the DUT to a normal mode according to the detected malfunction type.

Abstract: A method for scan-testing of an integrated circuit includes the following steps carried out by the circuit itself: upon powering on of the circuit, watching for bit sequences applied to a use pin configured for receiving serial data from the exterior at the rate of a clock signal applied to a clock pin; configuring the circuit in a test mode when a bit sequence is identified as a test initialization sequence; connecting latches of the circuit in a shift register configuration, and connecting the shift register for receiving a test vector in series from the use pin; switching the transfer direction of the use pin to the output mode for providing to the exterior serial data at the rate of the clock signal; and connecting the shift register for providing its content, as a test result set, in series on the use pin.

Abstract: A method of detecting a short circuit affecting a sensor, at least one terminal of the sensor being connected to a bias resistor, includes: applying to at least one bias resistor at least one test bias voltage having at least one predefined characteristic that is different from a corresponding characteristic of a nominal bias voltage of the resistor; measuring a resulting differential voltage across the terminals of the sensor; and as a function of at least one characteristic of the measured differential voltage corresponding to the predefined characteristic of the test bias voltages, determining whether the sensor presents a short circuit.

Abstract: A semiconductor integrated circuit includes a plurality of semiconductor chips coupled to one another through vias, wherein a lowermost semiconductor chip of the plurality of semiconductor chips is configured to generate a first test pulse signal and transmit the first test pulse signal through the via, an uppermost semiconductor chip of the plurality of semiconductor chips is configured to generate a second test pulse signal while substantially maintaining a time difference with the first test pulse signal, and to transmit the second test pulse signal through the via, and the plurality of semiconductor chips are configured to generate test result signals for determining whether the vias are defective in response to the first test pulse signal and the second test pulse signal.