Abstract: A testing apparatus includes a thermal control chamber including a test room, which temperature is controlled within a testing temperature range; a carrier frame including a direction guiding unit installed securely within the test room and formed with one guiding groove and a carrier rod extending through the guiding groove in the direction guiding unit; and a clamping unit mounted on the carrier rod for clamping a display-panel module securely, wherein, movement of the carrier rod transversely within the guiding groove relative to the direction guiding unit results in disposing the display-panel module to extend along one of several testing directions for undergoing a burn-in test.

Abstract: The present invention relates generally to a system and a method for thermal control. More particularly, the invention encompasses an apparatus for thermal control and management of at least one device under test (DUT). The inventive thermal control and management apparatus also allows for the management of a plurality of devices under test, and with each device under test having its own testing regimen. The thermal control and management of the device under test (DUT) is managed using at least one thermoelectric element or cooler (TEC), which can be used to either heat or cool the corresponding device under test (DUT).

Abstract: A method of post-processing a plurality of electronic components in a post-processing machine after fabrication of the electronic components including providing a carrier with align fixtures, which align fixtures have a clamping mechanism, actuating the clamping mechanism to enlarge a size of receptacles, each of the receptacles is assigned to one of the align fixtures and the enlarged receptacles are larger than the electronic components to be received, positioning the electronic components in the receptacles of the align fixtures, actuating the clamping mechanism to reduce a size of the receptacles so that the electronic components are aligned within the receptacles of the carrier, placing the carrier in the post processing machine, and subjecting the electronic components to operations of the post-processing machine while the electronic components maintain in aligned positions in the receptacles of the carrier.

Abstract: An electronic device test apparatus which can optimize throughput and costs is provided. An electronic device test apparatus 1 comprises: a test cell cluster 10 having cell groups 11A to 11H each of which has a plurality of test cells 20; and a conveyor apparatus 30 supplying test carriers to a plurality of the test cells 20, and each of the test cell 20 has: contactors 215; a flow path 221 connected to a vacuum pump 25 and reducing pressure in a recess 211 of a pocket 21 so as to bring external terminals 73 and the contactors 215 into contact; and a test circuit for running a test on an electronic circuit formed into a die 90.

Abstract: A new electrical recycling apparatus for AC/DC power converter is provided to recycle the electricity in direct current to the input ends of the power converter to be tested to save a stage of power converter and avoid the complicated standard and requirement that feed the electricity to the mains supply.

Abstract: A method of post-processing a plurality of electronic components in a post-processing machine after fabrication of the electronic components including providing a carrier with align fixtures, which align fixtures have a clamping mechanism, actuating the clamping mechanism to enlarge a size of receptacles, each of the receptacles is assigned to one of the align fixtures and the enlarged receptacles are larger than the electronic components to be received, positioning the electronic components in the receptacles of the align fixtures, actuating the clamping mechanism to reduce a size of the receptacles so that the electronic components are aligned within the receptacles of the carrier, placing the carrier in the post processing machine, and subjecting the electronic components to operations of the post-processing machine while the electronic components maintain in aligned positions in the receptacles of the carrier.

Abstract: A method of manufacturing a semiconductor device includes providing a wafer, forming a memory device which includes phase change material layer on the wafer, completing a wafer level process of manufacturing the semiconductor device, and performing a thermal treatment process on the wafer to densify the phase change material. To this end, the process temperature of the thermal treatment is higher than the crystallization temperature of the phase change material and lower than the melting point of the phase change material.

Abstract: Devices, methods, and systems for facilitating heat transfer around an electronic component during thermal-cycle testing are presented. A system may include a core, a plurality of solid state heating/cooling devices, and a plurality of heat sinks. The core defines one or more cavities for receiving an electronic component. The system may include an air mover and a duct. In operation, the system may cool an electronic component to sub-ambient temperatures and heat it to above the boiling point of water. A method of thermal-cycle testing may include a core defining a cavity for receiving an electronic component, selectively inducing said heating/cooling devices to operate in a heating mode or a cooling mode, and measuring and recording conditions during the test.

Abstract: The use of a power sink function in IC testing results in a simple and rapid method for testing ICs, and assembled modules, at elevated temperature profiles without the use of environmental ovens. Testing IC devices at elevated temperatures may be useful for ‘burn-in’, for ‘hot sort’ performance testing that may be used in electronic devices such as DRAM memory, logic, communication devices, and microprocessors. The power sink function may be implemented as an additional isolated area of active devices, or as a section of the circuit that is not involved in the testing procedure. Alternately, the power dissipation circuit may consist of a resistive path between two external pins that are not used for IC operation, where the resistor may be on the IC or on the package. This allows for control of the temperature level and profile by simple adjustment of the voltage between the two external pins.

Abstract: Examples of thermal contact devices and methods are shown. Compliant thermal contact devices are shown that include interleaved conducting structures to provide a high thermal conduction contact area. Selected examples include a thermal interface material located at the interleaved interface between the conducting structures. Selected examples also include designs for alternate chip orientations.

Abstract: A method includes performing a burn-in test on an integrated circuit (IC) by removing power from a first component block within the IC and applying a maximum burn-in voltage and temperature to a second component block within the IC.

Abstract: A method of iteratively screening a sample of electrolytic capacitors having a predetermined rated voltage is provided. The method can include measuring a first leakage current of a first set of capacitors, calculating a first mean leakage current therefrom, and removing capacitors from the first set having a first leakage current equal to or above a first predetermined value, thereby forming a second set of capacitors. The second set can be subjected to a burn in heat treatment where a test voltage can be applied, then a second leakage current of the second set of capacitors can be measured and a second mean leakage current can be calculated. Capacitors having a second leakage current equal to or above a second predetermined value can be removed from the second set, forming a third set of capacitors. Because of such iterative screening, the capacitors in the third set have low failure rates.

Abstract: A test apparatus includes a plurality of rails, a plurality of test zones and a movable test chamber. The test zones are located between the rails. The movable test chamber includes a passageway, at least one heat source and at least one pair of rolling balls. The heat source is used to heat the passageway. The pair of rolling balls is movably contained in two rails, so as to facilitate movement of the passageway to different test zones.

Abstract: A burn-in method includes applying a stress current for applying thermal stress to a surface-emitting semiconductor laser, measuring an operation characteristic of the surface-emitting semiconductor laser to which the stress current is applied, and making a pass/fail decision on the surface-emitting semiconductor laser on the basis of the operation characteristic measured.

Abstract: Systems, methods, and apparatuses are provided for facilitating the use of a burn in board comprising integrated circuits. An apparatus may comprise a burn in board and a plurality of integrated circuits connected to the burn in board. Each integrated circuit may be configured to at least connect to a plurality of components to be subjected to a burn in process at room temperature; receive at least one signal for testing the plurality of components during the burn in process; and transmit the at least one signal to each of the plurality of components. Corresponding systems and methods are also provided.

Abstract: Apparatus and methods are described herein for emulating the hot spot distribution of a functional test by applying vectors for structural test to an integrated circuit (IC). The affects of the hot spots can then be tested and characterized. The vectors may be generated on the IC, or may be fed to the IC via an external source.

Abstract: The present invention relates generally to a system and a method for thermal control. More particularly, the invention encompasses an apparatus for thermal control and management of at least one device under test (DUT). The inventive thermal control and management apparatus also allows for the management of a plurality of devices under test, and with each device under test having its own testing regimen. The thermal control and management of the device under test (DUT) is managed using at least one thermoelectric element or cooler (TEC), which can be used to either heat or cool the corresponding device under test (DUT).

Abstract: Disclosed is in particular a device (2) for stressing an integrated circuit (1) including an electronic chip (10) mounted in a housing (12), the device including a source (20) of thermal stress. The device (2) also includes a thermally conductive coupling member (22), designed to be thermally coupled to the source (20) of thermal stress during the stressing operation. The coupling member (22) includes an end (220) whose geometry is suitable for being introduced into an aperture with a predefined geometry, to be made in the housing (12) of the integrated circuit (1) so as to thermally couple a coupling face (222) of this end (220) with a face (102) of the electronic chip (10).

Abstract: The present invention relates to a method and apparatus for preventing untested or improperly tested printed circuit boards from being used in a fire pump control system by interrogating each printed circuit board to ensure post-assembly fitness. Exemplary embodiments of the present invention comprise retrieving test status information stored on non-volatile memory of a printed circuit board, verifying the test status information stored on the non-volatile memory of the PCB, determining if all tests performed on the PCB have passed, outputting a message regarding the status of the PCB, and continuing to interrogate each additional PCB in the fire pump controller. A pass flag is set and recorded on the non-volatile memory of a respective PCB if all tests on the respective PCB have passed. Whereas, an error flag is set and recorded on the non-volatile memory if at least one test on a respective PCB has failed.

Abstract: Provided is a semiconductor test board which includes a power supply, a first temperature resistive element and a second temperature resistive element configured to commonly receive power from the power supply and having resistances that varies with temperature, a first chip embedding unit configured to receive the power through the first temperature resistive element and having a first semiconductor package embedded therein, and a second chip embedding unit configured to receive the power through the second temperature resistive element and having a second semiconductor package embedded therein.

Abstract: A new electrical recycling apparatus for AC/DC power converter is provided to recycle the electricity in direct current to the input ends of the power converter to be tested to save a stage of power converter and avoid the complicated standard and requirement that feed the electricity to the mains supply.

Abstract: A method for self repair of a semiconductor IC is presented. An IC state is set to test/repair mode upon powering up the IC. Fuse data is loaded from an e-fuse module. Defects or faults are detected by employing a built in self test (BIST) module. The IC self repairs using redundant circuitry by employing a built in self repair (BISR) module to repair each fault using redundant circuitry. The fault locations and repair locations are stored in the e-fuse module. The semiconductor IC state is changed to mission mode.

Abstract: An IC adapted for self-monitored burn-in includes a first memory and at least one BIST circuit coupled to the memory and operative to test the IC by executing a burn-in test and to generate test results indicative of at least one parameter of the burn-in test. The test results are at least temporarily stored in the first memory as a function of a first control signal.

Abstract: A probe includes a wire and a bump, wherein the wire is formed on a substrate; and the bump is formed upon the wire. In addition, a probe block includes a plurality of probes disposed on a substrate, so that the probe block is composed of a plurality of wires and bumps. The wires are disposed on the substrate and each bump is disposed accurately upon an end of each wire. The bump and the wire of the probe in accordance with the present invention are formed jointlessly. A method of fabricating the probe is characterized in that a grayscale mask is utilized to form the wire on the substrate and form the bump upon the wire by using a single masking process.

Abstract: A method of the invention for performing burn-in test includes assembling, on a fixture stand, a plurality of light source elements and a plurality of light detectors for monitoring a light output from a corresponding one of the plurality of light source elements; and electrifying the plurality of light source elements in a state where at least the plurality of light source elements and the plurality of light detectors are immersed in an insulation liquid. Thereby, it is realized to hold a stable temperature in a short period of time, to maintain a temperature that does not deviate from normal load conditions, and to perform a sorting test between defect parts and good part for light source unit chips without causing damage to the elements.

Abstract: A circuit for controlling temperature of a semiconductor chip includes a first heating element that is built into the semiconductor chip. The first heating element generates heat to increase the temperature of the semiconductor chip. The chip also includes a temperature controller that is coupled to the first heating element and built into the semiconductor chip. The temperature controller controls the temperature to enable testing of the semiconductor chip at a desired temperature.

Abstract: A testing system for a PSU includes a test chamber and a control device. The test chamber includes a first partition with the PSU accommodated therein and a second partition with an electric load accommodated therein. The PSU is electrically connected to the electric load. The control device includes a microcontroller unit (MCU). The MCU is connected to a setting circuit and a temperature sensing circuit. The setting circuit is configured to set one of predetermined parameters. The temperature sensing circuit is capable of sensing temperature in the test chamber. The MCU is capable of automatically controlling a predetermined temperature in the test chamber and presetting a test time for testing the PSU.

Abstract: A testing apparatus includes a thermal control chamber including a test room, which temperature is controlled within a testing temperature range; a carrier frame including a direction guiding unit installed securely within the test room and formed with one guiding groove and a carrier rod extending through the guiding groove in the direction guiding unit; and a clamping unit mounted on the carrier rod for clamping a display-panel module securely, wherein, movement of the carrier rod transversely within the guiding groove relative to the direction guiding unit results in disposing the display-panel module to extend along one of several testing directions for undergoing a burn-in test.

Abstract: A continuity testing apparatus includes open/short detection circuits provided for to-be-tested terminals, respectively and configured to determine the presence or absence of at least any one of an open-circuit failure and a short-circuit failure in to-be-tested terminals. Then, the continuity testing apparatus generates detected results of the open/short detection circuits based on the condition of continuity of the to-be-tested terminals having connections to the open/short detection circuits and the detected results from the open/short detection circuits in the preceding stages, and outputs the generated detected results to the open/short detection circuits in the succeeding stages. Further, the continuity testing apparatus determines the condition of continuity based on the output from the open/short detection circuit in the last stage.

Abstract: The automatic loading and unloading of devices for burn-in testing is facilitated by loading burn-in boards in a magazine with the stacked boards in the magazine moved into and out of a burn-in oven by means of a trolley. The trolley can include an elevator whereby a plurality of magazines can be stacked in the oven for the simultaneous burn-in testing of devices mounted on the burn-in boards. Each board has rollers on one end which are engagable by pneumatically actuated cam mechanisms for inserting the board into an electrical contact in the oven for burn-in tests. Preferably, the cam mechanisms allow for extraction of a single board for inspection.

Abstract: A method of accelerating the aging of a laser to thereby determine the reliability of the laser. The method includes an act of providing a laser die for reliability testing, an act of applying a plurality of short signal pulses to the laser die so as to simulate the aging of the laser die, and an act of ascertaining the reliability of the laser die based on its response to the plurality of short signal pulses.

Abstract: An accelerated failure indicator embedded on a semiconductor chip includes an insulating region; a circuit located inside the insulating region; a heating element located inside the insulating region, the heating element configured to heat the circuit to a temperature higher than an operating temperature of the semiconductor chip; and a reliability monitor configured to monitor the circuit for degradation, and further configured to trigger an alarm in the event that the degradation of the circuit exceeds a predetermined threshold. A method of operating an accelerated failure indicator embedded on a semiconductor chip includes determining an operating temperature of the semiconductor chip; heating a circuit located inside an insulating region of the accelerated failure indicator to a temperature higher than the determined operating temperature; monitoring the circuit for degradation; and triggering an alarm in the event that the degradation of the circuit exceeds a predetermined threshold.

Abstract: The invention relates to a tester apparatus of the kind including a portable supporting structure for removably holding and testing a substrate carrying a microelectronic circuit. An interface on the stationary structure is connected to the first interface when the portable structure is held by the stationary structure and is disconnected from the first interface when the portable supporting structure is removed from the stationary structure. An electrical tester is connected through the interfaces so that signals may be transmitted between the electrical tester and the microelectronic circuit to test the microelectronic circuit.

Abstract: An improved structure of a burn-in oven includes a housing, a loading support, a cooling-fan assembly, and a motor-fan assembly. A circuit-board-space and an exhaust channel are defined inside of the housing, wherein the exhaust channel is provided with a plurality of venting holes such that the circuit-board-space and the exhaust channel are communicated with each other through the venting holes. The loading support is disposed in the circuit-board-space for loading a plurality of circuit boards. The cooling-fan assembly is arranged at one side of the loading support and beside the exhaust channel. The motor-fan assembly is arranged at the exhaust channel. Thereby, a phenomenon of heat accumulation locally at a back panel side of the oven can be improved so as to enhance cooling effect of the oven, let alone the number of fans installed on the oven can be decreased.

Abstract: The automatic loading and unloading of devices for burn-in testing is facilitated by loading burn-in boards in a magazine with the stacked boards in the magazine moved into and out of a burn-in oven by means of a trolley. The trolley can include an elevator whereby a plurality of magazines can be stacked in the oven for the simultaneous burn-in testing of devices mounted on the burn-in boards. Each board has rollers on one end which are engagable by pneumatically actuated cam mechanisms for inserting the board into an electrical contact in the oven for burn-in tests. Preferably, the cam mechanisms allow for extraction of a single board for inspection.

Abstract: Method and apparatus for self-regulated burn-in of an integrated circuit (IC) is described. One embodiment of a method of burn-in for the IC includes: configuring programmable resources of the IC device based on a burn-in pattern to implement a load controller, the load controller having a plurality of heat core circuits. The load controller is initialized with a number of enabled heat core circuits of the plurality of heat core circuits. A junction temperature is measured in the IC device after a measurement period has elapsed. The junction temperature is compared with a set-point temperature. The number of the enabled heat core circuits is increased if the junction temperature is less than the set-point temperature, or the number of the enabled heat core circuits is decreased if the junction temperature is greater than the set-point temperature.

Abstract: A method for characterizing the electronic properties of a solar cell to be used in a photovoltaic module comprises the steps of performing a room temperature IV curve measurement of the solar cell and classifying the solar cell based on this IV curve measurement. In order to take stress-related effects into account, the solar cells are reclassified depending on the result of an additional measurement conducted on the solar cells under stress. This stress-related measurement may be gained from light induced thermography (LIT) yielding information on diode shunt areas within the solar cell.

Abstract: A method of performing a wafer level burn-in test for a plurality of surface-emitting laser devices formed on a wafer includes causing a plurality of contact electrodes arranged in a same plane with a pitch same as that of the surface-emitting laser devices being electrically connected to each other to have contact with pad electrodes of the surface-emitting laser devices, respectively, and applying a current to second electrodes of the surface-emitting laser devices and the contact electrodes. The wafer level burn-in test is performed while heating the wafer at a predetermined temperature. Laser lights emitted from the surface-emitting laser devices are monitored during the wafer level burn-in test.

Abstract: Testing of a three-dimensional (3D) integrated circuit includes defining a first group of parts by a region and/or layer on the 3D integrated circuit. The testing further includes applying a first intensity of stress test conditions to the first group of parts. The testing also includes defining a second group of parts by a region and/or layer on the 3D integrated circuit that is different from the first group of parts. The testing further includes and applying a second intensity of stress test conditions to the second group of parts. The second intensity of stress test conditions is greater than the first intensity and is determined by sensitivities identified for each of the first and second group of parts. A determination is made whether the 3D integrated circuit passed the testing based upon results of application of the first and second intensities of stress test conditions.

Abstract: A semiconductor device comprises a burn-in test circuit configured to receive a flag signal for a burn-in test, generate a toggled output enable signal, and drive a first input/output line to toggle a signal on the first input/output line, and a switching device connected between a bit line and a second input/output line for transferring a signal on the bit line to the second input/output line in response to the output enable signal.

Abstract: Semiconductor lasers are aged to identify weak or flawed devices, resulting in improved reliability of the remaining devices. The lasers can be aged using a high-power optical burn-in that includes providing a high drive current to the lasers for a period of time, and maintaining the ambient temperature of the lasers at a low temperature. After the high-power optical burn-in, the output of the lasers can be measured to determine if the lasers are operating within specifications. Those that are not can be discarded, while those that are can be further aged using a high-temperature thermal burn-in that includes providing a drive current to the lasers while maintaining the ambient temperature of the lasers at a high-temperature.

Abstract: Methodologies and test configurations are provided for testing thermal interface materials and, in particular, methodologies and test configurations are provided for testing thermal interface materials used for testing integrated circuits. A test methodology includes applying a thermal interface material on a device under test. The test methodology further includes monitoring the device under test with a plurality of temperature sensors. The test methodology further includes determining whether any of the plurality of temperature sensors increases above a steady state.

Abstract: Operation of an internal voltage supply level (Vgg) of an IC is characterized over operating temperature or at a selected temperature to determine a temperature-equivalent internal voltage level. The internal voltage supply of the IC is set to the temperature-equivalent level, and the IC is tested at room temperature to screen for low-temperature defects or high-temperature defects.

Abstract: A burn-in system (10) includes an enclosure (12) defining a burn-in chamber (14). The enclosure (12) is configured to be mounted on a burn-in board (34) over a burn-in socket (36). A heating element (16) is configured to generate heat within the burn-in chamber (14) and a temperature sensor (18) is configured to sense a temperature within the burn-in chamber (14). An opening (24) is formed in the enclosure (12) for receiving a fluid (26). A controller (20) is configured to control the heating element (16) and fluid flow into the enclosure (12) in response to the temperature sensed by the temperature sensor (18).

Abstract: According to one embodiment of the invention, a testing apparatus for executing highly accelerated life testing on at least one test subject includes at least one structure operable to thermally stress the test subject via conduction and at least one pneumatic hammer operable to input imparting vibrations to the test subject. According to another embodiment of the invention, a method for executing highly accelerated life testing of at least one test subject includes applying a thermal stress to the test subject via conduction at a rate of change of at least 8° C. per minute and imparting vibrations to the test subject at a rate of at least 3 Gs rms.

Abstract: An equipment burn-in method, which includes the equipment undergoing treatment in an oven, the oven undergoing cycles including at least one temperature-rise and/or temperature-fall transition, for which ventilation of the equipment is cut off during at least part of a temperature transition of the oven.

Abstract: The present invention discloses a burn-in testing system including a burn-in board and a burn-in testing apparatus, the burn-in board including: a first interface component, adapted to connect with the burn-in testing apparatus for signal input and/or output between the burn-in board and the burn-in testing apparatus; and a second interface component, adapted to connect with a device under test for signal input and/or output between the burn-in board and the device, wherein the burn-in testing system further includes a pin matching unit flexibly connected with the burn-in board and adapted to adjust signal connection relationship between the first interface component and the second interface component according to a pin description of the device.

Abstract: A temperature regulation plate 106 is divided into at least two areas, a heater 408 for applying a temperature load in correspondence with such areas and its control system are divided and controlled independently to set temperatures, and a cooling source is controlled by comparing the measurements from temperature sensors 409 arranged in respective areas for controlling the heater 408 and switching the measurement for calculating the control output sequentially thus reducing variation in in-plane temperature of a wafer due to heating when an electric load is applied. Since consumption and burning of a probe are prevented, highly reliable wafer level burn-in method and apparatus can be provided.

Abstract: An exemplary apparatus for detecting defect is capable of measuring temperature characteristics of a semiconductor sample without restrictions in the movement range of a sample stage and a probe device by a temperature control device. A heater heats a sample stage, and the sample stage is cooled by a refrigerant contained in a refrigerant container through a heat transfer line connected to the sample stage, a first heat receiving portion connected to the heat transfer line, a second heat receiving portion that is detachable from the heat receiving portion, a heat transfer line connected to the heat receiving portion, and a heat transfer rod connected to the heat transfer line, thereby adjusting the temperature of a semiconductor sample held by the sample stage. The heat receiving portions are separated from each other to release the restriction of the sample stage and a probe device such that the sample stage and the, probe device can be moved in a sample chamber.

Abstract: A burn-in and electrical test system (20) includes a temperature controlled zone (22) and a cool zone (24) separated by a transition zone 25. The temperature controlled zone (22) is configured to receive a plurality of wafer cartridges (26) and connect the cartridges (26) to test electronics (28) and power electronics (30), which are mounted in the cool zone (24). Each of the wafer cartridges (26) contains a semiconductor wafer incorporating a plurality of integrated circuits. The test electronics (28) consists of a pattern generator PCB (100) and a signal driver and fault analysis PCB (102) connected together by a parallel bus (104). The pattern generator PCB (100) and the fault analysis PCB (102) are connected to a rigid signal probe PCB (104) in cartridge (26) to provide a straight through signal path.