Contact Probe Patents (Class 324/754.03)
  • Patent number: 9995770
    Abstract: One or more probe cards, wafer testers, and techniques for testing a semiconductor arrangement are provided. Testline arrangements are formed within scribe lines of a semiconductor wafer, in multiple directions, such as an x-direction and a y-direction. A wafer tester is configured to concurrently test the semiconductor arrangement in multiple directions using a multidirectional probe arrangement of a probe card. In some embodiments, a first pin arrangement of the multidirectional probe arrangement is mated with a first testline arrangement in a first direction, and a second pin arrangement of the multidirectional probe arrangement is mated with a second testline arrangement in a second direction. The wafer tester concurrently tests the semiconductor arrangement in multiple directions, such as in the first direction and the second direction, through the pin arrangements mated with the testline arrangements.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: June 12, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tseng-Chin Lo, Huan Chi Tseng, Kuo-Chuan Chang, Yuan-Yao Chang, Chien-Chang Lee
  • Patent number: 9989558
    Abstract: Probe head assemblies, components of probe head assemblies, test systems including the probe head assemblies and/or components thereof, and methods of operating the same. The probe head assemblies are configured to convey a plurality of test signals to and/or from a device under test and include a space transformer, a contacting assembly, and a riser that spatially separates the space transformer from the contacting assembly and conveys the plurality of test signals between the space transformer and the contacting assembly. The contacting assembly may include a frame that defines an aperture and has a coefficient of thermal expansion that is within a threshold difference of that of the device under test, a flexible dielectric body that is attached to the frame, maintained in tension by the frame, and extends across the aperture, and a plurality of conductive probes. The plurality of conductive probes may include a dual-faceted probe tip.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: June 5, 2018
    Assignee: Cascade Microtech, Inc.
    Inventors: Koby Duckworth, Eric Hill
  • Patent number: 9977052
    Abstract: An example test fixture, which interfaces a tester and a unit under test (UUT), includes the following: first electrical contacts that face the tester; second electrical contacts that face the UUT; a substrate made of sections of printed first material, with the first material being electrically non-conductive, and with the substrate being between the first electrical contacts and the second electrical contacts; and structures through the substrate, with the structures including sections of second material, with the second material being electrically conductive, and with at least one of the structures electrically connecting a first electrical contact and a second electrical contact.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: May 22, 2018
    Assignee: Teradyne, Inc.
    Inventors: Anthony J. Suto, Joseph Francis Wrinn, John P. Toscano, John Joseph Arena
  • Patent number: 9972890
    Abstract: A wireless device including at least one parallel resonance element and a plurality of serial resonance components is provided. The at least one parallel resonance element may be configured to radiate in at least one frequency. The plurality of serial resonance components may be configured to radiate in a plurality of frequencies. The device may further include a distributed feed element configured to couple to the parallel resonance element and the serial resonance components and serve as a radiofrequency signal feed.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: May 15, 2018
    Assignee: Galtronics Corporation Ltd.
    Inventor: Matti Martiskainen
  • Patent number: 9928767
    Abstract: A system and method of testing chip-on-glass (COG) bonding quality automatically includes a glass panel comprising two test pads, the test pads electrically interconnected, a display driver comprising an input node and an output node, and an adhesive layer between the glass panel and the display driver, the adhesive layer binding the glass panel with the display driver, the adhesive layer comprising conductive portions across the adhesive layer between the glass panel and the display driver, wherein the input node, the output node, the two test pads, and the conductive portions are electrically connected to form an electrical testing loop, the electrical testing loop configured to measure a voltage drop across the conductive portions.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: March 27, 2018
    Assignee: Futurewei Technologies, Inc.
    Inventors: Xiangan Zhu, Guoping Luo, Qian Han, Shunlin Chen, Guangrong Wu, Jose Garcia, Steven R. Loza, Chuanning Chen
  • Patent number: 9880202
    Abstract: A probe card for an apparatus for testing electronic devices comprises at least one probe head, a plurality of contact probes housed within the probe head, each contact probe having at least one contact tip suitable to abut against contact pads of a device to be tested, a supporting plate of the probe head, an interface plate, a stiffener associating the supporting plate and the interface plate, a plurality of connecting elements with clearance disposed between the supporting plate and the interface plate and housed in a floating manner in a plurality of respective seats made in the supporting plate, and a plurality of connecting elements without clearance disposed between the interface plate and the stiffener.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: January 30, 2018
    Assignee: Technoprobe S.p.A.
    Inventors: Riccardo Vettori, Riccardo Liberini
  • Patent number: 9870959
    Abstract: Techniques for electrically testing a flip-chip assembly during its manufacture include a flip-chip assembly having an integrated circuit (IC) die and an IC package substrate. The IC package substrate is placed on a substrate part holder that includes test sockets and heating elements. The IC die is then placed on the placed IC package substrate. The placed IC die and IC package substrate are aligned such that conductive contacts are formed from conductive bumps and pads deposited on the surface of the IC die and IC package substrate. While the bumps and pads are in conductive contact, but prior to attachment, the flip-chip assembly is electrically tested. If the flip-chip assembly passes electrical testing, the conductive contacts may be attached by the heating elements on the substrate part holder, such as in a solder reflow process when the bumps are made from solder.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: January 16, 2018
    Assignee: ALTERA CORPORATION
    Inventor: Nagesh Vodrahalli
  • Patent number: 9846193
    Abstract: A semiconductor package testing apparatus comprises a package holder for holding a semiconductor package and which is positionable together with the semiconductor package at a test contactor station. There are probe pins located at the test contactor station for contacting a bottom surface of the semiconductor package and which are configured to apply an upwards force on the semiconductor package during testing of the semiconductor package. A restraining mechanism that is movable from a first position remote from the package holder and a second position over the package holder is configured to restrict lifting of the semiconductor package by the probe pins during testing of the semiconductor package when the restraining mechanism is at its second position.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: December 19, 2017
    Assignee: ASM TECHNOLOGY SINGAPORE PTE LTD
    Inventors: Chak Tong Sze, Pei Wei Tsai, Cho Hin Cheuk, Si Ming Chan, Kam Sing Lee
  • Patent number: 9843493
    Abstract: The measuring system comprises a measuring device and a device under test (9). This measuring device comprises a high-frequency processing unit (11), which is embodied to receive high-frequency signals from the device under test (9) and/or to transmit high-frequency signals to the device under test (9) via a first connection (5). The measuring system further comprises a test-software server unit (12), which is embodied to supply test-software to the device under test (9).
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: December 12, 2017
    Assignee: ROHDE & SCHWARZ GMBH & CO. KG
    Inventors: Uwe Baeder, Holger Jauch, Ingo Gruber
  • Patent number: 9804194
    Abstract: A contact for use in a test set which can be mounted to a load board of a tester apparatus. The contact, which serves to electrically connect at least one lead of a device being tested with a corresponding metallic trace on the load board, has a first end defining multiple contact points. As the test pin is rotated about an axis generally perpendicular to a plane defined by the contact, successive contact points are sequentially engaged by a lead of the device being tested. The test pin has a hard stop edge which engages a hard stop wall which limits its rotation movement. The bottom of the pin has a shallow convex curvature preferably with a flat region and the tip of the test pin has a chisel edge.
    Type: Grant
    Filed: February 28, 2016
    Date of Patent: October 31, 2017
    Assignee: Johnstech International Corporation
    Inventor: Michael Andres
  • Patent number: 9766269
    Abstract: A conductive probe may include a probe body for communicating with a circuit tester or a jumper. The probe body may be formed of metal and may have a free end. A probe tip may be mounted to the end of the probe body. The probe tip may be formed of thorium-tungsten. The probe tip may be configured for contacting a circuit node.
    Type: Grant
    Filed: December 29, 2012
    Date of Patent: September 19, 2017
    Assignee: Power Probe TEK, LLC
    Inventor: Wayne Russell
  • Patent number: 9678142
    Abstract: The present invention relates generally to testing of interconnects in a semiconductor die, and more particularly to testing of semiconductor chips that are three-dimensionally stacked via an interposer. In one aspect, a method for testing an interconnect in a semiconductor die comprises providing the semiconductor die, which includes a plurality of electrical contact elements formed at one or more surfaces of the semiconductor die, at least one interconnect-under-test disposed between a first electrical contact element and a second electrical contact element, and an electrical component electrically coupled between the interconnect-under-test and at least one third electrical contact element.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: June 13, 2017
    Assignee: IMEC
    Inventors: Julien Ryckaert, Erik Jan Marinissen, Dimitri Linten
  • Patent number: 9678110
    Abstract: A probe card includes a circuit board, a plurality of probes, and at least one deviation-compensating member. An end of each of the probes is connected to the circuit board. The deviation-compensating member is fixed to the circuit board and connected to the probes. The probes have a first thermal expansion characteristic, the deviation-compensating member has a second thermal expansion characteristic, and the first thermal expansion characteristic and the second thermal expansion characteristic are different.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: June 13, 2017
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chieh Liao, Yu-Min Sun, Chih-Feng Cheng
  • Patent number: 9632044
    Abstract: A method that includes performing multiple test iterations to provide multiple test results; and processing the multiple test results to provide estimates of a conductivity of each of the multiple bottoms segments. The multiple test iterations includes repeating, for each bottom segment of the multiple bottom segments, the steps of: (a) illuminating the bottom segment by a charging electron beam; wherein electrons emitted from the bottom segment due to the illuminating are prevented from exiting the hole; (b) irradiating, by a probing electron beam, an area of an upper surface of the dielectric medium; (c) collecting electrons emitted from the area of the upper surface as a result of the irradiation of the area by the probing electron beam to provide collected electrons; and (d) determining an energy of at least one of the collected electrons to provide a test result.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: April 25, 2017
    Assignee: APPLIED MATERIALS ISREAL LTD.
    Inventors: Alon Litman, Konstantin Chirko
  • Patent number: 9535091
    Abstract: A probe head includes a first substrate, a second substrate, a spacer, at least one probe, and an insulating material. The first substrate has at least one first through hole. The second substrate has at least one second through hole. The spacer is disposed between the first substrate and the second substrate. The spacer, the first substrate, and the second substrate together form a cavity. The probe is disposed in the cavity and protrudes from the first through hole and the second through hole. The insulating material is on the probe and at least partially disposed in the first through hole.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: January 3, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Cheng Hsu, Wen-Feng Liao, Wen-Tsai Su, Yuan-Pin Huang
  • Patent number: 9506974
    Abstract: An active probe card capable of improving testing bandwidth of a device under (DUT) test includes a printed circuit board; at least one probe needle, affixed to a first surface of the printed circuit board for probing the DUT; at least one connection member, electrically connected to the at least one probe needle; and an amplification circuit, formed on the printed circuit board and coupled to the at least one connection member for amplifying an input or output signal of the DUT.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: November 29, 2016
    Assignee: Sitronix Technology Corp.
    Inventors: Hung-Wei Lai, Tsung-Jun Lee
  • Patent number: 9459307
    Abstract: An in-circuit testing auto open and close system, apparatus and method includes an in-circuit tester having an upper panel and a lower panel, wherein the upper and lower panels are used to test electrical connections of one or more electronic units. One or more actuators are each coupled to both the upper panel and the lower panel such that they are able to move the upper and lower panels with respect to each other. As a result, a controller coupled with the in-circuit tester and the actuators is able to cause the actuators to automatically close the panels such that the panels sandwich the electronic units at the beginning of a testing program and to automatically open the panels such that the panels are separated at the end of the testing program.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: October 4, 2016
    Assignee: Flextronics AP, LLC
    Inventors: Juan Francisco Duran Hernandez, Jose Antonio Becerra Castrejon
  • Patent number: 9449920
    Abstract: An electronic device is disclosed. The electronic device comprises a transistor provided on a substrate, a transmission line provided on the substrate and connected to the transistor, an electrode pad connected to the transmission line, and a connection wiring electrically connecting the electrode pad and the transmission line through a first wiring and a second wiring. Both of the first wiring and the second wiring are connected to different positions of the electrode pad.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: September 20, 2016
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Osamu Baba, Takeshi Kawasaki
  • Patent number: 9418970
    Abstract: Redistribution layers for microfeature workpieces, and associated systems and methods are disclosed. One method for processing a microfeature workpiece system includes positioning a pre-formed redistribution layer as a unit proximate to and spaced apart from a microfeature workpiece having an operable microfeature device. The method can further include attaching the redistribution layer to the microfeature workpiece and electrically coupling the redistribution layer to the operable microfeature device.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: August 16, 2016
    Assignee: Micron Technology, Inc.
    Inventor: David Pratt
  • Patent number: 9383389
    Abstract: A prober 10 including a probe card 16 having multiple probe needles 17 includes a needle-tip polishing unit 24, and the needle-tip polishing unit 24 includes a WAPP 28 to be contacted with needle tips and a supporting member 27 configured to support the WAPP 28. On a top surface of the WAPP 28, a wrapping sheet 29 is provided, and the WAPP 28 includes multiple recesses 31 formed on a bottom surface 30 thereof and the supporting member 27 includes multiple protrusions 33 formed on a ceiling surface 32 thereof. When the WAPP 28 is moved to a retreat position, the protrusions 33 are respectively inserted and fitted into the recesses 31, and when the WAPP 28 is moved to a contact position, top portions of the protrusions 33 are respectively brought into contact with portions on the bottom surface 30 where the recesses 31 are not formed.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: July 5, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kazuya Yano, Shuji Akiyama
  • Patent number: 9354192
    Abstract: The present invention relates to a ferroelectric analyzing device and a method for adjusting ferroelectric domain switching speed with the ferroelectric analyzing device, and pertains to the technical field of characteristic test of solid-state dielectrics. The ferroelectric analyzing device comprises a voltage pulse generator for generating square pulse signal, which is biased on a ferroelectric thin film so as to switch the polarization of ferroelectric domains, the ferroelectric analyzing device further comprises a variable resistor which is connected in series with the ferroelectric thin film. The variable resistor is used for adjusting domain switching current so as to realize adjustment of domain switching speed of ferroelectric domains. In the method, the square pulse signal is biased on the ferroelectric thin film, and an adjustment of domain switching speed of ferroelectric domains can be realized by adjusting the resistance value of the variable resistor.
    Type: Grant
    Filed: April 4, 2011
    Date of Patent: May 31, 2016
    Assignee: Fudan University
    Inventors: Anquan Jiang, Xiaobing Liu
  • Patent number: 9347971
    Abstract: A probing device includes a circuit board, a reinforcing plate, at least one space transformer and at least one probe assembly. The reinforcing plate is disposed on the circuit board, and the reinforcing plate has a plurality of inner conductive wires electrically connecting to those of the circuit board. The reinforcing plate defines a plurality of receiving space therein. The space transformer is disposed on the reinforcing plate, and the space transformer has a plurality of inner conductive wires electrically connecting to those of the reinforcing plate via a plurality of first solder balls. The probe assembly is disposed on the space transformer, and the probe assembly includes a plurality of probes. The first solder balls are disposed in the receiving spaces, and the reinforcing plate abuts against the space transformer.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: May 24, 2016
    Assignee: MPI CORPORATION
    Inventors: Chien-Chou Wu, Ming-Chi Chen, Chung-Che Li
  • Patent number: 9335376
    Abstract: The disclosed ring-oscillator-based test architecture comprises a plurality of boundary scan cells coupled to a plurality of interconnects and control circuitry. Each of the plurality of boundary scan cells can be configured to operate as, based on control signals, a conventional boundary scan cell or any bit of an asynchronous counter. The control signals are supplied by the control circuitry.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: May 10, 2016
    Assignee: Mentor Graphics Corporation
    Inventors: Wu-Tung Cheng, Ruifeng Guo, Yu Huang, Liyang Lai, Jing Ye, Yu Hu
  • Patent number: 9322714
    Abstract: A method of manufacturing a particle-based image display having a plurality of imaging cells is disclosed. The method includes filling the plurality of imaging cells with a plurality of first particles, identifying a defect associated with one or more of the imaging cells, and repairing the defect within a unit corresponding to part of the plurality of imaging cells.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: April 26, 2016
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Jui-Yu Lin, Jen-Ming Chang, Jiunn-Jye Hwang, Jung-Yang Juang, Ming-Hai Chang, Hao-Jan Wan
  • Patent number: 9304341
    Abstract: A signal panel for checking images displayed on liquid crystal devices is disclosed. The signal panel includes: a power supply mainboard; a plurality of low voltage differential signaling plugs arranged on the power supply mainboard for directly engaging with the low voltage differential signaling sockets of the liquid crystal device; a plurality of low voltage differential signaling adapters arranged on the power supply mainboard for engaging with the low voltage differential signaling sockets of the liquid crystal device via the adapters; and a plurality of frequency-angle adjusting switches of the low voltage differential signals arranged on the power supply mainboard for adjusting frequency-angle parameters of the low voltage differential signals of the liquid crystal device. The signal panel can test the liquid crystal device without using connecting wires and signal generators, which effectively reduce the cost.
    Type: Grant
    Filed: December 24, 2013
    Date of Patent: April 5, 2016
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Guochuan Huang
  • Patent number: 9293074
    Abstract: An active-matrix substrate includes: a substrate; gate lines disposed on the substrate; source lines disposed on the substrate in a direction that crosses the gate lines; a first terminal provided for each of data line blocks obtained by grouping every m-lines (m being an integer greater than or equal to 2) of the source lines into a block; a first selection circuit provided for each of the data line blocks, for causing conduction between the first terminal and at least one source line selected from among the m source lines; a second terminal provided for every n-blocks (n being an integer greater than or equal to 2) of the data line blocks; and a second selection terminal provided for every n-blocks of the data line blocks, for causing conduction between the second terminal and at least one source line selected from among the m×n source lines.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: March 22, 2016
    Assignee: JOLED INC.
    Inventors: Kenichi Tajika, Hiroshi Shirouzu
  • Patent number: 9291669
    Abstract: A semiconductor device, a test structure of the semiconductor device, and a method of testing the semiconductor device are provided. The test structure including a first pad and a second pad being separated from each other, and a first test element and a second test element connected between the first pad and the second pad, a first value of a characteristic parameter of the first test element being different from a second value of the characteristic parameter of the second test element, may be provided.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: March 22, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Myoung Lee, Il-Kwon Lee, Jun-Woo Lee, Sang-Goo Jung, Kyoung-Mi Park, In-Ae Lee
  • Patent number: 9285392
    Abstract: A test fixture for testing a head gimbal assembly having a flex circuit with a plurality of circuit pads, prior to installation of the head gimbal assembly into a disc drive. The fixture comprises a contact board having a plurality of electrically conductive contact points on a surface thereof, the contact points arranged to contact the circuit pads of the flex circuit. The fixture further comprises a clamp assembly connected to the contact board, the clamp assembly having an activation end, an opposite engagement end, and a pivot axis extending orthogonal to an axis defined by the activation end and the engagement end. The engagement end has a non-conductive engagement surface configured to contact the head gimbal assembly on a surface opposite the plurality of circuit pads.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: March 15, 2016
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: David G. Wobbe, David G. Qualey
  • Patent number: 9146273
    Abstract: An embodiment for making a check of the electric type executed on wafer for testing the correct positioning or alignment of the probes of a probe card on the pads or bumps of the electronic devices integrated on semiconductor wafer. An embodiment consists in making a current circulate in at least part of the seal ring of at least one of the above devices, and in case it has to flow in the seal ring of more devices, these seal rings are suitably interconnected to each other. Thanks to an embodiment the seal ring may also be reinforced in the angle areas of the chip, and suitable circuits may be possibly inserted in the seal ring or between the seal rings.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: September 29, 2015
    Assignee: STMicroelectronics S.r.l.
    Inventor: Alberto Pagani
  • Patent number: 9105282
    Abstract: A method, related to manufacturing of head gimbal assembly (HGA) including the steps of soldering a first component on a HGA, while the HGA is mounted on an HGA mounting member and while a protective carrier bar of the HGA carrier is in a first position. The method further includes the steps of moving the protective carrier bar to a second position, and soldering a second component on the HGA while the protective carrier bar is in the second position.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: August 11, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventors: Wachira Puttichaem, Udom Konyong
  • Publication number: 20150137845
    Abstract: Methods and devices are disclosed for testing an electronic assembly comprising a number of segments. In one embodiment, a scalable periphery amplifier may comprise a number of amplifier segments. In one embodiment a method of testing the amplifier segments in a scalable periphery architecture is described. One or more of the amplifier segments can be independently turned on and/or turned off to achieve desired impedance characteristics of the overall amplifier to test the scalable periphery amplifier. In another embodiment, the electronic assembly comprises digitally tunable capacitors.
    Type: Application
    Filed: November 15, 2013
    Publication date: May 21, 2015
    Applicant: Peregrine Semiconductor Corporation
    Inventor: Chris Olson
  • Patent number: 9030219
    Abstract: A variable pressure probe pin device, including: a housing with a channel having a first longitudinal axis; a probe at least partially disposed in the channel and including a plurality of probe pins configured to measure a property of a conductive layer; and a fluid pressure system configured to supply pressurized fluid o the channel to control a position of the probe within the channel. The housing or the probe is displaceable such that the plurality of probe pins contact the conductive layer.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: May 12, 2015
    Assignee: KLA-Tencor Corporation
    Inventors: Walter H. Johnson, Nanchang Zhu
  • Publication number: 20150115990
    Abstract: A test control port (TCP) includes a state machine SM, an instruction register IR, data registers DRs, a gating circuit and a TDO MX. The SM inputs TCI signals and outputs control signals to the IR and to the DR. During instruction or data scans, the IR or DRs are enabled to input data from TDI and output data to the TDO MX and the top surface TDO signal. The bottom surface TCI inputs may be coupled to the top surface TCO signals via the gating circuit. The top surface TDI signal may be coupled to the bottom surface TDO signal via TDO MX. This allows concatenating or daisy-chaining the IR and DR of a TCP of a lower die with an IR and DR of a TCP of a die stacked on top of the lower die.
    Type: Application
    Filed: January 6, 2015
    Publication date: April 30, 2015
    Inventor: Lee D. Whetsel
  • Publication number: 20150115989
    Abstract: A semiconductor evaluation apparatus includes a jig for evaluation and a probe substrate. The jig for evaluation is provided such that a plurality of semiconductor devices can be placed thereon. The probe substrate is provided so as to face the jig for evaluation, and includes a contact probe. The jig for evaluation includes a plurality of housing portions divided by a frame portion such that the plurality of semiconductor devices can be separately placed on the plurality of housing portions, respectively. The semiconductor evaluation apparatus is configured such that the contact probe can be brought into contact with a plurality of elements in the state where a space is provided by bringing the frame portion and the probe substrate in proximity to each other. In this space, each of the plurality of semiconductor devices is placed between a corresponding one of the plurality of housing portions and the probe substrate.
    Type: Application
    Filed: June 17, 2014
    Publication date: April 30, 2015
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Akira OKADA, Takaya NOGUCHI, Norihiro TAKESAKO, Kinya YAMASHITA, Hajime AKIYAMA
  • Publication number: 20150109013
    Abstract: A semiconductor device includes a unit region including a circuit test region and a probe test region. The circuit test region includes a test circuit and a plurality of circuit test pads operatively coupled to the test circuit. The probe test region includes first and second probe test pads insulated from the circuit test pads, and a first resistance pattern operatively coupled to the first and second probe test pads.
    Type: Application
    Filed: December 30, 2014
    Publication date: April 23, 2015
    Inventors: JINMAN CHANG, Kyounghyun Kim
  • Publication number: 20150102831
    Abstract: A probing assembly includes a TDR probe coupling a time-domain reflectometry (TDR) device with a semiconductor device including a transistor therein, the transistor having a gate electrode, a source electrode, and a drain electrode on a substrate, wherein the TDR probe includes a first probe tip connecting the gate electrode to a signal line of the TDR device, and second to fourth probe tips connecting the source electrode, the drain electrode, and a bulk region of the substrate to ground lines of the TDR device, respectively.
    Type: Application
    Filed: October 3, 2014
    Publication date: April 16, 2015
    Applicant: GWANJU INSTITUTE OF SCIENCE
    Inventors: Byoung-Hun LEE, Yong-Hun KIM, Young-Gon LEE
  • Publication number: 20150087089
    Abstract: A method comprises connecting a testing setup having a plurality of probes to a device under test having a plurality of vias, wherein a probe is aligned with a corresponding via of the device under test and conducting a plurality of via electrical characteristic tests through a conductive path comprising the vias, the probes and a plurality of conductive devices, each of which connects two adjacent probes, wherein the conductive devices are in the testing setup.
    Type: Application
    Filed: December 5, 2014
    Publication date: March 26, 2015
    Inventors: Mill-Jer Wang, Chih-Chia Chen, Hung-Chih Lin, Ching-Nen Peng, Hao Chen
  • Publication number: 20150084660
    Abstract: A de-embed probe including an input configured to connect to a device under test, a memory, a signal generator connected to the input, the signal generator configured to generate a test signal, and a controller connected to the signal generator and configured to control the signal generator. The de-embed probe may be used in a test and measurement system. The test and measurement system also includes a test and measurement instrument including a processor connected to the controller of the de-embed probe, the processor configured to provide instructions to the controller, and a test and measurement input to receive an output from the de-embed probe.
    Type: Application
    Filed: June 27, 2014
    Publication date: March 26, 2015
    Inventors: Daniel G. Knierim, Barton T. Hickman
  • Publication number: 20150077149
    Abstract: A test terminal block is formed of a series terminal block and a test plug block pluggable onto the series terminal block and fastening clamps for releasably securing them together. Each of two fastening clamps has a clamp housing contains at least two catch elements and the housing of each has at least two corresponding mating catch elements that determine two interlocking positions of fastening parts in the fastening clamps, one position is arranged after the other in the plug-on direction of the fastening parts. An unlocking element is movably arranged in the housing of each of the two fastening parts, which unlocking element can be brought into a first unlocking position and a second unlocking position, the locking of the first interlocking position being released in the first unlocking position and the locking of the second interlocking position being released in the second unlocking position by the unlocking element.
    Type: Application
    Filed: September 4, 2013
    Publication date: March 19, 2015
    Applicant: Phoenix Contact GmbH & Co. KG
    Inventor: Christian Kloppenburg
  • Patent number: 8981803
    Abstract: A method for cleaning a contact pad of a microstructure or device to be tested when it is in electric contact with a measure apparatus, being obtained by electrically contacting a flexible probe with said contact pad. The method includes mechanically engaging a free end of the flexible probe in a manner that sticks the free end in the pad; and laterally flexing, by a tip charge, the flexible probe in a manner that keeps the free end stuck in the pad, so as to locally dig into a covering layer of the pad and realize a localized crushing thereof.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: March 17, 2015
    Assignee: Technoprobe S.p.A.
    Inventor: Riccardo Vettori
  • Publication number: 20150070037
    Abstract: Systems and methods to fixture and utilizing a probe which tests a capacitive array are described herein. A support bracket with freedom about a plurality of axes may aid in locating a probe and allowing the probe to contact multiple surfaces consistently. By utilizing the support bracket, the angle between a test probe and a contact surface may be minimized such that the surface of the test probe and the contact surface may rest flat against one another. The system may also limit the force translated through support bracket. This system and method may allow for a high degree of accuracy and a high degree of precision during contact of the test probe and the test surface.
    Type: Application
    Filed: August 4, 2014
    Publication date: March 12, 2015
    Inventors: Anuranjini Pragada, Terrence L. Van Ausdall, Steven P. Hotelling
  • Patent number: 8975906
    Abstract: A probe for inspecting electronic components, and more particularly, to a probe for inspecting electronic components, which connects a target electronic component to an inspection apparatus to inspect defects of the target electronic component. The probe for inspecting electronic components includes: a cylinder body having a cylindrical shape; a piston body reciprocating between an inside and an outside of the cylinder body; a spring surrounding an outer circumference of the cylinder body and the piston body, and forcing a part of the piston body to resiliently move out of the cylinder body when inserted into the cylinder body; a probing unit extending from the cylinder body to be brought into contact with a target electronic component to be inspected as to flow of electric current therethrough; and a contact unit extending from the piston body to be connected to an inspection apparatus for inspecting the target electronic component.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: March 10, 2015
    Assignee: NTS Co., Ltd.
    Inventor: Woo-Yoel Jeong
  • Patent number: 8970238
    Abstract: A probe module for testing an electronic device comprises at least two contacts, each contact including a first end portion extending in a first direction along a first line, a second end portion extending linearly in a second direction opposite from the first direction and along a second line, and a third curved portion extending between the first end portion and the second end portion. The first line is spaced apart from and in parallel with the second line, and the at least two contacts are spaced apart from each other in a direction perpendicular to the first line and the second line. Methods for making such a probe module are also taught.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: March 3, 2015
    Assignee: Electro Scientific Industries, Inc.
    Inventor: Douglas J. Garcia
  • Patent number: 8970240
    Abstract: Resilient electrical interposers that may be utilized to form a plurality of electrical connections between a first device and a second device, as well as systems that may utilize the resilient electrical interposers and methods of use and/or fabrication thereof. The resilient electrical interposers may include a resilient dielectric body with a plurality of electrical conduits contained therein. The plurality of electrical conduits may be configured to provide a plurality of electrical connections between a first surface of the electrical interposer and/or the resilient dielectric body and a second, opposed, surface of the electrical interposer and/or the resilient dielectric body. The systems and methods disclosed herein may provide for improved vertical compliance, improved contact force control, and/or improved dimensional stability of the resilient electrical interposers.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: March 3, 2015
    Assignee: Cascade Microtech, Inc.
    Inventors: Kenneth R. Smith, Mike Jolley, Eric Strid, Peter Hanaway, K. Reed Gleason, Koby L. Duckworth
  • Patent number: 8957690
    Abstract: The present invention relates to a micro contact probe used for a probe card. An exemplary embodiment of the present invention provides a micro contact probe including a coating layer of a nanostructure such as carbon nanotubes formed on a surface thereof to reduce contact resistance when contacting a semiconductor chip. According to the micro contact probe of which the surface is coated with the nanostructure, contact resistance between the probe and the semiconductor chip is lowered and the high frequency characteristics are improved, such that a more accurate measurement can be obtained.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: February 17, 2015
    Assignee: Korea Institute of Machinery & Materials
    Inventors: Jung-Yup Kim, Hak-Joo Lee, Chang-Soo Han
  • Patent number: 8952713
    Abstract: A device tester is provided. The device tester includes a probe card and a substrate coupled to the probe card. The substrate has a plurality of layers for routing a signal. An integrated circuit is coupled to the substrate. The integrated circuit is operable to transmit an input signal received from a testing apparatus to a device under test through the substrate to a signal probe. The signal probe is further operable to receive a test signal from the device under test in response to the input signal, wherein the integrated circuit is operable to amplify the test signal, and transmit the amplified test signal to the testing apparatus.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: February 10, 2015
    Assignee: Altera Corporation
    Inventors: Jayabrata Ghosh Dastidar, Aman Aflaki Beni, Zunhang Yu Kasnavi
  • Patent number: 8947108
    Abstract: A method for determining and retrieving positional information includes forming a grid by locating a plurality of first conductive elements on a surface and a plurality of second conductive elements on the surface. A second grid is coupled to the surface and electrically isolated from the grid. The surface is penetrated with a projectile and a first location of a first penetration of the surface is electronically determined based on a first change in a first electrical measurement. A plurality of third and fourth electrical measurements are performed in a second plurality of locations of the second grid and the location impact is electronically determined.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: February 3, 2015
    Inventor: Bruce Hodge
  • Patent number: 8941108
    Abstract: A method performs electrical testing and assembly of an electronic device on a wafer and comprising a pad made in an oxide layer covered by a passivation layer. The method includes connecting the electronic device to a testing apparatus; providing said electronic device with a metallization layer extending on the passivation layer from the pad to a non-active area of said wafer. The method comprises-performing the electrical testing on wafer of the electronic device by placing a probe of on a portion of the extended metallization layer; performing the cut of said wafer, reducing the extension of the metallization layer to the edge of the electronic device; embedding the device inside a package, forming on the metallization layer an electrical connection configured to connect the metallization layer to a circuit in said package.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: January 27, 2015
    Assignee: STMicroelectronics S.r.l.
    Inventor: Alberto Pagani
  • Publication number: 20150022227
    Abstract: An integrated high-speed probe system is provided. The integrated high-speed probe system includes a circuit substrate for transmitting low-frequency testing signals from a tester through a first probe of the probe assembly to a DUT, and a high-speed substrate for transmitting high-frequency testing signals from the tester to the DUT. The high-speed substrate extends from the upper surface of the circuit substrate in the testing area to the lower surface of the circuit substrate in the probe area for being adjacent to the probe assembly and electrically connecting the second probe. In this way, the tester can transmit testing signals of different frequencies through the integrated high-speed probe system.
    Type: Application
    Filed: October 3, 2014
    Publication date: January 22, 2015
    Inventors: Chun-Chi WANG, Chia-Tai CHANG, Ya-Yun CHENG, Wei-Cheng KU, Chao-Ping HSIEH
  • Publication number: 20150015288
    Abstract: A test probe is provided for probing signal information on a back-drilled plated through hole connector formed in a printed circuit board, where the test probe includes a conductive probe body with a distal tip region extending a predetermined minimum coverage length (LTIP) that is longer than a recess depth dimension (DPL) for a recessed plating layer formed in the back-drilled plated through hole connector with an elastomer test probe tip formed around the distal tip region and having a total tip width (WTIP) which is compressed when inserted into the recessed plating layer formed in a back-drilled plated through hole connector, thereby establishing a conductive path between the conductive probe body and the recessed plating layer.
    Type: Application
    Filed: July 10, 2013
    Publication date: January 15, 2015
    Inventor: Wai M. Ma