Abstract: A multiple conduction path probe can provide an electrically conductive signal path from a first contact end to a second contact end. The probe can also include an electrically conductive secondary path and an electrically insulated gap between the signal path and the secondary path. The gap can be relatively small and thus provide the probe with a low loop inductance. A probe assembly can comprise multiple such probes disposed in passages in substantially parallel electrically conductive guide plates. The signal path of each of the probes can be electrically insulated from both guide plates, but the secondary path of each probe can be electrically connected to one or both of the guide plates. In some configurations, the probe assembly can include one or more secondary probes disposed in passages of the conductive guide plates and electrically connected to one or both of the guide plates.

Abstract: A probe module, which supports loopback test and is provided between a PCB and a DUT, includes a substrate, a probe base, two probes, two signal path switchers, and a capacitor. The substrate has two first connecting circuits and two second connecting circuits, wherein an end of each first connecting circuit is connected to the PCB. The probe base is provided between the substrate and the DUT with the probes provided thereon, wherein an end of each probe is exposed and electrically connected to one second connecting circuit, while another end thereof is also exposed to contact the DUT. Each signal path switcher is provided on the probe base, and respectively electrically connected to another end of one first and one second connecting circuits. The capacitor is provided on the probe base with two ends electrically connected to the two signal path switchers.

Abstract: A method of testing a semiconductor die having an array of contacts, where at least two I/O pads in adjacent positions have the same data signal during testing operations with a test probe. The adjacent I/O pads form a test cluster allowing the use of a larger test probe tip and/or greater tolerance on test probe tip alignment during testing operations.

Abstract: A three dimensional (3D) integrated circuit (IC) testing apparatus includes a plurality of connection devices. When a device under test (DUT) such as an interposer or a 3D IC formed by a plurality of 3D dies operates in a testing mode, the 3D IC testing apparatus is coupled to the DUT via a variety of interface channels such as probes. The connection devices and a variety of through silicon vias (TSVs) in the DUT form a TSV chain so that an electrical characteristic test of the variety of TSVs can be tested all at once.

Abstract: A multifunction test instrument probe includes a housing having a hollow bore with an open end. A clamp plunger is carried in the hollow bore, with a first end including a thumb press, and a second end including an alligator clamp having a pair of jaws, with a compression spring normally biasing the thumb press away from the housing, and normally biasing the alligator clamp substantially within the hollow bore proximate the open end. A point plunger is also carried in the bore, with a first end including a thumb press, and a second end terminating in a point, with a second compression spring normally biasing the thumb press away from the housing, and biasing the point within the hollow bore proximate the open end.

Abstract: A method is disclosed for the measurement of a power device in a prober, which serves the examination and testing of such components. In the process, a power device is held by a chuck, and at least one electric probe is held by a probe holder, and optionally, the power device or the probe is positioned each relative to the other using a positioning device with an electrical drive, and contacts the power device. At the same time, an electrical connection remains between the probe to a signal unit with which a power signal is sent out or received, is blocked and only unblocked when it is determined that the contact between probe 26 and contact area is established.

Abstract: Embodiments of the present invention are directed to adjustable test probe tips that are indexable. In one embodiment a mechanism is coupled to a probe tip so that the mechanism may be used to index the probe tip to a plurality of particular positions. A label portion may be provided to communicate to a user that the length of the exposed probe tip is less than a particular length, such as the maximum length an exposed probe tip may be for a particular application.

Abstract: A test control device and a method automatically test signal integrities of an electronic product. The test control device includes an oscilloscope and robot devices each holding a probe of the oscilloscope. The test control device sets test projects and locations of test points of each test project on the electronic product. The test control device selects a test project and selects probes for measuring electrical outputs at the test points of the selected test project, controls robot devices holding the selected probes to move tips of the selected probes to touch the test points, and controls the electronic product to activate the test points. The oscilloscope measures the electrical outputs at the test points through the selected probes. The test control device further obtains results of the measurements from the oscilloscope, analyzes and integrates all of the measurements, and generates a signal integrity report of the electronic product.

Abstract: A test fixture (120) is disclosed for electrically testing a device under test (130) by forming a plurality of temporary mechanical and electrical connections between terminals (131) on the device under test (130) and contact pads (161) on the load board (160). The test fixture (120) has a replaceable membrane (150) that includes vias (151), with each via (151) being associated with a terminal (131) on the device under test (130) and a contact pad (161) on the load board (160). In some cases, each via (151) has an electrically conducting wall for conducting current between the terminal (131) and the contact pad (161). In some cases, each via (151) includes a spring (152) that provides a mechanical resisting force to the terminal (131) when the device under test (130) is engaged with the test fixture (120).

Abstract: A method of testing a semiconductor device having a substrate in and on which a cell structure and a termination structure are formed, the cell structure having a main current flowing therethrough, the termination structure surrounding the cell structure, the method includes a first test step of testing dielectric strength of the semiconductor device, a charge removal step of, after the first test step, removing charge from a top surface layer of the termination structure, the top surface layer being located on the substrate and formed of an insulating film or a semi-insulating film, and a second test step of, after the charge removal step, testing dielectric strength of the semiconductor device.

Abstract: There is provided a test apparatus for testing a device under test, including a test signal generator that generates a test signal to test the device under test, an electric-photo converter that converts the test signal into an optical test signal, an optical interface that (i) transmits the optical test signal generated by the electric-photo converter to an optical receiver of the device under test and (ii) receives and outputs an optical response signal output from the device under test, a photo-electric converter that converts the optical response signal output from the optical interface into an electrical response signal and transmits the electrical response signal, and a signal receiver that receives the response signal transmitted from the photo-electric converter and a test method.

Abstract: A method of obtaining an electrical property of a test sample, comprising a non-conductive area and a conductive or semi-conductive test area, by performing multiple measurements using a multi-point probe. The method comprising the steps of providing a magnetic field having field lines passing perpendicularly through the test area, bringing the probe into a first position on the test area, the conductive tips of the probe being in contact with the test area, determining a position for each tip relative to the boundary between the non-conductive area and the test area, determining distances between each tip, selecting one tip to be a current source positioned between conductive tips being used for determining a voltage in the test sample, performing a first measurement, moving the probe and performing a second measurement, calculating on the basis of the first and second measurement the electrical property of the test area.

Abstract: A circuit board inspection apparatus configured to perform electrical inspection of wiring patterns formed on a circuit board with a built-in electronic component is provided with a plurality of contactors, a switching circuit, and a controller. The controlling device applies voltage by using a power supply between a contactor and a contactor in a state a switch of the switching circuit is set to be ON and inspects an insulating state between two wiring patterns corresponding to two inspection points on the circuit board. At this time, if forward bias is applied to and forward current flows in diodes inserted between the contactors outside the circuit board, a potential difference between the contactors becomes equal to a potential difference between the diodes and is limited to a relatively small value.

Abstract: A method for temporary electrical contacting of a component arrangement with a plurality of contact surfaces is described. A connection support includes a plurality of connection surfaces, on which contact protrusions are disposed. The connection support and component arrangement are brought together in such a way that the connection surfaces and the associated contact surfaces overlap in a top view and the contact protrusions form an electrical contact with respect to the contact surfaces in order to achieve electrical contacting of the component arrangement. Subsequently the connection support and the component arrangement are separated from each other.

Abstract: There is provided a circuit board inspection tool configured to electrically connect a circuit board with a built-in electronic component and a circuit board inspection apparatus configured to inspect a plurality of wiring patterns formed on the circuit board. The circuit board inspection tool includes a plurality of contactors, an electrode body on which the respective contactors abut at the other end and which are electrically connected to the circuit board inspection apparatus, and a holding body having an inspection-side holding unit configured to guide one ends of the contactors to the inspection points and an electrode-side holding unit configured to guide the other ends thereof to the electrode units, wherein an amount of projection of a contactor which abuts on an inspection point of a wiring pattern conductively connected to the electronic component is formed to be greater than that of the other contactors.

Abstract: A circuit for testing a floating body field-effect transistor (FET), and a related method, are provided. Embodiments of this invention include a circuit including a contacted-body FET structure that can be operated in a floating body mode or a body-contacted mode, and a passgate FET. A body of the contacted-body FET structure is connected to the drain of the passgate FET. Voltage can be applied to the passgate FET to either allow or restrict current flow through the passgate FET, to operate the contacted-body FET structure in body contacted mode or floating body mode. Data can be taken in each mode and compared to extract a floating body voltage.

Abstract: A semiconductor wafer includes semiconductor chips divided by a dicing line, one of the semiconductor chips including terminals of an identical potential; a wiring located on the dicing line, and electrically connecting the terminals to each other; and a pad electrically connected through the wiring to the terminals, wherein the pad is located entirely on the semiconductor chip and is not present on the dicing line.

Abstract: Crack sensors for semiconductor devices, semiconductor devices, methods of manufacturing semiconductor devices, and methods of testing semiconductor devices are disclosed. In one embodiment, a crack sensor includes a conductive structure disposed proximate a perimeter of an integrated circuit. The conductive structure is formed in at least one conductive material layer of the integrated circuit. The conductive structure includes a first end and a second end. A first terminal is coupled to the first end of the conductive structure, and a second terminal is coupled to the second end of the conductive structure.

Abstract: A probe includes a first deforming portion which includes a linkage mechanism formed by a vertical probe and a plurality of horizontal beams extending in a direction perpendicular to vertical direction, one ends of the horizontal beams being connected to a fixed end and the other ends being connected to the vertical probe, wherein: a vertical portion of the vertical probe extending from the horizontal beams forms a second deforming portion including a horizontal beam portion extending toward the fixed end from an intermediate part of the vertical portion; and scrubbing of the vertical probe in whole operation of an overdrive is strictly controlled by causing bending moment to act on the horizontal beam portion of the second deforming portion, simultaneously with the overdrive applying in a direction in which bending moment applied to the vertical probe of the first deforming portion is offset.

Abstract: An embodiment of a test apparatus for executing a test of a set of electronic devices having a plurality of electrically conductive terminals, the test apparatus including a plurality of electrically conductive test probes for exchanging electrical signals with the terminals, and coupling means for mechanically coupling the test probes with the electronic devices. In an embodiment, the coupling means includes insulating means for keeping each one of at least part of the test probes electrically insulated from at least one corresponding terminal during the execution of the test. Each test probe and the corresponding terminal form a capacitor for electro-magnetically coupling the test probe with the terminal.

Abstract: In one embodiment, a method for testing a plurality of singulated semiconductor die involves 1) placing each of the singulated semiconductor die on a surface of a die carrier, 2) mating an array of electrical contactors with the plurality of singulated semiconductor die, and then 3) performing electrical tests on the plurality of singulated semiconductor die, via the array of electrical contactors.

Abstract: The present disclosure provide a probe card for wafer level testing. The probe card includes a space transformer having a power line, a ground line, and signal lines embedded therein, wherein the space transformer includes various conductive lines having a first pitch on a first surface and a second pitch on a second surface, the second pitch being substantially less than the first pitch; a printed circuit board configured approximate the first surface of the space transformer; and a power plane disposed on the first surface of the space transformer and patterned to couple the power line and the ground line of the space transformer to the printed circuit board.

Abstract: A wafer testing system and associated methods of use an manufacture are disclosed herein. In one embodiment, the wafer testing system includes an assembly for releaseably attaching a wafer to a wafer translator and the wafer translator to an interposer by means of separately operable vacuums, or pressure differentials. The assembly includes a wafer translator support ring coupled to the wafer translator, wherein a first flexible material extends from the wafer translator support ring so as to enclose the space between the wafer translator and the interposer so that the space may be evacuated by a first vacuum through one or more first evacuation paths. The assembly can further include a wafer support ring coupled to the wafer and the chuck, wherein a second flexible material extends from wafer support ring so as to enclose the space between the wafer and the wafer translator so that the space may be evacuated by a second vacuum through one or more second evacuation pathways.

Abstract: A contact structure for inspection that is installed on a bottom surface of a circuit board includes a ground conductor that is grounded; an elastic contact member that is brought into contact with an inspection target object; and a conductive line that electrically connects the circuit board and the elastic contact member. Here, the elastic contact member may be provided on a bottom surface of the ground conductor that is grounded. The elastic contact member may include an insulating layer, a wiring layer, a contactor and an elastic body provided at a position corresponding to the contactor. The elastic body provides the elastic contact member with elasticity when the contactor is brought into contact with an electrode. The elastic contact member is provided in parallel with the ground conductor. The wiring layer and the ground conductor form a microstrip line.

Abstract: A probe apparatus may include a plurality of probe pins attached to a probe head portion. Each of the probe pins may be independently movable relative to the probe head portion.

Abstract: A method for determining scattering parameters using a calibration substrate having at least one calibration standard with at least two electrical connection points, each for one measurement gate of a vector network analyzer. At least one electrical connection point is formed of at least one calibration standard having a switch, wherein the switch has a first electrical contact electrically connected to an electrical connection point of the calibration standard, a second electrical contact designed for electrically connecting to a measurement gate of the vector network analyzer, and a third electrical contact, wherein the switch is designed such that an electrical contact is established either between the first and third electrical contact or between the first and second electrical contact.

Abstract: The present invention relates generally to testing of interconnects in a semiconductor die, and more particularly to testing of semiconductor chips that are three-dimensionally stacked via an interposer. In one aspect, a method for testing an interconnect in a semiconductor die comprises providing the semiconductor die, which includes a plurality of electrical contact elements formed at one or more surfaces of the semiconductor die, at least one interconnect-under-test disposed between a first electrical contact element and a second electrical contact element, and an electrical component electrically coupled between the interconnect-under-test and at least one third electrical contact element.

Abstract: One plate-like member and the other plate-like member to be aligned with each other are provided with guide holes and guide portions to be received in the guide holes, respectively. The plate-like members are aligned appropriately, and in a state in which this alignment is held, the guide portions are formed on land portions provided on the other plate-like member so as to be aligned with the guide holes. Accordingly, regardless of presence/absence or size of a process error in the guide holes, the guide portions appropriate to the respective guide holes can be formed. Consequently, by aligning the guide portions with the guide holes, the plate-like members can be aligned appropriately without relative fine adjustment between the members.

Abstract: A switch probe for use in a substrate inspection device to inspect a substrate includes a first tubular element, a first rod element partially accommodated in the first tubular element, and pressed into the first tubular element when the certain part is mounted for substrate inspection, a second tubular element fixed in the first tubular element, a second rod element partially accommodated in the second tubular element which is inside the first tubular element, and contacting with the first rod element when the first rod element is pressed into the first tubular element, and a fixing mechanism configured to temporarily fix the second rod element in a position so that the second rod element does not contact with the first rod element even when the first rod element is pressed into the first tubular element.

Abstract: A test apparatus that test a device under test, comprising a test head that is arranged facing the device under test and that includes a test module for testing the device under test, and a probe assembly that transmits a signal and that is arranged between the test head and the device under test. The probe assembly includes a plurality of low voltage pins arranged at prescribed intervals from each other, and a plurality of high voltage pins that are arranged such that distance between each high voltage pin and each low voltage pin is greater than the prescribed interval, and that transmit a signal with a higher voltage than a signal transmitted by the low voltage pins. All of the high voltage pins are arranged in only one of two regions formed by dividing a surface of the probe assembly in half.

Abstract: Various embodiments of a semiconductor apparatus and related methods are disclosed. In one exemplary embodiment, a semiconductor apparatus may include a chip, scribe lanes disposed around the chip, and a probe test logic circuit for conducting a probe test on the chip. The probe test logic circuit is disposed on a portion of the scribe lanes.

Abstract: An apparatus for interrogating an electronic circuit supported by a substrate includes a tester external to the substrate and comprising an tester transceiver. A testing circuit is supported by the substrate and connected to the electronic circuit. The testing circuit includes a processor and a testing circuit transceiver in communication with the tester transceiver for transmitting instructions from the tester to the processor and for transmitting results of an interrogation from the processor to the tester. The processor being programmed to process instructions from the tester to interrogate the electronic circuit with an interrogation corresponding to the instructions.

Abstract: Systems and methods for simultaneous optical testing of a plurality of devices under test. These systems and methods may include the use of an optical probe assembly that includes a power supply structure that is configured to provide an electric current to a plurality of devices under test (DUTs) and an optical collection structure that is configured to simultaneously collect electromagnetic radiation that may be produced by the plurality of DUTs and to provide the collected electromagnetic radiation to one or more optical detection devices. The systems and methods also may include the use of the optical probe assembly in an optical probe system to evaluate one or more performance parameters of each of the plurality of DUTs.

Abstract: A printed circuit board has first terminals for contacting terminals of a socket, second terminals for contacting terminals of a test fixture of an automatic test equipment, which are adapted for contacting the terminals of the socket of a device under test, transmission lines for connecting the first terminals and the terminals, and an extracting circuit electrically coupled to one of the transmission lines and configured to extract the signal being exchanged between the device under test and the automatic test equipment. The extracting circuit has a resistor or an electrical resistor network, wherein a loss added on the signal being exchanged between the device under test and the automatic test equipment over the one transmission line due to the presence of the printed circuit board is smaller than 6 dB.

Abstract: Electronic test system and associated method, including a first and a second connection terminals respectively coupled to two pins of a chip under test, a signal source terminal coupled to a signal generator, a first and a second measurement terminals coupled to a tester, a fifth switch, a seventh switch and a switch circuit which has a first and a fourth front terminals coupled to the signal source terminal, has a first and a fourth back terminals coupled to the first and second connection terminals, and controls conduction between the first front terminal and the first back terminal, as well as conduction between the fourth front terminal and the fourth back terminal. The fifth switch is coupled between the fourth back terminal and the first measurement terminal, and the seventh switch is coupled between the first connection terminal and the second measurement terminal.

Abstract: An object of the invention is to provide an inspection device which has a function of preventing electric discharge so that an absorbed current is detected more efficiently. In the invention, absorbed current detectors are mounted in a vacuum specimen chamber and capacitance of a signal wire from each probe to corresponding one of the absorbed current detectors is reduced to the order of pF so that even an absorbed current signal with a high frequency of tens of kHz or higher can be detected. Moreover, signal selectors are operated by a signal selection controller so that signal lines of a semiconductor parameters analyzer are electrically connected to the probes brought into contact with a sample. Accordingly, electrical characteristics of the sample can be measured without limitation of signal paths connected to the probes to transmission of an absorbed current. In addition, a resistance for slow leakage of electric charge is provided in each probe stage or a sample stage.

Abstract: A high bandwidth signal probe device and a method of probing a high bandwidth signal are provided. The high bandwidth signal probe device includes a probe tip for probing a stub of a backdrilled via of a printed circuit board. The probe tip is adapted to fit in the backdrilled via. The probe tip has a length adapted to reach the stub of the backdrilled via. The probe tip is adapted to contact a plated portion of the stub of the backdrilled via. A resistive element is associated with the probe tip. The method includes inserting a probe tip of a signal probe device in the backdrilled via, placing the probe tip in contact with a plated portion of the stub of the backdrilled via, and receiving an electrical signal through a path which includes a resistive element of the probe tip of the signal probe device.

Abstract: A contactless measuring system having at least one test probe forming part of a coupling structure for the contactless decoupling of a signal running on a signal waveguide, wherein the signal waveguide is designed as a conductor of the electric circuit on a circuit board and as part of an electric circuit. To this end, at least one contact structure is configured and disposed on the circuit board such that said contact structure is galvanically separated from the signal waveguide, forms part of the coupling structure, is displaced completely within the near field of the signal waveguide, and has at least one contact point, which may be electrically contacted by a contact of the test probe.

Abstract: Systems and methods are provided for testing partially completed three-dimensional ICs. Example methods may incorporate one or more of the following features: design for testing (DFT); design for partial wafer test; design for partial probing; partial IC probecards; partial IC test equipment; partial IC quality determinations; partial IC test optimization; and partial test optimization. Other aspects may also be included. Systems and methods incorporating these features to test partially completed three-dimensional ICs may result in saved time and effort, and less scraped material, as the partial device is not built any further when a bad partial device is detected. This results in lower costs and higher yield.

Abstract: A probe apparatus has probe wires with a contact pattern on one side. The contact pattern is for contacting a respective contact pattern on another test equipment or component, such as a circuit board. The probe wires have tips that probe a device desired for testing. Signals are transmitted through the probe wires from the probe card, for example, through a circuit board to other diagnostic equipment. The contact of the probe card with the circuit board allows signals to be transferred through the probe wires to the other diagnostic equipment. On another side of the probe card is a connector structure. The connector structure includes a retainer that can allow the probe card to be replaced from a test system, such as allowing it to be connected and disconnected from a holder.

Abstract: A startup boot cycle test system for testing a mobile multi-function device under test (DUT) that has a power manager and a main system processor is described. The system includes an external power source and a tester device. The external power source provides an input current to the power manager, which in turn provides a boot current, drawn from the input current, to the main system processor. The tester device connects to a test point in the DUT using a contact test probe to draw a margin current from the boot current. The resulting diminished boot current is used by the processor to boot. The tester device detects whether the processor successfully boots using the diminished boot current using a data input connector connected between the DUT and tester device. Other embodiments are also described and claimed.

Abstract: An embodiment of a test apparatus for executing a test of a set of electronic devices having a plurality of electrically conductive terminals, the test apparatus including a plurality of electrically conductive test probes for exchanging electrical signals with the terminals, and coupling means for mechanically coupling the test probes with the electronic devices. In an embodiment, the coupling means includes insulating means for keeping each one of at least part of the test probes electrically insulated from at least one corresponding terminal during the execution of the test. Each test probe and the corresponding terminal form a capacitor for electro-magnetically coupling the test probe with the terminal.

Abstract: A system for testing a device under test (DUT), in which electrical coupling among a module board, a low profile connector, and, a DIB is established by applying a pressure on the module board toward the DUT, is provided. The system includes a test head bracket secured inside a test head, the test head bracket includes the module board having a first section including a plurality of connectors to couple a test analyzer to the module board, a second section including a plurality of contacts pads to electrically couple the module board to the DUT, and, a flexible board to enable the first section to be placed at an angle with respect to the second section. The test head bracket also includes a module board stiffener mechanically securing the first section and the second section to the test head and the low profile connector electrically couples the module board to the DUT.

Abstract: Translators coupleable to opposing surfaces of microelectronic substrates for testing, and associated systems and methods are disclosed. An arrangement in accordance with one embodiment includes a microelectronic substrate having a first major surface, a second major face facing opposite from the first major surface, and electrically conductive through-substrate vias extending through the substrate and electrically accessible from both the first and second surfaces.

Abstract: Provided is a current application device capable of applying a test current of a magnitude necessary for testing of a semiconductor element without any trouble. A current application device 1 is configured to have a contacting section having a plurality of projections 21 for contacting a contact region 24 inside an active region 23 of a semiconductor element 22 and applying the test current thereto, and a pressing section 3 which presses the contacting section 2 against the semiconductor element 22 such that each projection 21 contacts the contact region 24. A plurality of the projections 21 are arranged such that an arrangement density of outside projections 21 is larger than the arrangement density of inside projections 21.

Abstract: Approaches for performing in line wafer testing are provided. An approach includes a method that includes generating a radio frequency (RF) test signal, and applying the RF test signal to a device under test (DUT) in a wafer using a buckling beam probe set with a predefined pitch. The method also includes detecting an output RF signal from the DUT in response to the applying the RF test signal to the DUT, and sensing at least one frequency component of the detected output RF signal.

Abstract: Circuits and methods for testing wafers are disclosed herein. An embodiment of a method includes electrically contacting a first probe and a second probe to a wafer. A gas is blown in the areas proximate the first probe and the second probe. An electric potential is then applied between the first probe and the second probe while the gas is being blown.

Abstract: Systems and methods for rotational alignment of a device under test are disclosed herein. These systems include a chuck that includes a rotational positioning assembly that includes a lower section and an upper section that is configured to selectively rotate relative to the lower section about a rotational axis. The rotational positioning assembly further includes a first bearing that is configured to support a radial load between the upper section and the lower section and a second bearing that is configured to support a thrust load between the upper section and the lower section. The methods include providing a fluid stream to the second bearing to permit rotation of the upper section relative to the lower section, rotating the upper section relative to the lower section, and ceasing the providing the fluid stream to the second bearing to restrict rotation of the upper section relative to the lower section.

Abstract: A contactor includes a contactor base material including a first material and a conductor film including a second material. The conductor film is formed only on a contact surface with an electrode of a semiconductor apparatus at a tip of the contactor film.

Abstract: A probe includes a contact member brought into contact with an object to be tested. Contact particles having conductivity are uniformly distributed in the contact member. A part of the contact particles protrude from a surface of the contact member on the side of the object to be tested. A conductive member having elasticity is placed on a surface of the contact member on the opposite side to the object to be tested. The probe further includes an insulating sheet including a through hole and the contact member is so positioned as to penetrate the through hole. An upper part of the contact member is formed of a conductor which does not include the contact particles. An additional conductor is placed on a surface of the conductor on the side opposite to the object to be tested.