In Or On Support For Device Under Test Patents (Class 324/754.08)
  • Patent number: 10663382
    Abstract: A testing apparatus for applying a test load to a specimen, comprises a cradle and a test bed supported on the cradle. The test bed has a chamber which receives a specimen and is hermetically sealed with the specimen received inside. There is a vacuum source in communication with the chamber. The vacuum source provides vacuum pressure to the chamber, thereby applying a uniform load to the specimen.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: May 26, 2020
    Assignee: Canada Scaffold Supply Co. Ltd.
    Inventors: Keith Iwasaki, Chris Musil
  • Patent number: 10663484
    Abstract: Device and system for characterizing samples using multiple integrated tips scanning probe microscopy. Multiple Integrated Tips (MiT) probes are comprised of two or more monolithically integrated and movable AFM tips positioned to within nanometer of each other, enabling unprecedented micro to nanoscale probing functionality in vacuum or ambient conditions. The tip structure is combined with capacitive comb structures offering laserless high-resolution electric-in electric-out actuation and sensing capability. This “platform-on-a-chip” approach is a paradigm shift relative to current technology based on single tips functionalized using stacks of supporting gear: lasers, nano-positioners and electronics.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: May 26, 2020
    Assignee: Xallent, LLC
    Inventor: Kwame Amponsah
  • Patent number: 10571487
    Abstract: Contact engines, probe head assemblies, probe systems, and associated methods for on-wafer testing of the wireless operation of a device under test (DUT). A contact engine includes a flexible dielectric membrane having a first surface and a second surface and a plurality of probes supported by the flexible dielectric membrane. The plurality of probes are oriented to contact a plurality of contact locations on the DUT. Each probe in the plurality of probes includes a corresponding probe tip that projects from the second surface of the flexible dielectric membrane and is configured to electrically and physically contact a corresponding contact location of the plurality of contact locations. The contact engine further includes at least one membrane antenna supported by the flexible dielectric membrane. A probe head assembly includes the contact engine. A probe system includes the probe head assembly. Associated methods include methods of utilizing the contact engine.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: February 25, 2020
    Assignee: FormFactor Beaverton, Inc.
    Inventors: Daniel Mark Bock, Tim Cleary
  • Patent number: 10564202
    Abstract: A test set-up for testing a system-in package with an integrated antenna is described herein. According to one exemplary embodiment, the test set-up includes a carrier with an RF probe arranged thereon and a test socket with resilient electric contacts. The test socket is mounted on the carrier and provides an electric contact to interconnects of the package when it is placed on the test socket. The test socket has an opening which is arranged superjacent to the RF probe.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: February 18, 2020
    Assignee: Infineon Technologies AG
    Inventors: Jochen O. Schrattenecker, Oliver Frank, Alexander Kaineder
  • Patent number: 10184978
    Abstract: A probe card for a wafer tester includes a mother card having a reinforcing element and at least one daughter card which is rigidly connected to the reinforcing element detachably. The mother card includes electrical contacts for producing an electrical connection with the wafer tester. The at least one daughter card includes electrical contact elements for making contact with an electrical circuit on a wafer. In addition, the mother card and the at least one daughter card are electrically detachably connected to one another via an electrical interface.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: January 22, 2019
    Assignee: Infineon Technologies AG
    Inventors: Karl Dominizi, Oliver Frank, Klaus Standner, Stefan Zielke
  • Patent number: 10161964
    Abstract: An inspection unit includes: a metal block having at least a through hole; a ground bush disposed in the through hole, and being an electrically conductive body including: a cylindrical body part; and a projected part which is projected sideward from an outer face of the body part, and which is in contact with an area around an opening of the through hole in the metal block; and a contact probe for ground passing through an interior of the ground bush.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: December 25, 2018
    Assignee: Yokowo Co., Ltd.
    Inventor: Masataka Miyagawa
  • Patent number: 10114055
    Abstract: Apparatus for testing a device by delivering an electrostatic discharge signal to one or more device terminals, comprising a first part configured for mechanically mounting the device and comprising one or more first part connectors for electrically coupling to the one or more device terminals and thus providing electrical access to the one or more device terminals, a second part comprising one or more second part connectors configured for electrically coupling the one or more first part connectors to the one or more second part connectors for testing the device via the second part connectors, and a guide arranged for mechanically moving the first part relative to the second part. The guide is configured to physically disconnect the one or more first part connectors from the one or more second part connectors while the electrostatic discharge signal is delivered to the one or more device terminals.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: October 30, 2018
    Assignee: NXP USA, Inc.
    Inventors: Alain Salles, Jean Dalmon, Roger Stivanin
  • Patent number: 9952122
    Abstract: An electronic test plate includes a test plate comprising plurality of wells, each well configured to contain a substance to be analyzed. Sensors are arranged to sense characteristics of the substance and to generate sensor signals based on the sensed characteristics over time. The sensors are arranged so that multiple sensors are associated with each well. At least one sensor of the multiple sensors senses a characteristic of the substance that is different from a characteristic sensed by another sensor of the multiple sensors. Sensor select circuitry is arranged on a backplane disposed along the test plate. The sensor select circuitry is coupled to the sensors and enable the sensor signals of selected sensors to be accessed at a data output of the backplane.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: April 24, 2018
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Mandana Veiseh, JengPing Lu, Eugene M. Chow, David K. Biegelsen, Ramkumar Abhishek, Felicia Linn
  • Patent number: 9905954
    Abstract: A power transmission device includes a first circuit board, a conductive base, a connection element, a second circuit board, and a fixing element. The conductive base is fixed on the first circuit board. The connection element is disposed on the conductive base. The second circuit board is fixed on the connection element. The fixing element is disposed on the second circuit board, and connected to the conductive base by penetrating through the second circuit board and the connection element. The first circuit board is electrically connected to the second circuit board via the conductive base and the connection element.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: February 27, 2018
    Assignee: Delta Networks, Inc.
    Inventors: I-Wen Chan, Shu-Hong Chu, Kuo-Shung Huang
  • Patent number: 9857678
    Abstract: A method of controlling distortion of an exposure process is provided. The method includes aligning an exposure mask with a wafer, forming a first test pattern on the wafer by performing a first exposure with the exposure mask and a first illumination system, forming a photoresist layer on an entire surface of the wafer including the first test pattern, performing a second exposure with the exposure mask and a second illumination system to form a second test pattern overlapping with the first test pattern, extracting a distortion value between the first test pattern and the second test pattern, and correcting the exposure mask or fabricating a corrected exposure mask using the distortion value.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: January 2, 2018
    Assignee: SK Hynix Inc.
    Inventors: Chan Ha Park, Shin Young Kim
  • Patent number: 9817032
    Abstract: To provide a measurement device which allows long-term accurate measurement of voltage without adversely affecting a device under test, by ensuring a predetermined level of resistance to ESD and reducing leakage current. A measurement device includes a probe needle for contacting a device under test, a first FET for detecting voltage of the device under test, and a protection circuit for protecting the first FET from static electricity. The protection circuit includes a second FET having an oxide semiconductor film as a channel formation region.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: November 14, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kei Takahashi, Noboru Inoue
  • Patent number: 9817062
    Abstract: A parallel concurrent test (PCT) system is provided for performing the parallel concurrent testing of semiconductor devices. The PCT system includes a pick and place (PnP) handler for engaging and transporting the semiconductor devices along a testing plane, the PnP handler including at least one manipulator. The PCT system also includes a device under test interface board (DIB), the DIB including a broadside test socket for broadside (BS) testing of the semiconductor devices, the broadside testing using at least half of a total number of a semiconductor device pins, and a plurality of design-for-test (DFT) test sockets for DFT testing, the DFT testing using less than half of the total number of the semiconductor device pins, and a tester in electrical contact with the DIB for testing the semiconductor devices in accordance with a stepping pattern test protocol.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: November 14, 2017
    Assignee: CELERINT, LLC.
    Inventor: Howard H. Roberts, Jr.
  • Patent number: 9696402
    Abstract: Provided is a probe card inspection apparatus including: a substrate; a first insulating layer which covers the substrate; and a first detection unit which is formed on the first insulating layer and detects physical defects of a probe of a probe card. The first detection unit includes: a ground detection unit including a first conductive pattern which defines a plurality of openings which expose a portion of the first insulating layer and detect defects of a ground probe of the probe card and; and a signal and power detection unit including a second conductive pattern which defines a plurality of openings which expose another portion of the first insulating layer and detect defects of a signal and power supply probe of the probe card.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: July 4, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shin-ho Kang, Joon-su Ji, Jung-woo Kim
  • Patent number: 9658279
    Abstract: A power semiconductor device includes a semiconductor body. The semiconductor body includes an active semiconductor region and a perimeter semiconductor region surrounding the active semiconductor region. The active semiconductor region has an active surface area, and the perimeter semiconductor region has a perimeter surface area. The power semiconductor device further includes a test structure for contactless testing of the perimeter semiconductor region. The test structure includes an electrically conductive path mounted on the perimeter surface area. The test structure is configured to extract energy from a remotely generated electromagnetic radio frequency test field.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: May 23, 2017
    Assignee: Infineon Technologies AG
    Inventors: Eric Graetz, Hermann Bilban, Rudolf Pairleitner
  • Patent number: 9595773
    Abstract: A probe pin has a coil spring having a first end and a second end, a first plunger having a major portion, and a first elastic extension and a second elastic extension that from the major portion in the same direction, and a second plunger forcedly inserted between the first and the second elastic extensions. The first and the second plungers have electric conductivity. The first and the second plungers are inserted from the first and second ends of the coil spring, respectively, so that the first and the second elastic extensions of the first plunger hold the second plunger with the first elastic extension making a forced contact with a surface of the second plunger to form thereat an electric connection between the first and the second plungers.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: March 14, 2017
    Assignee: OMRON Corporation
    Inventors: Yoshinobu Hemmi, Takahiro Sakai, Hirotada Teranishi
  • Patent number: 9551740
    Abstract: A parallel concurrent test (PCT) system is provided for performing the parallel concurrent testing of semiconductor devices. The PCT system includes a pick and place (PnP) handler for engaging and transporting the semiconductor devices along a testing plane, the PnP handler including at least one manipulator. The PCT system also includes a device under test interface board (DIB), the DIB including a broadside test socket for broadside (BS) testing of the semiconductor devices, the broadside testing using at least half of a total number of a semiconductor device pins, and a plurality of design-for-test (DFT) test sockets for DFT testing, the DFT testing using less than half of the total number of the semiconductor device pins, and a tester in electrical contact with the DIB for testing the semiconductor devices in accordance with a stepping pattern test protocol.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: January 24, 2017
    Assignee: CELERINT, LLC.
    Inventor: Howard H. Roberts, Jr.
  • Patent number: 9128121
    Abstract: A mechanism is described for facilitating a dynamic electro-mechanical interconnect capable of being employed in a test system according to one embodiment. A method of embodiments of the invention may include separating, via a cavity, a first conductor of an interconnect from a second conductor of the interconnect, and isolating, via the cavity serving as a buffer, a first electrical path provided through the first conductor from a second electrical path provided through the second conductor.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: September 8, 2015
    Assignee: Intel Corporation
    Inventors: Evan M. Fledell, Joe F. Walczyk, Dinia P. Kitendaugh
  • Patent number: 9082474
    Abstract: An embodiment providing one or more improvements includes a memory loading system and method for at least managing testing of a memory unit using a memory test system and responsive to at least completion of testing and passing the testing, loading non-testing content into the memory unit for delivery to a customer.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: July 14, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Gerald L. Cadloni
  • Publication number: 20150130488
    Abstract: An inspection apparatus capable of reducing the effect of noises is provided. An inspection apparatus according to the present invention includes a work table 26 on which an object, a fixed body 28 disposed above the work table 26, a probe assembly that holds a probe stylus 38a, a support base member 40 supported on the fixed body 28, a suspension mechanism 46 that supports the probe assembly 38 above the work table 26, and a signal circuit substrate 54 including therein an IC chip 54a that generates an inspection signal supplied to the probe stylus 38a, the signal circuit substrate 54 being supported by the suspension mechanism 46 below the suspension mechanism 46, in which the probe assembly 38 and the support base member 40 are electrically isolated from each other.
    Type: Application
    Filed: October 23, 2014
    Publication date: May 14, 2015
    Inventor: Takayoshi KUDO
  • Patent number: 9013204
    Abstract: A test system is provided. A printed circuit board (PCB) includes a plurality of traces and at least one test point. A central processing unit (CPU) socket including a plurality of first pins and a memory module slot including a plurality of second pins are disposed on the PCB. Each of the second pins is coupled to the corresponding first pin of the CPU socket via the corresponding trace. A CPU interposer board is inserted into the CPU socket, and a memory interposer board is inserted into the memory module slot. The traces form a test loop via the CPU interposer board and the memory interposer board. When an automatic test equipment (ATE) provides a test signal to the test loop via the test point, the ATE determines whether the test loop is normal according to a reflectometry result of the test signal.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: April 21, 2015
    Assignee: Wistron Corp.
    Inventors: Kuan-Lin Liu, Kuo-Jung Peng
  • Patent number: 8970238
    Abstract: A probe module for testing an electronic device comprises at least two contacts, each contact including a first end portion extending in a first direction along a first line, a second end portion extending linearly in a second direction opposite from the first direction and along a second line, and a third curved portion extending between the first end portion and the second end portion. The first line is spaced apart from and in parallel with the second line, and the at least two contacts are spaced apart from each other in a direction perpendicular to the first line and the second line. Methods for making such a probe module are also taught.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: March 3, 2015
    Assignee: Electro Scientific Industries, Inc.
    Inventor: Douglas J. Garcia
  • Publication number: 20150048857
    Abstract: A universal meter socket for portable test equipment has low insertion and extraction forces. The universal meter socket is durable and light in weight, providing a long service life. The universal meter socket contains field-cleanable terminals with replaceable wear components. The universal meter socket also optimizes short current paths for the high current section of the meter, further reducing equipment weight by reducing wire weight and volt-ampere (hereinafter sometimes VA) drive requirements for test equipment. The universal meter socket complies with ANSI C12.7-2005 REQUIREMENTS FOR WATTHOUR METER SOCKETS. The universal meter socket is generally intended for use with electricity meters that comply with ANSI C12 requirements.
    Type: Application
    Filed: March 15, 2013
    Publication date: February 19, 2015
    Applicant: Radian Research, Inc.
    Inventors: Joseph P. Joyce, Robert L. Kindschi
  • Publication number: 20150008948
    Abstract: A prober for testing devices in a repeat structure on a substrate is provided with a probe holder plate, probe holders mounted on the plate, and a test probe associated with each holder. Each test probe is displaceable via a manipulator connected to a probe holder, and a substrate carrier fixedly supports the substrate. Testing of devices, which are situated in a repeat structure on a substrate, in sequence without a substrate movement and avoiding individual manipulation of the test probes in relation to the contact islands on the devices, is achieved in that the probe holders are fastened on a shared probe holder plate and the probe holder plate is moved in relation to the test substrate.
    Type: Application
    Filed: September 19, 2014
    Publication date: January 8, 2015
    Inventors: Frank-Michael Werner, Matthias Zieger, Sebastian Giessmann
  • Patent number: 8884639
    Abstract: In one embodiment, a method for testing a plurality of singulated semiconductor die involves 1) placing each of the singulated semiconductor die on a surface of a die carrier, 2) mating an array of electrical contactors with the plurality of singulated semiconductor die, and then 3) performing electrical tests on the plurality of singulated semiconductor die, via the array of electrical contactors.
    Type: Grant
    Filed: August 27, 2009
    Date of Patent: November 11, 2014
    Assignee: Advantest (Singapore) Pte Ltd
    Inventors: James C. Anderson, Alan D. Hart, Kenneth D. Karklin
  • Patent number: 8841932
    Abstract: A prober for testing devices in a repeat structure on a substrate is provided with a probe holder plate, probe holders mounted on the plate, and a test probe associated with each holder. Each test probe is displaceable via a manipulator connected to a probe holder, and a substrate carrier fixedly supports the substrate. Testing of devices, which are situated in a repeat structure on a substrate, in sequence without a substrate movement and avoiding individual manipulation of the test probes in relation to the contact islands on the devices, is achieved in that the probe holders are fastened on a shared probe holder plate and the probe holder plate is moved in relation to the test substrate.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: September 23, 2014
    Assignee: Cascade Microtech, Inc.
    Inventors: Frank-Michael Werner, Matthias Zieger, Sebastian Giessmann
  • Publication number: 20140253162
    Abstract: A system for testing a device under test (DUT) includes a probe card and a test module. The probe card includes probe beds electrically coupled to a circuit board and a first plurality of electrical contacts coupled to the circuit board, which are for engaging respective ones of a plurality of electrical contacts of a test equipment module. Probes are coupled to respective probe beds and are disposed to engage electrical contacts of the DUT. The probe card includes a second plurality of electrical contacts coupled to the circuit board. The first and second pluralities of contacts are mutually exclusive. The test module includes a memory, a processor, and a plurality of electrical contacts electrically coupled to respective ones of the second plurality of electrical contacts of the probe card. The circuit board includes a first electrical path for electrically coupling the test equipment module to the test module.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 11, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Mill-Jer WANG, Ching-Nen PENG, Hung-Chih LIN, Wei-Hsun LIN, Hao CHEN, Chung-Han HUANG
  • Patent number: 8786301
    Abstract: A system for testing a device under test (DUT), in which electrical coupling among a module board, a low profile connector, and, a DIB is established by applying a pressure on the module board toward the DUT, is provided. The system includes a test head bracket secured inside a test head, the test head bracket includes the module board having a first section including a plurality of connectors to couple a test analyzer to the module board, a second section including a plurality of contacts pads to electrically couple the module board to the DUT, and, a flexible board to enable the first section to be placed at an angle with respect to the second section. The test head bracket also includes a module board stiffener mechanically securing the first section and the second section to the test head and the low profile connector electrically couples the module board to the DUT.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: July 22, 2014
    Assignee: Altera Corporation
    Inventors: Adam J. Wright, Joseph W. Foerstel, Mark Andrew Banke, Ken A. Ito
  • Publication number: 20140159758
    Abstract: A method and apparatus for testing a package-on-package digital device is provided. The method includes the steps of: affixing a top device onto a wing board; affixing a bottom device onto the wing board; connecting the top side solderballs of the bottom package to the bond fingers of the wing board. The wing board is then mounted onto a flat top socket. Once the mounting has been completed, the testing begins, and may use a solid immersion lens or optical diagnostic tool. The configuration of the flat top socket and wing board allows the optical diagnostic tool full access to the bottom device for the testing process and failure analysis.
    Type: Application
    Filed: December 12, 2012
    Publication date: June 12, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Himaja H. Bhatt, Martin E. Parley, Martin L. Villafana
  • Patent number: 8749256
    Abstract: The invention discloses a contacting device for a thin film solar cell, comprising a positioning plane for positioning the solar cell thereon, a contact element for electrically contacting the solar cell and a suction element, wherein the solar cell is arrangeable on the top side of the positioning plane, the contact element is arranged slideably in a direction orthogonal to the positioning plane and arranged slideably through an opening of the positioning plane, and the suction element is arranged on the bottom side of the positioning plane for sucking air through the opening. The contacting device allows for obtaining improved measurement accuracy.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: June 10, 2014
    Assignee: Tel Solar AG
    Inventors: Marco Apolloni, Jean Randhahn
  • Patent number: 8624621
    Abstract: In an embodiment, a chuck to support a solar cell in hot spot testing is provided. This embodiment of the chuck comprises a base portion and a support portion disposed above the base portion. The support portion is configured to support the solar cell above the base portion and to define a cavity between a bottom surface of the solar cell and the base portion that thermally separates a portion of the bottom surface of the solar cell from the base portion.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: January 7, 2014
    Assignee: SunPower Corporation
    Inventors: Jose Francisco Capulong, Emmanuel Abas
  • Patent number: 8558568
    Abstract: A ground terminal has a cylindrical main body. A signal terminal has a terminal main body that is disposed on the inside of the cylindrical main body, and a connecting plate portion that extends from an end portion of the terminal main body. Additionally, a ground terminal has at least three connecting plate portions that are disposed so as to encompass the connecting plate portion of the ground terminal, each extending from mutually different positions on an edge of the cylindrical main body.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: October 15, 2013
    Assignees: Molex Japan Co., Ltd., Advantest Corporation
    Inventors: Ryo Uesaka, Jun Watanabe, Akinori Mizumura, Hirotaka Wagata
  • Patent number: 8531198
    Abstract: A substrate support unit adapted for a system for testing or processing of a substrate is provided. The substrate support unit includes a support table having at least one substrate carrier structure adapted to support a substrate, wherein the substrate carrier structure is electrically floating with respect to ground.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: September 10, 2013
    Assignee: Applied Materials, Inc.
    Inventor: Bernhard Gunter Mueller
  • Patent number: 8519729
    Abstract: In an embodiment, a chuck to support a solar cell in hot spot testing is provided. This embodiment of the chuck comprises a base portion and a support portion disposed above the base portion. The support portion is configured to support the solar cell above the base portion and to define a space between a bottom surface of the solar cell and the base portion that thermally separates a portion of the bottom surface of the solar cell from the base portion.
    Type: Grant
    Filed: February 10, 2010
    Date of Patent: August 27, 2013
    Assignee: SunPower Corporation
    Inventors: Jose Francisco Capulong, Emmanuel Abas
  • Patent number: 8508247
    Abstract: An embodiment of an electrical connecting apparatus comprises a probe base plate and a plurality of contacts provided with tips to be pressed against electrodes of a device under test and arranged on the underside of the probe base plate. The distance dimensions from an imaginary plane parallel to the probe base plate to the tips of the contacts are made the greater toward the center of the probe base plate.
    Type: Grant
    Filed: February 1, 2010
    Date of Patent: August 13, 2013
    Assignee: Kabushiki Kaisha Nihon Micronics
    Inventors: Katsuji Hoshi, Akihisa Akahira, Yoshinori Kikuchi
  • Patent number: 8427184
    Abstract: An SCR module tester facilitates rapid testing of SCR modules by a series of tests that are tailored to detect faults without applying full power to the modules. The SCR tester includes a quick clamp connector that is able to securely and easily clamp SCR modules for both the F/A-18 A/D GCU and F/A-18-E/F GCU facilitating the rapid testing of SCR modules.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: April 23, 2013
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Dexter T Kan
  • Patent number: 8378698
    Abstract: A testing apparatus includes a test controller configured to output a plurality of chip selection signals for selecting chips to be tested from among a plurality of chips, a plurality of first control signals for controlling supply of a power supply voltage to the chips selected by the chip selection signals, and a plurality of second control signals for controlling receiving of test voltages output from the chips supplied with the power supply voltage, and a probe card including one or more test blocks each having a plurality of signal transmitters configured to respectively transfer the power supply voltage to the corresponding chips in response to the different first control signals and respectively apply the test voltages output from the corresponding chips to the test controller in response to the different second control signals.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: February 19, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Young Choi, Chang-Hyun Cho
  • Publication number: 20120326741
    Abstract: Apparatus (10) for transmission testing of a telecommunications jack (100) having a plurality of insulation displacement contacts (IDCs) (103), the apparatus (10) including: a base (30); a plurality of transmission test probes (31) associated with the base (30); and a jack holder (20) for removably coupling the jack (100) to the base (30) such that IDCs (103) of the jack (100) are in electrical communication with corresponding test probes (31); wherein the jack holder (20) is fixed relative to the base (30) during testing, such that the jack (100) remains stationary with respect to the probes (31).
    Type: Application
    Filed: June 15, 2012
    Publication date: December 27, 2012
    Applicant: ADC Communications (Australia) Pty Limited
    Inventors: Kevin James Truskett, Kristian Darrell Stewart
  • Patent number: 8334704
    Abstract: This relates to systems and methods for providing a system-on-a-substrate. In some embodiments, the necessary components for an entire system (e.g., a processor, memory, accelerometers, I/O circuitry, or any other suitable components) can be fabricated on a single microchip in “bare die” form. The die can, for example, be coupled to suitable flash memory through a substrate and flexible printed circuit board (“flex”). In some embodiments, the flex can extend past the substrate, die, or both, to allow additional, relatively large components to be coupled to the flex. In some embodiments, the die can be coupled to the flash memory through the flex and without a substrate. In some embodiments, component test points can be placed on the flash memory side of the substrate.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: December 18, 2012
    Assignee: Apple Inc.
    Inventors: Gloria Lin, Bryson Gardner, Jr., Joseph Fisher, Jr., Dave Goh, Barry Corlett, Dennis Pyper, Amir Salehi
  • Patent number: 8269516
    Abstract: Disclosed is a contactor interconnect in an integrated circuit device test fixture comprises a plurality of contactor pins enabled to provide electrical contact with the contact points of an integrated circuit device, the contactor pins being mounted in the test fixture; and an electrical circuit coupled to two or more of the contactor pins of the test fixture, wherein the electrical circuit is isolated from other contactor pins of the plurality of contactor pins and wherein the electrical circuit is coupled to the two or more contactor pins by an electronically direct pathway.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: September 18, 2012
    Assignee: Xilinx, Inc.
    Inventors: Mohsen H. Mardi, David M. Mahoney
  • Patent number: 8242794
    Abstract: An apparatus for testing electric characteristics of a test object including first connection terminals on a bottom surface and second connection terminals on a top surface, the apparatus comprises a test board comprising first pads on a predetermined surface; a socket configured to electrically connect the test object to the test board; and a handler configured to transport the test object to the socket. The socket comprises a first connection unit configured to be electrically connected to the first connection terminals of the test object and a second connection unit configured to be electrically connected to the second connection terminals of the test object.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: August 14, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Byeong-Hwan Cho
  • Patent number: 8232816
    Abstract: A probe head for testing semiconductor wafers has a probe contactor substrate have a first side and a second side. A plurality of probe contactor tips are coupled to the first side and the plurality of tips lie in a first plane. A plurality of mounting structures are coupled to the second side with each of the mounting structures each having a top surface lying in a second plane, wherein the first plane is substantially parallel to the second plane.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: July 31, 2012
    Assignee: Advantest America, Inc.
    Inventors: Salleh Ismail, Raffi Garabedian, Steven Wang
  • Patent number: 8143909
    Abstract: A universal test socket includes a housing frame including a side wall, an inner protruding portion protruding inwardly from the side wall, and a through window formed at a center portion of the housing frame, wherein the through window is surrounded by the side wall, a pin plate assembly coupled to the housing frame and including a pin plate in which a plurality of test pins are arranged and a plurality of guide pins formed on periphery of the pin plate, and a package guide portion coupled to the housing frame and located above the pin plate assembly, a semiconductor package to be tested being mounted on the package guide portion. When the pin plate assembly is coupled to the housing frame, the positions of the test pins arranged in the housing frame are varied according to a rotation angle of the pin plate assembly with respect to the housing frame.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: March 27, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: In-sun Ryu
  • Patent number: 8138776
    Abstract: A test assembly that may provide access to signals of a circuit that includes an integrated circuit. The test assembly may include structural members that limit movement of components relative to each other.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: March 20, 2012
    Inventors: Robert C. Shelsky, Kenneth W. Graham, Dennis D. Everson
  • Patent number: 8120024
    Abstract: A semiconductor package and testing method is disclosed. The package includes a substrate having top and bottom surfaces, a semiconductor chip mounted in a centrally located semiconductor chip mounting area of the substrate, and a plurality of test pads disposed on top and bottom surfaces of the substrate and comprising a first group of test pads configured on the top and bottom surfaces of the substrate and having a first height above the respective top and bottom surface of the substrate, and a second group of test pads disposed on the lower surface of the substrate and having a second height greater than the first, wherein each one of the second group of test pads includes a solder ball attached thereto.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: February 21, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-seok Song, Dong-han Kim, Hee-seok Lee
  • Publication number: 20110316574
    Abstract: A prober for testing devices in a repeat structure on a substrate is provided with a probe holder plate, probe holders mounted on the plate, and a test probe associated with each holder. Each test probe is displaceable via a manipulator connected to a probe holder, and a substrate carrier fixedly supports the substrate. Testing of devices, which are situated in a repeat structure on a substrate, in sequence without a substrate movement and avoiding individual manipulation of the test probes in relation to the contact islands on the devices, is achieved in that the probe holders are fastened on a shared probe holder plate and the probe holder plate is moved in relation to the test substrate.
    Type: Application
    Filed: April 26, 2011
    Publication date: December 29, 2011
    Inventors: Frank-Michael WERNER, Matthias ZIEGER, Sebastian GIESSMANN
  • Publication number: 20110309853
    Abstract: The test probe assembly of the invention is used for an electric meter such as a multimeter or the like. The electric meter has a main body. The test probe assembly includes a pair of insulated rods, a pair of probe tips and a pair of leads. The insulated rods are separately provided with two corresponding engaging portions, so that the insulated rods can be combined or detached. One end of each probe tip is fixed in one of the insulated rods and the other ends are protrudent. The leads connect between the insulated rods and main body. The combination or detachment of the test probe assembly may form a variety of configurations for different measured objects.
    Type: Application
    Filed: June 17, 2010
    Publication date: December 22, 2011
    Inventor: Po-Chao TAN
  • Publication number: 20110291683
    Abstract: A substrate support unit adapted for a system for testing or processing of a substrate is provided. The substrate support unit includes a support table having at least one substrate carrier structure adapted to support a substrate, wherein the substrate carrier structure is electrically floating with respect to ground.
    Type: Application
    Filed: June 16, 2010
    Publication date: December 1, 2011
    Applicant: APPLIED MATERIALS, INC.
    Inventor: Bernhard Gunter MUELLER
  • Patent number: 8067718
    Abstract: A probe comprises a small “consumable” probe substrate permanently mounted to a circuit-under-test. The probe substrate includes a high-fidelity signal pathway, which is inserted into a conductor of the circuit-under-test, and a high-bandwidth sensing circuit which senses the signal-under-test as it propagates along the signal pathway. The probe substrate further includes a probe socket for receiving a detachable interconnect to a measurement instrument. Power is alternatively supplied to the probe by the circuit-under-test or the interconnect. When the interconnect is attached, control signals from the measurement instrument are supplied to the sensing circuit and the output of the sensing circuit is supplied to the measurement instrument. In one embodiment, the sensing circuit uses high-breakdown transistors in order to avoid the use of passive attenuation. In a further embodiment, the sensing circuit includes broadband directional sensing circuitry.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: November 29, 2011
    Assignee: Tektronix, Inc.
    Inventors: Robert A. Nordstrom, William Q. Law, Mark W. Nightingale, Einar O. Traa, Ira G. Pollock
  • Publication number: 20110285415
    Abstract: A ground terminal has a cylindrical main body. A signal terminal has a terminal main body that is disposed on the inside of the cylindrical main body, and a connecting plate portion that extends from an end portion of the terminal main body. Additionally, a ground terminal has at least three connecting plate portions that are disposed so as to encompass the connecting plate portion of the ground terminal, each extending from mutually different positions on an edge of the cylindrical main body.
    Type: Application
    Filed: May 18, 2011
    Publication date: November 24, 2011
    Applicants: Advantest Corporation, Molex Japan Co., Ltd.
    Inventors: Ryo Uesaka, Jun Watanabe, Akinori Mizumura, Hirotaka Wagata
  • Patent number: RE43739
    Abstract: A test probe for a finger tester for the testing of non-componented circuit boards has a test needle with a probe tip which may be brought into contact with a circuit board test point, and which may be pivotably attached to a mount by means of at least two flexible sprung retaining arms. It is distinguished by the fact that at least one of the retaining arms is made of an electrically conductive material and is electrically connected to the test needle. In a corresponding finger tester, the test probe is driven by a linear motor.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: October 16, 2012
    Assignee: ATG Luther & Maelzer GmbH
    Inventor: Victor Romanov