Abstract: A voice analyzer analyzes whether a voice signal input into a voice input unit includes a specific characteristic component. A voice recognizer recognizes a voice represented by the voice signal input into the voice input unit. A response instruction unit instructs a response to a response operation unit that operates in response to the voice recognized by the voice recognizer. A controller controls the voice recognizer not to execute voice recognition processing by the voice recognizer or controls the response instruction unit not to instruct the response operation unit about an instruction content by the voice recognized by the voice recognizer, when the voice analyzer analyzes that the voice signal includes the specific characteristic component.

Abstract: In some implementations, a radiofrequency down converter comprises an input port to receive a radiofrequency input signal, and the down converter includes a first bandpass filter configured to filter the input signal. The down converter includes a mixer stage coupled to the bandpass filter, the mixer stage being configured to generate a mixer output signal by processing the filtered input signal using a gain adjustment device, one or more amplifiers, and a mixer. The down converter includes a signal adjustment stage coupled to receive the mixer output signal, the signal adjustment stage comprising: a temperature compensation device configured to compensate for changes in signal gain due to changes in temperature; a second bandpass filter; a gain adjustment device; one or more amplifiers; and a low pass filter. The down converter comprises an output port coupled to output an adjusted mixer output signal from the signal adjustment stage.

Abstract: An apparatus and method identify emitters. The apparatus includes a receiver, a parameter estimator, a database, and a correlator. The receiver receives an electromagnetic signal from an emitter and measures actual values of observed parameters of the electromagnetic signal. The parameter estimator surmises surmised values of unobserved parameters from the actual values of the observed parameters. The actual values of the observed parameters and the surmised values of the unobserved parameters characterize the emitter. The database stores one or more entries for each emitter. Each entry specifies an identifier of an emitter and exemplary values of the observed and unobserved parameters. The correlator matches the actual values of the observed parameters and the surmised values of the unobserved parameters with the exemplary values of one of the entries of the emitter from which the receiver receives the electromagnetic signal. The correlator outputs the identifier from this entry in the database.

Abstract: A stepped frequency radar system is disclosed. The system includes components for performing stepped frequency scanning across a frequency range using frequency steps of a step size, the stepped frequency scanning performed using at least one transmit antenna and a two-dimensional array of receive antennas, changing at least one of the step size and the frequency range, and performing stepped frequency scanning using the at least one transmit antenna and the two-dimensional array of receive antennas and using the changed at least one of the step size and the frequency range.

Abstract: An apparatus for detecting group delay information over frequency for a transmission medium has: a receiver for receiving a measurement signal, the measurement signal comprising at least a first carrier signal at a first carrier frequency, a second carrier signal at a second carrier frequency and a third carrier signal at a third carrier frequency; a frequency analyzer for analyzing the reception signal to obtain reception phase information on the first carrier signal, the second carrier signal and the third carrier signal; and a processor for forming a first combined piece of phase information and for forming a second combined piece of phase information, for forming a first piece of group delay information and for forming a second piece of group delay information, and for associating the first piece of group delay information to a first frequency and the second piece of group delay information to a second frequency.

Abstract: Circuitry and methods of operating the same to strobe a DQ signal with a gated DQS signal are described. Some aspects are directed to a gating scheme to selectively pass a received strobe signal such as a DQS strobe signal based on a state of a drive enable (DE) signal in a drive circuit in the ATE, such that edges generated by the drive circuit are prevented from mistakenly strobing a received data signal such as a DQ signal.

Abstract: An emitter ID ambiguity reduction system includes a Mission Data File Ambiguity Resolution matrix that contains both a) the INTEL-based emitter parameters data necessary to break emitter-by-emitter ambiguities, and b) the action(s) the Electronic Warfare (EW) system is to take to collect that data. Control software is triggered via either external command or per Mission Data File information (such as that contained in the Ambiguity Resolution Matrix). The emitter ID ambiguity reduction system includes Data collection hardware and firmware and Data Analysis OFP software algorithm(s).

Abstract: A semiconductor device including scan configuration circuitry that reconfigures latches of the device into a scan chain in response to assertion of a scan enable control signal, and scan control circuitry including delay circuitry, scan enable circuitry, evaluation circuitry, and scan reset circuitry. The scan reset circuitry keeps each of the secure latches in a predetermined reset state until assertion of both an evaluation signal and a scan mode signal. The delay circuitry includes N series-coupled flip-flops selected from different cell libraries detecting assertion of the scan mode signal and asserting a delay output signal only after N transitions of a test clock. The scan enable circuitry asserts the scan enable control signal when a scan enable command signal and the delay output signal are both asserted. The evaluation circuitry asserts the evaluation signal only when a collective state of the delay circuitry has achieved a predetermined state.

Abstract: A Multi-Signal Instantaneous Frequency Measurement, MIFM, system comprising a front end adapted to shift and combine signal spectra of different sub-frequency bands (SFBs) of a received wideband signal (WBS) into an intermediate frequency band (IFB) having an instantaneous bandwidth (IBW), wherein each shifted SFB signal spectrum is marked individually with SFB marking information associated with the respective sub-frequency band (SFB) and a digital receiver (3) having the instantaneous bandwidth (IBW) configured to process the shifted SFB signal spectra within the intermediate frequency band (IFB) using the SFB marking information to resolve any frequency ambiguity caused by the shifting and combining of the SFBs signal spectra.

Abstract: A sound receiving system is disclosed, each of the plurality of basic array devices has an output terminal connected with one filter, each of the plurality of filters has an output terminal connected with an input terminal of the second sound-mixing output device; the basic array device includes a microphone array, the microphone array includes a plurality of microphones longitudinally arranged along a straight line in order, and two adjacent microphones in the microphone array are separated with a distance of 1 n ? ? ; each microphone has an output terminal connected with one of the time delay circuits, each time delay circuit has an output terminal connected with an input terminal of the first sound-mixing output device; and the i-th time delay circuit has a delay time defined by adding (n-i) times of unit time to a delay time of the last time delay circuit.

Abstract: A timing skew characterization apparatus comprises a coarse timing skew characterization circuit, a fine timing skew characterization circuit and a coarse delay cell calibration circuit. The coarse timing skew characterization circuit comprises a plurality of coarse delay cells whose delays can be calibrated through the coarse delay cell calibration circuit. The calibration of fine delay cells can be implemented through a trail and error process. Both coarse delay step and fine delay step can be characterized through a single measurement setup. As a result, the timing skew characterization apparatus provides a high resolution setup and hold time measurement.

Abstract: A method of measuring signal delay in a integrated circuit comprising applying a common clock signal at a circuit input and output, applying a test signal at the circuit input, detecting a corresponding output signal at the circuit output and detecting whether the test signal and output signal occur in a common part of the clock signal.

Abstract: A first timing comparator TCP1 latches a data signal at a timing that corresponds to each edge of a first strobe signal. A first delay element delays a first strobe signal so as to output a first delayed strobe signal. A first clock recovery unit makes a comparison between the phase of the first delayed strobe signal and a clock signal, and outputs a first reference strobe signal which is used to perform phase adjustment such that the phases of these signals match each other. A third delay element delays a first reference strobe signal, and outputs the signal thus delayed as the first strobe signal. A delay amount that corresponds to the amount of skew that occurs between the data signal and the clock signal is set for the third delay element.

Abstract: A timing detection device includes a draw back amount acquiring unit and a detecting unit. The draw back amount acquiring unit is configured to acquire a draw back amount of a received signal with respect to a peak value of the signal. The detecting unit is configured to detect the timing at which the draw back amount acquired by the draw back amount acquiring unit has exceeded a constant value as the timing at which a value of the signal is switched.

Abstract: A test structure for gathering switching history effect statistics includes a waveform generator circuit that selectively generates a first test waveform representative of a 1SW transistor switching event, and a second test waveform representative of a 2SW transistor switching event; and a history element circuit coupled to the waveform generator circuit, the history element circuit including a device under test (DUT) therein, and a variable delay chain therein, wherein a selected one of the first and second test waveforms are input to the DUT and the variable delay chain; wherein the history element circuit determines fractional a change in signal propagation delay through the DUT between the 1SW and 2SW transistor switching events, with the fractional change in signal propagation delay calibrated with timing measurements of a variable frequency ring oscillator; and wherein the test structure utilizes only external low-speed input and output signals with respect to a chip.

Abstract: A digital signal delay measuring circuit for measuring a delay time of a digital signal of a scan-testable digital circuit inside a device to be tested is provided. The circuit includes: outputting means for outputting a delay time measuring signal as a digital signal; delay means for delaying a timing when a state of the delay time measuring signal is changed; and at least two signal holding means, each receiving the delay time measuring signal and holding the state of the delay time measuring signal at a holding-command input timing.

Abstract: Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements.

Abstract: A test pattern for analyzing a delay characteristic of an interconnection line and a method of analyzing a delay characteristic of an interconnection line using the test pattern are provided. The test pattern for analyzing a delay characteristic of an interconnection line includes: a first metal line formed as a snake shaped structure having a plurality of concave-convex sections each having the same width; a second metal line having a comb shape formed on the same layer as the first metal line such that a plurality of teeth portions of the second metal line are respectively formed between the concave-convex sections at one side of the first metal line; and a third metal line having a comb shape formed on the same layer as the first metal line such that a plurality of teeth portions of the third metal line are respectively formed between the concave-convex sections at the other side of the first metal line.

Abstract: A circuit board with a processing unit and a delay line with a controllable number of delay elements fabricated thereon includes apparatus for testing and calibrating the delay line elements. In the test mode, a calibrated pulse is delayed by the delay line while determining the logic state of pulse at two times, the interval between the two times being the same as the pulse width. By adding delay elements, the period of the calibrated pulse as a function of number of delay elements can determine the delay of each delay element. In the calibration mode, the delay line is configured as a ring oscillator and the frequency of the ring oscillator as a function of number of delay elements provides the time delay for the individual elements.

Abstract: A high frequency delay circuit operable to output a high frequency signal delayed for a desired delay time. The high frequency delay circuit includes: a variable delay circuit operable to receive a reference signal of which a frequency is lower than the high frequency signal, and to output a delay reference signal delayed from the reference signal for the desired delay time in advance; and a multiplier operable to generate the high frequency signal, of which a frequency is a frequency of the delay reference signal multiplied by a predetermined value, and to output the generated high frequency signal at timing according to a phase of the delay reference signal.

Abstract: A communications apparatus and method use tapped delay lines as multiplexers and demultiplexers. In one embodiment, a receiver (100) uses a tapped delay line (110) as a demultiplexer to acquire a burst communication at very high data rates in the range of 2.5 to 80 Gbps with low preamble overhead. A sliding window correlator (114) continually samples the delay line (110) to determine when a PN encoded word is contained therein. The transmission frequency is pre-acquired before any data is present through the use of a ring oscillator frequency calibration loop (130) that is imbedded within the tapped delay line (110).

Abstract: According to the methods of the invention, a further delayed DLL signal is compared to the reference clock and a delayed reference clock signal is compared to a DLL signal. These two comparisons are performed on the 360° signal and on the 180° signal. The delay introduced by the methods of the invention is preferably adjustable based on the results of a process monitor test. The process monitor test can be run continuously and accounts for process, voltage and temperature. The methods of the invention can also be used to test for clock skew in a clock tree on a chip.

Abstract: An analog delay circuit to impart a group delay to an analog input signal is described. The analog delay circuit may comprise a capacitor to impart at least a portion of the group delay to the analog output signal and a buffer circuit coupled between the capacitor and an input stage to substantially remove at least a portion of a capacitive load at the input stage.

Abstract: A testing approach involves selective application of clock signals to target circuitry. In an example embodiment (300), a target circuit (332) having logic circuitry that processes data in response to an operational clock signal (308) having at least one clock period, is analyzed for delay faults. Test signals are applied to the logic circuitry while the logic circuitry is clocked with a high-speed test clock (309) having several clock-state transitions that occur during at least one clock period of the operational clock (308). An output from the logic circuitry is analyzed for its state (e.g., as affected by delay in the circuitry). Delay faults are detected as a difference in state of the output of the logic circuitry. With this approach, circuits are tested using conventional testers (340) that operate at normal (e.g., slow) speeds while selectively clocking selected portions of the circuit at higher speeds for detecting speed-related faults therein.

Abstract: Delay-locked loops, signal locking methods and devices and system incorporating delay-locked loops are described. A delay-locked loop includes a forward delay path, a feedback delay path, a phase detector and a timer circuit. The forward delay path alternatively couples to an external clock signal and to an internal test signal. The phase detector adjusts a delay line based upon the phase differences of a feedback signal and the external clock signal. The timer circuit switches the test signal into the forward delay path and measures the time of traversal of the test signal around the forward delay path and the feedback delay path and generates a time constant for configuring the phase detector's update period. The phase detector is thereafter able to stabilize at an improved rate.

Abstract: An inexpensive, small, low-power consumption, wide-band, high resolution spectrum analyzer is provided as a listening device for throw-away applications such as surveillance that involve deployment of large numbers of battery-powered spectrum analyzer modules to detect a signal source such as two-way radio traffic. Power requirements are minimized by the utilization of only one chirp generator to elongate battery life while providing a high resolution result. In order to minimize power drain the spectrum analyzer includes a single compound-chirp Fourier Transform generator. The compound chirp generator is used in one embodiment with a surface acoustic wave, SAW, dispersive delay line in conjunction with a surface electromagnetic wave, SEW dispensive delay line.

Abstract: In a shift clock signal generating apparatus, a delay line includes a plurality of unit delay elements connected in cascade. A reference clock signal propagates in the delay line while being successively delayed by the unit delay elements. Switches have first ends connected with output terminals of the unit delay elements respectively, and second ends connected with a shift clock signal output path. When specified one among the switches is in its on position, a delayed clock signal which results from delaying the reference clock signal by a prescribed time interval is transmitted via the specified switch to the shift clock signal output path as a shift clock signal. The specified one among the switches is determined on the basis of data representing a phase difference of the shift clock signal from the reference clock signal. The specified switch is set in its on position.

Abstract: A signal processing apparatus for providing concurrent electrical frequency measurements of multiple, time-coincident signal inputs. In one embodiment of the present invention, an input signal is received that contains a plurality of individual signals independent of each other in frequency, phase, and electrical amplitude. A power splitter splits the input signal into two separate input signals. A delay line introduces a time delay to one of the two separate input signals. Two Bragg cells within a channelized optical phase measurement (COPM) device modulates two optical carrier signals with the delayed and non-delayed input signals, respectively, separating the modulated delayed and non-delayed input signals into multiple time-concurrent frequency channel signals. Upon exiting the Bragg cells, the two optical beams interfere spatially to develop an interference pattern along the phase and frequency channel number axes of a photodetector array.

Abstract: A phase-locked loop with dual-mode phase/frequency detection is provided. The phase-locked loop circuit includes a dual-mode phase/frequency detector, a loop filter, a voltage-controlled oscillator, and a frequency converter. In addition, the dual-mode phase/frequency detector includes a digital phase/frequency detector, an analog phase/frequency detector, a charge pump, and a control unit. When the phase-locked loop circuit starts, the control unit causes a detection output signal from the dual-mode phase/frequency detector to correspond to a digital signal from the digital phase/frequency detector. When the phase-locked loop circuit approaches a lock state, the control unit causes the detection output signal to correspond to an analog signal from the analog phase/frequency detector. The phase-locked loop with dual-mode phase/frequency detection has the advantages of providing linear characteristics, fast switching speed, and high sensitivity.

Abstract: The present invention provides both differential and integral non-linearity measurement capabilities with a minimum of additional hardware and a test time reduction of several orders of magnitude. The test circuit for N delay lines includes a ring oscillator that has a select signal and an output. A counter is connected in parallel with the ring oscillator. An arithmetic logic unit receives a “COMPARE” value from a register and the counter output. An upper and a lower bound register store acceptable tolerances for non-linearity. Each comparator, upper and lower bound, receives the tolerance stored in the corresponding register and the output of the arithmetic logic unit. An AND gate receives the outputs of the upper and lower bound comparators and generates a signal indicative of the state of the oscillator.

Abstract: The invention accurately determines propagation delay for a sawtooth pattern. Through measurement, the actual delays added per bend in the sawtooth pattern are determined and the values are then used in a CAD tool. The invention can add a known amount of propagation delay to a wire length by routing net wires close together without using a large amount of board space.

Abstract: Arrangements and methods for measuring an antenna signal strength (X) are described, the arrangement comprising:

Abstract: On a semiconductor device 20, fabricated are a VCO 10A, an frequency divider by integer R 21, a frequency divider by integer (P×N+A) 22 wherein each of P, N and A is an integer, A is variable and A<N, a phase comparator 23, and a charge pump 24. A low pass filter 25 having been confirmed to have standard characteristics is externally added to the semiconductor device 20 to construct a PLL circuit to be tested. The frequency divider 22 is of a pulse swallow type and has a control input for setting the integer A at ones in the vicinity of a value in normal use by user. The control input is connected to external terminals D0 and D1 of the semiconductor device 20 for simplifying a test. The semiconductor device 20 is judged whether it is acceptable or not in quality by checking whether or not the PLL circuit enters into a locked state within a given period in each cases of A=A1 and A=A2, where A1<A0<A2 and A0 is a value in normal use by user.

Abstract: A spectrum analyzer having an improved local oscillator for use in a digital step sweep is capable of minimizing a dynamic spurious response which is inverse proportional to a unit step time in the step sweep. The local oscillator includes a random clock delay which provides a random clock to a direct digital synthesizer to incorporate random timings in a time length of the unit step time for sweeping the local oscillator. In another aspect, the local oscillator includes a sweep step number control which maximizes the number of steps in the step sweep to ultimately decrease the dynamic spurious response.