Abstract: The present disclosure relates to a graphene spin transistor for all-electrical operation at room temperature and a logic gate using the graphene Rashba spin transistor. A graphene spin transistor of the present disclosure provides a graphene spin FET (Field Effect Transistor) for all-electrical operation at room temperature without a magnetic field or a ferromagnetic electrode by utilizing the Rashba-Edelstein effect in the graphene or the spin Hall effect of a TMDC (Transition Metal Dichalcogenide) material in order to replace CMOS transistors and extend Moore's Law, and further provides a logic gate using the graphene Rashba spin transistor.

Abstract: A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, and a surface insulating film disposed in a manner extending across the cell portion and the outer peripheral portion, and in the cell portion, formed to be thinner than a part in the outer peripheral portion.

Abstract: A method includes specifying a target memory macro with one or more parameters, finding function-blocks in the target memory macro, and determining failure rates of the function-blocks based on an amount of transistors and area distributions in a collection of base cells. The method includes generating a failure-mode analysis for the target memory macro, from a memory compiler, based on the failure rates of the function-blocks. The method includes determining a safety level of the target memory macro, based upon the failure-mode analysis of the target memory macro.

Abstract: A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, and a surface insulating film disposed in a manner extending across the cell portion and the outer peripheral portion, and in the cell portion, formed to be thinner than a part in the outer peripheral portion.

Abstract: A semiconductor circuit includes a first logic gate that receives inputs of a first input signal, a clock signal and a feedback signal and performs a first logical operation to output a first output signal. A second logic gate that receives inputs of the first output signal of the first logic gate, the clock signal, and an inverted output signal of the first input signal and performs a second logical operation to output the feedback signal.

Abstract: A reference voltage generator is constructed to be equipped with a first constant current circuit which outputs a first constant current with respect to an input voltage, a second constant current circuit which outputs a second constant current, and a voltage generation circuit which generates a voltage based on an input current, and to take a current based on the first constant current and the second constant current as an input current of the voltage generation circuit and output a reference voltage from the voltage generation circuit.

Abstract: A semiconductor circuit includes a first logic gate that receives inputs of a first input signal, a clock signal and a feedback signal and performs a first logical operation to output a first output signal. A second logic gate that receives inputs of the first output signal of the first logic gate, the clock signal, and an inverted output signal of the first input signal and performs a second logical operation to output the feedback signal.

Abstract: A magnetic memory includes a plurality of memory cells and a data identification circuit. Each of the memory cells includes: a first bias node to which a first voltage is applied in data reading, the first voltage being a positive voltage; a second bias node to which a second voltage is applied in the data reading, the second voltage being a negative voltage having substantially the same absolute value as the first voltage; a connection node; a first spin device element connected between the first bias node and the connection node; and a second spin device element connected between the connection node and the second bias node. The first and second spin device elements operate differentially. The data identification circuit identifies data stored in each of the memory cells based on a polarity of a voltage generated on the connection node.

Abstract: A circuit comprising a first injection BJT in a common-base configuration and configured to output a first injection current at its collector. A first multiple-collector BJT is in an open collector configuration, is electrically coupled to the first injection BJT, and is arranged to receive the first injection current at its base. The first multiple-collector BJT has a capacitance load at one of its collectors. A first supply voltage is electrically coupled to the first injection BJT. The first supply voltage is configured to dynamically adjust during operation of the circuit in response to a change in the capacitance load of the first multiple-collector BJT.

Abstract: A spin transistor includes: an input part that is made of a material exhibiting a spin Hall effect and configured to transfer electrons with a predetermined direction of spin to a connecting part; and the connecting part that receives the electrons with the predetermined direction of spin from the input part, rotates the spin of the electrons in accordance with a gate voltage applied to the gate electrode, and transfers the electrons to the output part.

Abstract: A CMOS logic circuit includes a resistive element that is connected to a first voltage line at a first end thereof. The CMOS logic circuit includes a first inverter circuit having a first MOS transistor and a second MOS transistor. The CMOS logic circuit includes a second inverter circuit having a third MOS transistor and a fourth MOS transistor. The CMOS logic circuit includes a fifth MOS transistor that is connected in parallel with the resistive element between the first voltage line and the first end of the first MOS transistor and the gate of which is connected to the second end of the third MOS transistor. The CMOS logic circuit includes a sixth MOS transistor that is connected between the first voltage line and the first output terminal.

Abstract: Apparatus and related fabrication and operating methods are provided for logic circuits that include ferromagnetic elements. An exemplary logic circuit includes a first ferromagnetic element having a first ferromagnetic layer, a second ferromagnetic element having a second ferromagnetic layer, and a transistor coupled to the first ferromagnetic element. The first transistor is configured to allow current to flow through the first ferromagnetic element. The current influences the magnetization direction of the first ferromagnetic layer, which, in turn, influences the magnetization direction of the second ferromagnetic layer.

Abstract: There is provided a complementary spin transistor logic circuit, including: a parallel spin transistor that includes a magnetized first source, a first drain magnetized in parallel with the magnetization direction of the first source, a first channel layer and a first gate electrode; and an anti-parallel spin transistor that includes a magnetized second source, a second drain magnetized in anti-parallel with the magnetization direction of the second source, a second channel layer and a second gate electrode, wherein the first gate electrode and the second gate electrode are connected to a common input terminal.

Abstract: There is provided a complementary spin transistor logic circuit, including: a parallel spin transistor that includes a magnetized first source, a first drain magnetized in parallel with the magnetization direction of the first source, a first channel layer and a first gate electrode; and an anti-parallel spin transistor that includes a magnetized second source, a second drain magnetized in anti-parallel with the magnetization direction of the second source, a second channel layer and a second gate electrode, wherein the first gate electrode and the second gate electrode are connected to a common input terminal.

Abstract: A digital communication system for transmitting and receiving Digital Visual Interface (DVI) communication data signals and Display Data Channel (DDC) communication signals over a transmission line comprises an open-loop equalizer circuit and a DDC extension circuit. The open-loop equalizer circuit is operable to receive DVI communication signals transmitted over the transmission line and output equalized DVI communication data signals. The DDC extension circuit is operable to inject a boost current at the receive end of the transmission line during a positive transition in the DDC communication signal, and clamp the receive end of the transmission line during a negative transition of the DDC communication signal.

Abstract: A new compound derivative that can be used to form a unit molecular film as a rectifier in a molecular electronic device, a new rectifying compound (4,5,9,10-tetrahydro-pyren-2-yl)-carbamic acid 4-(2-methylsulfanyl-alkyl)-3,5-dinitro-benzyl ester and its derivative (4,5,9,10-Tetrahydro-pyren-2-yl)-carbamic acid 4-(2-methylsulfanyl-alkyl)-3,5-dinitro-benzyl ester, and methods of synthesizing the compounds are provided.

Abstract: An HNMOS transistor (4) has its drain electrode connected to the gate electrode of an NMOS transistor (21), and a logic circuit voltage (VCC) is applied to the drain electrode of the NMOS transistor (21) through a resistor (32). A ground potential is applied to the source electrode of the NMOS transistor (21). A drain potential (V2) at the NMOS transistor (21) is monitored by an interface circuit (1), for indirectly monitoring a potential (VS). Thus provided is a high voltage integrated circuit for preventing damage to a semiconductor device used for performing bridge rectification of a power line.

Abstract: In a charge transfer device and a driving method therefor, electrons are injected through an insulating film into floating gate 108 or electrons are extracted through the insulating film from the floating gate 108, whereby the potential of the floating gate is converged to a fixed voltage.

Abstract: A FIFO design interfaces a sender subsystem and a receiver subsystem operating on different time domains. The sender subsystem and the receiver subsystem may be synchronous or asynchronous. The FIFO circuit includes a put interface configured to operate in accordance with the sender time domain and get interface configured to operate in accordance with the receiver time domain. The FIFO circuit includes an array of cells having a register and state controller indicative of the state of the cell. Each cell also has a put component part configured to operate according to the sender time domain including a put token passing circuit and put controller circuit. Each cell has get component part configured to operate according to the receiver time domain including a get token passing circuit and a get controller circuit. A mixed-clock relay station design interfaces a sender subsystem and a receiver subsystem working at different time domains, and where the latency between sender and receiver is large.

Abstract: An IIL reset circuit includes an IIL inverter having input and output terminals, and a capacitor connected to the IIL inverter through the input terminal. When the IIL inverter is supplied with a constant current, it charges the capacitor through the input terminal, and outputs a reset pulse through the output terminal. The reset pulse has a pulse width that is determined based on both a current supplied to the capacitor, and on a capacitance of the capacitor.

Abstract: A circuit configuration and a method for accelerating aging in an MRAM, in which additional means are provided in order to feed a higher current into a control line of a memory cell which is located nearer the soft-magnetic layer. A second transistor is inserted in parallel with the driver transistors, which form a first control unit. The second transistor supplies a current through the control line located nearer the soft-magnetic layer. The second transistor can drive a higher current through the control line and can be activated by means of a test mode.

Abstract: An analog IC includes analog circuit components and digital circuit components formed from plural I2L circuits. The analog IC is supplied with first and second voltages from first and second direct current sources. The analog circuit components are driven by the first voltage and the I2L circuits are driven by the second voltage. At least one I2L circuit is activated before the analog IC receives the first voltage while the remaining at least one I2L circuit is activated after the analog IC receives the first voltage, a switching circuit switching on and off the transmission of the second voltage to the remaining at least one I2L circuit according to a voltage level of the first voltage.

Abstract: The invention allows programming an antifuse so as to reduce the antifuse resistance and the standard deviation of the resistance without increasing the programming current. This is achieved by passing current pulses of the opposite polarity through the antifuse. In some embodiments, the magnitude of the second pulse is lower than the magnitude of the first pulse. Further, if the antifuse is formed on a semiconductor substrate with one electrode on top of the other electrode and on top of the substrate, the current during the first pulse flows from the top electrode to the bottom electrode and not vice versa. A programming circuitry is provided that allows to program antifuses in a programmable circuit. A driver circuit is connected to each "horizontal" channel and each "vertical" channel. Each driver circuit is controlled by data in the driver circuit. The driver circuits are connected into shift registers so that all the data can be entered from one, two, three or four inputs.

Abstract: To provide a type of logic circuit, characterized by the fact that the novel-configuration logic circuit can be easily manufactured in a bipolar process, having a high integration degree and allowing a high-speed operation. For standard longitudinal-type NPN transistor TR0, its emitter E0 is connected to bias terminal BIAS, base B0 is connected to voltage source+Vcc, and collector C0 is connected to base B1 of PNP transistor TR1. For lateral-type PNP transistor TR1, emitter E1 is connected to voltage source Vxx, base B1 is connected to both the collector Co of NPN transistor TR0 and input terminal IN, and collectors C1, C2, C3, . . . Cn are connected to output terminals OUT1, OUT2, PUT3, . . .OUTn, respectively. Schottky diodes SBD1, SBD2, SBD3, . . .SBDn are connected between base B1 and collectors C1, C2, C3, . . . Cn of NPN transistor TR1 with a cathode on the side of the base and with an anode on the side of the collector.

Abstract: A digital communication system for transmitting and receiving Digital Visual Interface (DVI) communication data signals and Display Data Channel (DDC) communication signals over a transmission line comprises an open-loop equalizer circuit and a DDC extension circuit. The open-loop equalizer circuit is operable to receive DVI communication signals transmitted over the transmission line and output equalized DVI communication data signals. The DDC extension circuit is operable to inject a boost current at the receive end of the transmission line during a positive transition in the DDC communication signal, and clamp the receive end of the transmission line during a negative transition of the DDC communication signal.