Abstract: An integrated circuit includes a first multiplexer (mux) with multiple inputs and configured to produce a mux output signal. The electronic circuit also includes a first gated buffer to receive the mux output signal from the first multiplexer and produce a first gated buffer output signal, a second gated buffer to receive the first gated buffer output signal and to produce a second gated buffer output signal to be provided to a pin, and a receive buffer. The receive buffer is coupled to the pin and receives an input signal from the pin. The electronic circuit operates in a test mode in which the second gated buffer is disabled preventing a test signal provided to an input of the first mux from reaching the pin. Instead, the test signal is provided through the first mux to the first gated buffer and to the receive buffer thereby testing the first mux.

Abstract: A method of testing an integrated circuit (IC) having a plurality of dies can include receiving, within a master die of the plurality of dies of the IC, a configuration data set specifying a circuit design, wherein the circuit design is instantiated within the master die. The method can include broadcasting the configuration data set to at least one slave die, wherein the circuit design is instantiated within each slave die and receiving, within the master die, a test vector set. The method also can include broadcasting the test vector set to the at least one slave die and responsive to each die executing the test vector set, storing test output data generated by each die.

Abstract: Techniques and technology are provided to enable the testing of a programmable integrated circuit from within the programmable integrated circuit itself. In various implementations of the invention, a hardware verification module is added to the programmable integrated circuit by the manufacturer. Once the programmable integrated circuit is programmed to have a desired functionality, the hardware verification module may be activated and used to apply tests and receive responses from the programmable integrated circuit to verify its functionality.

Abstract: Transition detection circuitry for detecting during multiple clock cycles, transitions occurring within a detection period in each of said multiple clock cycles at a plurality of nodes within a circuit is disclosed. The transition detection circuitry comprises: a clock signal generator for generating a detection clock signal from a clock signal clocking a sampling element within said circuit, said detection clock signal defining said detection period; a plurality of transition detectors for detecting transitions at respective ones of said plurality of nodes during said detection period, each of said plurality of transition detectors being clocked by said detection clock signal; and combining circuitry for combining said detected transitions output by said plurality of transition detectors to generate a composite transition detection signal.

Abstract: A circuit having a local power block for leakage reduction is disclosed. The circuit has a first portion and a second portion. The first portion is configured to operate at a substantially greater operating frequency than the operating frequency of the second portion. The second portion has a local power block configured to decouple the second portion if the second portion is inactive to reduce leakage current associated with the second portion without sacrificing performance of the first portion.

Abstract: A continuity testing apparatus includes open/short detection circuits provided for to-be-tested terminals, respectively and configured to determine the presence or absence of at least any one of an open-circuit failure and a short-circuit failure in to-be-tested terminals. Then, the continuity testing apparatus generates detected results of the open/short detection circuits based on the condition of continuity of the to-be-tested terminals having connections to the open/short detection circuits and the detected results from the open/short detection circuits in the preceding stages, and outputs the generated detected results to the open/short detection circuits in the succeeding stages. Further, the continuity testing apparatus determines the condition of continuity based on the output from the open/short detection circuit in the last stage.

Abstract: Described are methods and circuits for reducing the error-inducing effects of crosstalk. Communication circuits in accordance with some embodiments adjust the phase of transmitted “aggressor” data to misalign transmitted signals from the perspective of “victim” channels. This misalignment moves the noise artifacts cross coupled to the victim channel away from sensitive sample times in the victim data, and consequently reduces the net effects of aggressor crosstalk on neighboring victim channels. Some embodiments reduce the effects of crosstalk by introducing static timing offsets to one or a plurality of aggressor transmitters, one or a plurality of victim transmitters, or some combination of aggressor and victim transmitters. Other embodiments dynamically alter the relative timing of aggressor and victim transmitters.

Abstract: A semiconductor integrated circuit includes first and second bump pads configured to output data, a probe test pad coupled to the first bump pad, and a pipe latch unit configured to selectively transfer data loaded on first and second data lines to one of the first and second bump pads in response to a pipe output dividing signal during a normal mode, and sequentially transfer the data loaded on the first and second data lines to the probe test pad in response to the pipe output dividing signal during a test mode.

Abstract: A circuit and method of directly measuring the Single Event Transient (SET) performance of a combinatorial circuit includes a measurement chain. The measurement chain includes a plurality of cells, each in turn including a pair of SR latches, a dual-input inverter, and a target. During measurement and testing, the targets are irradiated, and a pulse signal caused by an SET event is allowed to propagate through the measurement chain only if the pair of SR latches are active at the same time. The pulse signal is latched by the measurement chain, thus allowing the presence of an SET event to be detected.

Abstract: A semiconductor chip includes a first power supply line and a second power supply line. A first switch is coupled between the first power supply line and the second power supply line, and a second switch is coupled between the first power supply line and the second power supply line. A circuit is coupled to the second power supply line. A first control signal line is coupled to the first switch, and a second control signal line coupled to the second switch. A logic gate is coupled to the first and the second control signal lines and a terminal is coupled to the logic gate to output a signal to an outside of the semiconductor chip.

Abstract: A configurable die stack arrangement including a first configurable integrated circuit die located on a first substrate. The first configurable integrated circuit die includes a first array and a first configuration memory management circuit that includes an interface to the first array. The first array includes a first logic element and a first configuration memory. The configurable die stack arrangement also includes a second configurable integrated circuit die located on a second substrate that is different than the first substrate. The second configurable integrated circuit die includes a second array and a second configuration memory management circuit that includes an interface to the second array. The second array includes a second logic element and a second configuration memory. A signal is coupled to the first configuration management circuit and to the second configuration management circuit, and the first configuration memory management circuit includes circuitry to control the signal.

Abstract: The peripheral circuitry (350, 360, ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die.

Abstract: A multiple level integrated circuit uses an array of oppositely oriented individually enabled buffers between through-silicon vias (TSVs) and a clocked flip-flop, for each of multiple signal lines that include TSVs. Applying and/or reading logic levels to and from the TSVs and associated flip-flops produces values that a logic element compares to expected values characterizing nominal operation or detects open and short circuit defects. A process associated with testing the TSVs during assembly comprises testing for short circuits and then exposing and connecting the TSVs via a conductive layer to check for open circuits.

Abstract: A semiconductor integrated circuit according to one embodiment includes a plurality of flip-flop groups configured by dividing a plurality of flip-flops, connected in series, for carrying out a serial operation of serially transferring data, a continuous signal determination circuit configured to output a first signal if outputs of the flip-flops contained in the flip-flop group match, and output a second signal in other cases; and a clock gating circuit configured not to provide a clock signal when receiving the first signal and to provide a clock signal when receiving the second signal with respect to the flip-flops other than a head of the flip-flop group.

Abstract: Exemplary method, computer-accessible medium, and test configuration can be provided for testing at least one flip-flop. For example, the exemplary test configuration can include at least one scan-out channel having a plurality of regions and a plurality of compactors associated with the plurality of regions.

Abstract: In an example embodiment there is described herein an apparatus, comprising a device having an input and an output, a controllable selecting device having a first input coupled to input of the device and a second input coupled to the output of the device, and a selection control circuit having a test input for receiving a test signal and a power mode input for receiving a power mode signal. The selection control circuit is coupled to the controllable selecting device and operable to control which input the controllable selecting device selects. The selection control circuit is configured to select the first input to isolate the device responsive to the test signal indicating no testing is being performed the power mode signal indicating a low power mode.

Abstract: A circuit and method of directly measuring the Single Event Transient (SET) performance of a combinatorial circuit includes a measurement chain. The measurement chain includes a plurality of cells, each in turn including a pair of SR latches, a dual-input inverter, and a target. During measurement and testing, the targets are irradiated, and a pulse signal caused by an SET event is allowed to propagate through the measurement chain only if the pair of SR latches are active at the same time. The pulse signal is latched by the measurement chain, thus allowing the presence of an SET event to be detected.

Abstract: A system for monitoring a device under test implemented within an integrated circuit (IC) can include at least one probe that detects a designated type of data transaction, where in response to detecting the designated type of data transaction, each probe outputs a single data transaction detection signal. The system also can include a data collector coupled to each probe, where the data collector stores an indication of each data transaction detection signal that is output by each probe. The data collector can be configured so that no value of any probed signal is stored.

Abstract: A semiconductor device includes a pump voltage detecting unit, an oscillation signal generating unit, and a pump voltage generating unit. The pump voltage detecting unit is configured to detect the level of a pump voltage based on a target level varying in response to a test signal. The oscillation signal generating unit is configured to generate an oscillation signal in response to an output signal of the pump voltage detecting unit, wherein the frequency of the oscillation signal varies in response to the test signal. The pump voltage generating unit is configured to generate the pump voltage by performing a charge pumping operation at a speed corresponding to the frequency of the oscillation signal.

Abstract: A circuit and method of directly measuring the Single Event Transient (SET) performance of a combinatorial circuit includes a measurement chain. The measurement chain includes a plurality of cells, each in turn including a pair of SR latches, a dual-input inverter, and a target. During measurement and testing, the targets are irradiated, and a pulse signal caused by an SET event is allowed to propagate through the measurement chain only if the pair of SR latches are active at the same time. The pulse signal is latched by the measurement chain, thus allowing the presence of an SET event to be detected.

Abstract: A method for testing a set of circuitry in an integrated circuit (IC) is described. The IC includes multiple configurable circuits for configurably performing multiple operations. The method configures the IC to operate in a user mode with a set of test paths that satisfies a set of evaluation criteria. Each test path includes a controllable storage element for controllably storing a signal that the storage element receives. The method operates the IC in user mode. The method reads the values stored in the storage elements to determine whether the set of circuitry is operating within specified performance limits.

Abstract: A method may include receiving a first set of parameters associated with a test environment, the test environment including a test system for testing a network, receiving a test objective, conducting a first test case based on the received first set of parameters and the test objective, automatically determining, by the test system, whether the test objective has been satisfied based on a first test result associated with the first test case, and automatically adapting, by the test system, a second test case based on the first test result when it is determined that the test objective has not been satisfied.

Abstract: Embodiments of the invention provides a method, device, and system for programming an electromigration fuse (eFuse) using a radio frequency (RF) signal. A first aspect of the invention provides a method of testing circuitry on a semiconductor chip, the method comprising: receiving a radio frequency (RF) signal using at least one antenna on the semiconductor chip; powering circuitry on the semiconductor chip using the RF signal; activating a built-in self test (BIST) engine within the circuitry; determining whether a fault exists within the circuitry using the BIST; and programming an electromigration fuse (eFuse) to alter the circuitry in response to a fault being determined to exist.

Abstract: According to an embodiment of the disclosure, a method verifies bitmap information or test data information for a semiconductor device. The method places a defect on a semiconductor device at an actual defect location using a laser to physically damage the semiconductor device. A logical address associated with the defect is detected and bitmap information or test data information is reviewed to determine an expected location corresponding to the logical address. Then, the accuracy of the bitmap information or the test data information is determined by comparing the actual defect location with the expected location. A deviation between the two indicates an inaccuracy.

Abstract: In one embodiment, an integrated circuit includes a self calibration unit configured to iterate a test on a logic circuit in the integrated circuit at respectively lower supply voltage magnitudes until the test fails. A lowest supply voltage magnitude at which the test passes is used to generate a requested supply voltage magnitude for the integrated circuit. In an embodiment, an integrated circuit includes a series connection of logic gates physically distributed over an area of the integrated circuit, and a measurement unit configured to launch a logical transition into the series and detect a corresponding transition at the output of the series. The amount of time between the launch and the detection is used to request a supply voltage magnitude for the integrated circuit.

Abstract: Selective blocking is applied to discrete segments of scan chains in the integrated circuit device. In some implementations, locking components associated with the scan segments are selectively activated according to blocking data incorporated in test pattern data. In other implementations, selective blocking is applied to the scan cells identified as causing the highest power consumption. Selective incorporation of blocking components in an integrated circuit device is based on statistical estimation of scan cell transition rates. When the blocking components are enabled, pre-selected signal values are presented to the functional logic of the integrated circuit device. At the same time, propagation of output value transitions that may take place in the scan cells is prevented.

Abstract: In a test and debug system in which a plurality of selectable modules under test have different operational rates, a selection unit associated with each module is used to control the application of the RCLK signal from the module to the combiner unit, the combiner unit providing a composite RCLK signal. Each selection unit has output signals of RCLK_NE and RCLK_PE signals which are applied to an combiner unit to form the composite RCLK signal. In response to the SELECT signal, the RCLK_NE and RCLK_PE are synchronized with the module RCLK signal. When the SELECT signal is removed, the RCLK_NE and RCLK_PE signals are continuously applied to the combiner unit.

Abstract: The peripheral circuitry (350, 360, ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die.

Abstract: According to one embodiment, an input circuit includes an input buffer, a control unit, a holding unit, a feedback unit. The input buffer receives a signal input from an outside. The input buffer includes a plurality of CMOS inverters connected in parallel. The plurality of CMOS inverters includes a plurality of PMOS transistors and a plurality of NMOS transistors. The control unit selects one or more PMOS transistors from the plurality of PMOS transistors so as to enter an operable state. The control unit selects one or more NMOS transistors from the plurality of NMOS transistors so as to enter an operable state. The holding unit holds a level of a signal transferred from the input buffer in synchronization with a clock signal. The holding unit outputs the held signal level. The feedback unit feeds the level of the signal output from the holding unit back to the control unit.

Abstract: An integrated circuit (IC) includes self-calibrating programmable digital logic circuitry. The IC includes at least one programmable digital logic cell, wherein the first programmable digital logic cell provides (i) a plurality of different accessible circuit configurations or (ii) a voltage level controller. A self-calibration system is provided that includes at least one reference device, a measurement device for measuring at least one electrical performance parameter that can affect a processing speed of the first programmable digital logic cell or at least one parameter that can affect the electrical performance parameter using the reference device to obtain calibration data. A processing device maps the calibration data or a parameter derived therefrom to generate a control signal that is operable to select from the plurality of different accessible circuit configurations or a voltage level output to change the processing speed of the programmable digital logic cell.

Abstract: A scan flip-flop circuit includes an input unit and an output unit. The input unit selects one of a data input signal and a scan input signal depending on an operation mode and generates an intermediate signal based on the selected signal. The output unit generates an output signal based on the intermediate signal and selects one of a data output terminal and a scan output terminal depending on the operation mode to provide the output signal through the selected output terminal. A voltage level at the selected output terminal bidirectionally transitions between a first voltage level and a second voltage level. A voltage level at a non-selected output terminal unidirectionally transitions between the first voltage level and the second voltage level.

Abstract: A Field Programmable Gate Arrays (FPGA) connection control board is provided. The FPGA connection control board includes a printed circuit board (PCB), a plurality of first connection terminals formed at an upper part of the PCB, a plurality of second connection terminals formed at a lower part of the PCB and a plurality of switches each for selectively connecting each of the plurality of first connection terminals with each of the plurality of second connection terminals.

Abstract: Sequential electronic circuit (10) reacting on a rising edge and a falling edge of a clock signal (CK), comprising a first (1) and a second (2) D-type flip-flop, a main multiplexer (3) coupled at input to the flip-flops (1 and 2), the circuit (10) comprising a first input receiving the clock signal (CK) and a second input receiving a control signal (TE) so as to control the circuit (10) according to a normal operating mode and a test operating mode making it possible to check the proper operation of the sequential electronic circuit (10). The clock signal (CK) used in the normal operating mode is used to gate the circuit (10) during the test operating mode.

Abstract: A method for testing a set of circuitry in an integrated circuit (IC) is described. The IC includes multiple configurable circuits for configurably performing multiple operations. The method configures the IC to operate in a user mode with a set of test paths that satisfies a set of evaluation criteria. Each test path includes a controllable storage element for controllably storing a signal that the storage element receives. The method operates the IC in user mode. The method reads the values stored in the storage elements to determine whether the set of circuitry is operating within specified performance limits.

Abstract: Various example embodiments are disclosed. According to one example embodiment, an integrated circuit may include a mode block, a plurality of data blocks, and a reset node. The mode block may be configured to output a test mode signal, a scan mode signal, and a trigger signal based on a received data input. The plurality of data blocks may each include registers configured to store data, each of the plurality of data blocks being configured to write over at least some of the data stored in their respective registers in response to receiving a write-over instruction. The reset node may be configured to reset the registers based on receiving either a first reset input or a second reset input. The integrated circuit may be configured to enter a test mode, enter a scan mode, and exit the test mode.

Abstract: An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan distributor circuit (800) receives serial test data from a peripheral bond pad (802) and distributes it to each parallel scan path. A scan collector circuit (844) collects test data from the parallel scan paths and applies it to a peripheral bond pad (866). This enables more parallel scan paths of shorter length to connect to the functional circuits. The scan distributor and collector circuits can be respectively connected in series to provide parallel connections to more parallel scan paths. Additionally multiplexer circuits (886,890) can selectively connect pairs of scan distributor and collector circuits together.

Abstract: An integrated circuit having a monitor circuit for monitoring timing in a critical path having a target timing margin is disclosed. The monitor circuit has two shift registers, one of which includes a delay element that applies a delay value to a received signal. The inputs to the two shift registers form a signal input node capable of receiving an input signal. The monitor circuit also has a logic gate having an output and at least two inputs, each input connected to a corresponding one of the outputs of the two shift registers. The output of the logic gate indicates whether the target timing margin is satisfied or not satisfied.

Abstract: Provided is a semiconductor integrated circuit capable of testing power control operation in the semiconductor integrated circuit including a power controllable region. Power control switches have switch series each constituted by a plurality of switch cells. A power controllable region includes output nodes in the switch series. The output nodes output power control signals that have passed through final stages of the respective switch series of the power control switches to the outside of the power controllable region. A chip on which the semiconductor integrated circuit is mounted has output terminals that output outputs of the output nodes to the outside of the chip. In the case of inserting a scan path test, observation flip-flops that load the outputs of the output nodes to data terminals, and load scan data to scan-in terminals are disposed in correspondence with the respective output nodes. Those observation flip-flops are connected to constitute a scan path chain.

Abstract: When an operation of a specified one of monitor circuits is defective or any of elements forming a ring oscillator in each of the monitor circuits has characteristic abnormality, if voltage control is performed based on a result from the monitor operating at a lowest speed, a required voltage may be overestimated. This results in an increase in power consumption, and also causes an accuracy reduction when the average value of detection results from the multiple monitors is calculated. The multiple monitor circuits are provided. Of the detection results therefrom, any detection result falling outside a predetermined range is ignored, and the average value of the remaining monitor results is used as a final monitor detection value.

Abstract: An fusing apparatus for correcting process variation is provided. The fusing apparatus for correcting the process variation of the semiconductor device includes a fusing part including a fusing resistor fused by a current penetrating; a current driving transistor for fusing the fusing resistor by driving a fusing current according to a fusing enable signal applied; a current path part for building a current path by connecting to the fusing part, and controlling a first node voltage according to a fusing state of the fusing resistor; and a latch part for latching a second node signal inversely amplified from the first node voltage, and outputting the latch value when a power-on reset part operates in a normal mode. Using the fusing cell, the test time can be reduced and the current consumption can be greatly decreased in the fusing process.

Abstract: A receiving circuit includes: a terminating resistor to set a terminating level of a transmission line for transmitting a reception signal including a signal having a first level indicating a preamble; a detection circuit to detect whether a level of the transmission line is the first level or a second level; and an adjustment circuit to adjust a resistance of the terminating resistor, the adjustment circuit adjusting the resistance of the terminating resistor to a value such that the detection circuit detects the level of the transmission line as the second level when a data request is output to a transmitting side.

Abstract: A semiconductor integrated circuit includes first and second bump pads configured to output data, a probe test pad coupled to the first bump pad, and a pipe latch unit configured to selectively transfer data loaded on first and second data lines to one of the first and second bump pads in response to a pipe output dividing signal during a normal mode, and sequentially transfer the data loaded on the first and second data lines to the probe test pad in response to the pipe output dividing signal during a test mode.

Abstract: A logic built-in self test (LBIST) system comprises a device under test having a first plurality of first bistable multivibrator circuits an LBIST controller, and a second plurality of second bistable multivibrator circuits. Each second bistable multivibrator circuit is coupled to a corresponding first bistable multivibrator circuit to swap a second state value kept by the second bistable multivibrator circuit with a first state value kept by the corresponding first bistable multivibrator circuit depending on a first control signal from the LBIST controller and the second bistable multivibrator circuits are coupled to form one or more scan chains when receiving a second control signal from the LBIST controller.

Abstract: A semiconductor device includes a first pad, a second pad and a third pad. The first pad and the third pad are electrically connected to each other. The first pad and the second pad are used for bonding. The second pad and the third pad are used for probing. According to this structure, Small size semiconductor device having high reliability even after a probing test can be provided.

Abstract: A semiconductor device includes a plurality of pads configured to receive a plurality of external signals, an internal circuit configured to perform a predetermined internal operation in response to one of the external signals that is inputted through one of the plurality of pads, and a signal transferring unit configured to receive the external signal, output the external signal to an internal circuit an output signal during a normal mode, and output a fixed signal regardless of changes in the external signal to the internal circuit in a test mode.

Abstract: An on-chip sensor measures dynamic power supply noise, such as voltage droop, on a semiconductor chip. In-situ logic is employed, which is sensitive to noise present on the power supply of functional logic of the chip. Exemplary functional logic includes a microprocessor, adder, and/or other functional logic of the chip. The in-situ logic performs some operation, and the amount of time required for performing that operation (i.e., the operational delay) is sensitive to noise present on the power supply. Thus, by evaluating the operational delay of the in-situ logic, the amount of noise present on the power supply can be measured.

Abstract: An internal voltage generating circuit is utilized to perform a TDBI (Test During Burn-in) operation for a semiconductor device. The internal voltage generating circuit produces an internal voltage at a high voltage level, as an internal voltage, in not only a standby section but also in an active section in response to a test operation signal activated in a test operation. Accordingly, dropping of the internal voltage in the standby section of the test operation and failure due to open or short circuiting are prevented. As a result, reliability of the semiconductor chip, by preventing the generation of latch-up caused by breakdown of internal circuits, is assured.

Abstract: A method is provided for thermal electric binary logic control. The method accepts an input voltage representing an input logic state. A heat reference is controlled in response to the input voltage. The method supplies an output voltage representing an output logic state, responsive to the heat reference. More explicitly, the heat reference controls the output voltage of a temperature-sensitive voltage divider. For example, the temperature-sensitive voltage divider may be a thermistor voltage divider.

Abstract: An fusing apparatus for correcting process variation is provided. The fusing apparatus for correcting the process variation of the semiconductor device includes a fusing part including a fusing resistor fused by a current penetrating; a current driving transistor for fusing the fusing resistor by driving a fusing current according to a fusing enable signal applied; a current path part for building a current path by connecting to the fusing part, and controlling a first node voltage according to a fusing state of the fusing resistor; and a latch part for latching a second node signal inversely amplified from the first node voltage, and outputting the latch value when a power-on reset part operates in a normal mode. Using the fusing cell, the test time can be reduced and the current consumption can be greatly decreased in the fusing process.

Abstract: A semiconductor integrated circuit includes first and second bump pads configured to output data, a probe test pad coupled to the first bump pad, and a pipe latch unit configured to selectively transfer data loaded on first and second data lines to one of the first and second bump pads in response to a pipe output dividing signal during a normal mode, and sequentially transfer the data loaded on the first and second data lines to the probe test pad in response to the pipe output dividing signal during a test mode.