Output Switching Noise Reduction Patents (Class 326/26)
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Patent number: 10027311Abstract: To provide an inexpensive semiconductor device capable of suppressing the influence by crosstalk. A semiconductor device includes a signal wiring disposed in an organic interposer, an output circuit which is coupled to a first end of the signal wiring and which sets an impedance so as to generate a reflected wave antiphase to a waveform transmitted to the first end and periodically outputs data, and an input circuit which is coupled to a second end of the signal wiring and sets an impedance so as to generate a reflected wave of the same phase as a waveform transmitted to the second end. An average delay of the signal wiring is set to be 1/integer of 2 or more relative to a half of a cycle of the data. A difference between the maximum and minimum values of a delay of a signal at each of other signal wirings disposed in the organic interposer is set to be not greater than the average delay.Type: GrantFiled: November 14, 2017Date of Patent: July 17, 2018Assignee: Renesas Electronics CorporationInventors: Ryuichi Oikawa, Wataru Shiroi
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Patent number: 10020059Abstract: A memory device includes an electrical line operably coupled to a plurality of memory cells, and a switchable impedance driver operably coupled to the electrical line. An electronic circuit includes a first driver having a first output impedance, and a second driver having a second output impedance that is less than the first output impedance. The first driver and the second driver are operably coupled in parallel to an output of the electronic circuit. The electronic circuit includes logic circuitry to enable the second driver during switching of a digital output of the driver. A method includes driving an output with both the first driver and the second driver when an input switches between logic levels, and disabling the second driver when the output reaches a desired logic level following the switch between logic levels of the input.Type: GrantFiled: April 12, 2017Date of Patent: July 10, 2018Assignee: SanDisk Technologies LLCInventors: Muralikrishna Balaga, Vinayak Ghatawade, Aditya Pradhan
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Patent number: 10014860Abstract: Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.Type: GrantFiled: June 21, 2017Date of Patent: July 3, 2018Assignee: Rambus Inc.Inventor: Ian Shaeffer
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Patent number: 9978460Abstract: A memory module includes a first memory device including a first one-die termination circuit for impedance matching of a signal path and a second memory device sharing the signal path with the first memory device and including a second on-die termination circuit for impedance matching of the signal path, wherein the signal path corresponds to a command or address signal path provided from a host, and the first and second on-die termination circuits are individually controlled according to control of the host.Type: GrantFiled: December 20, 2016Date of Patent: May 22, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sukyong Kang, Hangi Jung, Hun-Dae Choi
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Patent number: 9935632Abstract: A semiconductor device includes a power management integrated circuit that supplies a periodic supply voltage signal. The semiconductor device also includes programmable termination components and a calibration circuit. The calibration circuit generates impedance calibration codes associated with a period of the periodic supply voltage signal. The calibration circuit also calibrates impedance of the programmable termination components based on an average impedance calibration code of the impedance calibration codes. The semiconductor device further includes an averaging circuit that determines the average impedance calibration code of the impedance calibration codes.Type: GrantFiled: July 19, 2017Date of Patent: April 3, 2018Assignee: Micron Technology, Inc.Inventor: Dean D. Gans
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Patent number: 9935606Abstract: A system on chip (SoC) and a correction method of termination impedance element thereof are provided. The SoC includes a pad, a first termination impedance element, and a correction circuit. The pad is coupled to an external dynamic random access memory (DRAM) chip, where the DRAM chip includes a corrected termination impedance element. The first termination impedance element is coupled to the pad. The correction circuit is coupled to a control terminal of the first termination impedance element, to control an impedance value of the first termination impedance element. During an initialization period, the correction circuit corrects the impedance value of the first termination impedance element by using the impedance value of the corrected termination impedance element.Type: GrantFiled: December 8, 2016Date of Patent: April 3, 2018Assignee: ALi CorporationInventor: Yu-Hsiang Lin
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Patent number: 9935626Abstract: A driver for a power field-effect transistor includes a first and second circuits that apply respective charge currents to a gate of the power field-effect transistor when a control signal has a first logic value and the voltage between the gate and the source is smaller than a first threshold voltage and greater than a second threshold voltage. Third and fourth circuits apply respective discharge currents to the gate when the control signal has a second logic value and the voltage between the gate and the source is greater than a third threshold voltage and smaller than a fourth threshold voltage. The driver may include at least one field-effect transistor configured to generate at least one of the first, second, third or fourth threshold voltage.Type: GrantFiled: June 28, 2016Date of Patent: April 3, 2018Assignee: STMicroelectronics S.r.l.Inventor: Aldo Davide Gariboldi
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Patent number: 9928194Abstract: Described embodiments provide a transmitter for transmitting data over a serial bus coupled to the transmitter. The transmitter includes a controller to generate data for transmission by the transmitter. A transmit driver is coupled to the controller. The transmit driver, in response to the generated data for transmission, generates logic transitions on the serial bus. The transmit driver generates low-to-high logic transitions on the serial bus by charging the serial bus by a bus current based on (i) a predetermined initial bias level for a first time period, and (ii) a first predetermined maximum bias level for a second time period. The transmit driver generates high-to-low logic transitions on the serial bus by discharging the serial bus by a bus current based on (i) a pre-charged level of the transmit driver, and (ii) a second predetermined maximum bias level for a third time period.Type: GrantFiled: November 30, 2015Date of Patent: March 27, 2018Assignee: Allegro Microsystems, LLCInventors: Thomas Ross, Aldo Togneri, James McIntosh, Gianluca Allegrini
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Patent number: 9871520Abstract: The disclosed voting circuit includes a pull-up circuit connected to an output node and to a positive supply voltage. A pull-down circuit is connected to the output node and to ground, and the output node is coupled to receive true output of a first bi-stable circuit. The pull-up circuit pulls the output node to the positive supply voltage in response to complementary output signals from second and third bi-stable circuits being in a first state, and the pull-down circuit pulls the output node to ground in response to complementary output signals from second and third bi-stable circuits being in a second state that is opposite the first state.Type: GrantFiled: August 15, 2016Date of Patent: January 16, 2018Assignee: XILINX, INC.Inventors: Chi M. Nguyen, Robert I. Fu
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Patent number: 9871518Abstract: A memory interface circuit includes a first variable impedance circuit coupled between a first supply voltage and a pad, and a second variable impedance circuit coupled between a second supply voltage and the pad; wherein when the first supply voltage changes, at least one of the first variable impedance circuit and the second variable impedance circuit is controlled to have different setting in response to the changing of the first supply voltage.Type: GrantFiled: August 25, 2016Date of Patent: January 16, 2018Assignee: MEDIATEK INC.Inventors: Shang-Pin Chen, Chia-Yu Chan, Bo-Wei Hsieh
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Patent number: 9793708Abstract: Overvoltage protection circuits include a combination of an overvoltage detection circuit and a voltage clamping circuit that inhibits sustained overvoltage conditions. An overvoltage detection circuit can include first and second terminals electrically coupled to first and second power supply signal lines, respectively. This overvoltage detection circuit may be configured to generate a clamp activation signal (CAS) in response to detecting an excessive overvoltage between the first and second power supply signal lines. This CAS is provided to an input of the voltage clamping circuit, which is electrically coupled to the first power supply signal line and configured to sink current from the first power supply signal line in response to the CAS. The voltage clamping circuit may be configured to turn on and sink current from the first power supply signal line in-sync with a transition of the CAS from a first logic state to a second logic state.Type: GrantFiled: December 19, 2014Date of Patent: October 17, 2017Assignee: Integrated Device Technology, Inc.Inventors: Alan Wolfram Glaser, Tak Kwong Wong, Al Fang, Roland Thomas Knaack, Jon Roderick Williamson
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Patent number: 9716497Abstract: A calibration circuit sharing a resistor for impedance matching includes a command decoder configured to receive a command signal and decode the command signal into a calibration enable signal; a selector configured to select one of the calibration enable signal and a start signal according to a select signal, and provide a driving signal; and a calibration driver configured to perform an impedance matching operation in response to the driving signal, and generate a completion signal when performance is completed, wherein the start signal corresponds to a completion signal provided from another calibration circuit which shares the resistor for the impedance matching.Type: GrantFiled: March 18, 2015Date of Patent: July 25, 2017Assignee: SK hynix Inc.Inventors: Oung Sic Cho, Jong Hoon Oh
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Patent number: 9684321Abstract: An integrated circuit includes a voltage regulator to supply a regulated voltage and a data output that couples to an unterminated transmission line. The circuit draws a variable amount of power from the voltage regulator according to the data. The voltage regulator includes a first current generation circuit to provide a data transition-dependent current.Type: GrantFiled: April 29, 2015Date of Patent: June 20, 2017Assignee: Rambus Inc.Inventors: Brian S. Leibowitz, Michael D. Bucher, Lei Luo, Chaofeng Charlie Huang, Amir Amirkhany, Huy M. Nguyen, Hsuan-Jung (Bruce) Su, John Wilson
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Patent number: 9641175Abstract: To decrease the circuit scale necessary for the calibration of the output circuit and to decrease the time required for the calibration operation. The invention includes a first output buffer and a second output buffer that are connected to a data pin, and a calibration circuit that is connected to a calibration pin. The first output buffer and the second output buffer include plural unit buffers. The unit buffers have mutually the same circuit structures. With this arrangement, the impedances of the first output buffer and the second output buffer can be set in common, based on the calibration operation using the calibration circuit. Consequently, both the circuit scale necessary for the calibration operation and the time required for the calibration operation can be decreased.Type: GrantFiled: June 9, 2016Date of Patent: May 2, 2017Assignee: Longitude Semiconductor S.a.r.l.Inventor: Hiroki Fujisawa
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Patent number: 9620497Abstract: An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad.Type: GrantFiled: August 17, 2015Date of Patent: April 11, 2017Assignee: International Business Machines CorporationInventors: James P. Di Sarro, Robert J. Gauthier, Jr., Nathan D. Jack, JunJun Li, Souvick Mitra
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Patent number: 9614497Abstract: An impedance adjustment circuit includes a counter circuit outputting a count value thereof as a plurality of first impedance adjustment signals, a mode selection circuit setting a second impedance adjustment signal to be in an active/inactive state irrespective of the count value, and a level fixing circuit fixing a third impedance adjustment signal to be in an active state. A pre-stage circuit generates a plurality of first output control signals, a second output control signal, and a third output control signal in response to the first impedance adjustment signals, the second impedance adjustment signal, and the third impedance adjustment signal, respectively, and a data signal. An output circuit includes a plurality of first transistors, a second transistor, and a third transistor connected in parallel to each other between an output terminal and a first power supply wiring.Type: GrantFiled: February 16, 2016Date of Patent: April 4, 2017Assignee: Micron Technology, Inc.Inventors: Yuhei Kaneko, Kohei Nakamura
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Patent number: 9601163Abstract: A memory module is provided which includes a printed circuit board; first semiconductor packages provided on one surface of the printed circuit board; and second semiconductor packages provided on the other surface of the printed circuit board, the first semiconductor packages and the second semiconductor packages having semiconductor dies that form ranks. A number of the ranks formed by the first semiconductor packages being different from a number of the ranks formed by the second semiconductor packages. Semiconductor packages forming a same one of the ranks receive a chip selection signal in common and semiconductor packages forming other ranks receive a different chip selection signal.Type: GrantFiled: May 31, 2016Date of Patent: March 21, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Hyung Song, Kyoungsun Kim, Yong-Jin Kim, Jaejun Lee, Sangseok Kang, Jungjoon Lee
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Patent number: 9571098Abstract: A receiving circuit includes a termination resistance circuit and a resistance adjustment circuit. The termination resistance circuit is configured to receive a first differential signal via a first input terminal and a second differential signal via a second input terminal, and to be selectively connected to the first and second input terminals. The termination resistance circuit has an adjustable resistance value. The resistance adjustment circuit is configured to decrease the resistance value of the termination resistance circuit in response to a signal reception preparation command and connection of the termination resistance circuit to the first and second input terminals.Type: GrantFiled: August 10, 2015Date of Patent: February 14, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Ha Kim, Hwaseok Oh
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Patent number: 9548654Abstract: Temperature, process and supply compensated delay circuits, DC to DC converters and integrated circuits are presented in which switch driver dead time delays are provided using a plurality of cascaded CMOS inverter circuits with a first inverter coupled through a diode-connected MOS transistor to a regulated voltage or circuit ground and a MOS capacitor is provided between the first inverter output and the regulated voltage or circuit ground to provide a controlled delay time. A second cascaded CMOS inverter is powered by a compensated voltage which decreases with temperature to operate as a comparator, and certain embodiments include one or more intermediate CMOS inverters to form a level shifting circuit between the second inverter and the final output inverter, with the level shift inverters powered by successively higher compensated voltages that decrease with increasing temperature.Type: GrantFiled: March 2, 2015Date of Patent: January 17, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jun Yi, Xuechun Ou
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Patent number: 9531291Abstract: Described embodiments provide a transmission-line resistance compression network that includes an input port, a first output port coupled to a first load and a second output port coupled to a second load. The first and second loads may have substantially similar input impedances under substantially similar operating conditions. The transmission-line resistance compression network includes a transmission-line network coupled to the input port, the first output port and the second output port, and includes at least two transmission lines of different lengths. For a first operating range, the resistances at input ports of the first and second loads vary over first and second ratios, respectively. The resistance of the input impedance at the input port of the transmission-line resistance compression network varies over a third ratio that is smaller than at least one of the first and second ratios.Type: GrantFiled: April 17, 2014Date of Patent: December 27, 2016Assignee: Eta Devices, Inc.Inventor: David J. Perreault
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Patent number: 9485854Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for electrical signal absorption in an interconnect disposed in a printed circuit board (PCB) assembly. In one instance, a PCB assembly may comprise a substrate, and an interconnect formed in the substrate to route an electrical signal within the PCB. The interconnect may be coupled with a connecting component that is disposed on a surface of the PCB. An absorbing material may be disposed on the PCB to be in direct contact with at least a portion of the connecting component to at least partially absorb a portion of the electrical signal. Other embodiments may be described and/or claimed.Type: GrantFiled: August 20, 2014Date of Patent: November 1, 2016Assignee: Intel CorporationInventors: Shaowu Huang, Kai Xiao, Beom-Taek Lee, Boping Wu, Xiaoning Ye
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Patent number: 9432018Abstract: A storage controller includes a first on-die termination (ODT) circuit, a second ODT circuit and an ODT control circuit. The first ODT circuit provides a first termination resistance with a strobe signal line transferring a data strobe signal. The second ODT circuit provides a second termination resistance with at least one data line transferring data. The ODT control circuit individually controls activation and deactivation of the first ODT circuit and the second ODT circuit.Type: GrantFiled: July 23, 2015Date of Patent: August 30, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Kwang-Soo Park, Su-Jin Kim, Jung-Hee Cho
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Patent number: 9407263Abstract: A driver circuit having an adjustable output signal includes a logic circuit configured to receive an input signal into a first input terminal and an output circuit coupled to the logic circuit, wherein the output circuit is configured to generate, at an output terminal of the output circuit, an output signal having a signal level that changes in response to a signal level of the input signal. The driver circuit further includes a feedback circuit coupled to a second input terminal of the logic circuit. The feedback circuit includes first and second gate terminals coupled to the output terminal and a third gate terminal coupled to a control signal supply, wherein the feedback circuit is configured to control a maximum level of the output signal from the driver circuit based on an operating threshold of the feedback circuit as set by a control signal generated by the control signal supply.Type: GrantFiled: October 31, 2012Date of Patent: August 2, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Alexander B. Hoefler, Hector Sanchez
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Patent number: 9385722Abstract: Embodiments include apparatuses, methods, and systems for voltage level shifting a data signal between a low voltage domain and a high voltage domain. In embodiments, a voltage level shifter circuit may include adaptive keeper circuitry, enhanced interruptible supply circuitry, and/or capacitive boosting circuitry to reduce a minimum voltage of the low voltage domain that is supported by the voltage level shifter circuit. Other embodiments may be described and claimed.Type: GrantFiled: November 25, 2014Date of Patent: July 5, 2016Assignee: Intel CorporationInventors: Amit R. Trivedi, Jaydeep P. Kulkarni, Carlos Tokunaga, Muhammad M. Khellah, James W. Tschanz
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Patent number: 9361843Abstract: The present invention discloses an input buffer circuit capable of recognizing and driving a low-voltage signal, output from a low-voltage environment, in a high-voltage environment and a gate driver IC including the input buffer circuit. The input buffer circuit is configured to include two or more multi-stage inverters and to recognize and output a gate signal having a different voltage domain from an operating voltage. Accordingly, a signal interface environment between chips operating in different voltage domains can be provided.Type: GrantFiled: September 27, 2013Date of Patent: June 7, 2016Assignee: SILICON WORKS CO., LTD.Inventors: Young Keun Ko, An Young Kim
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Patent number: 9343165Abstract: A system for optimizing drive strength may be utilized for identifying the maximum data transfer rate for different devices and different device configurations. The drive strength may be optimized for input/output (I/O) devices by measuring voltage drops on I/O power supply using different test patterns. The maximum drive strength is identified that satisfies a limit or threshold for the allowed voltage drop level. The test pattern may include a simultaneous toggling of each I/O device. A slew rate for the device may be utilized along with the drive strength for identifying the maximum data transfer rate.Type: GrantFiled: February 27, 2013Date of Patent: May 17, 2016Assignee: SanDisk Technologies Inc.Inventors: Dmitry Vaysman, Arkady Katz
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Patent number: 9318420Abstract: A stack package including a first semiconductor chip and second semiconductor chip, the first semiconductor chip including first data I/O pads for transmitting data I/O signals, a first flag pad for receiving a flag signal, and a first buffer for controlling a switching operation between the first data I/O pads and an internal circuit of the first semiconductor chip. The second semiconductor chip includes second data I/O pads for transmitting the data I/O signals, a second flag pad for receiving the flag signal, and a second buffer for controlling a switching operation between the second data I/O pads and an internal circuit of the second semiconductor chip. The first data I/O pads are electrically connected to respective ones of the second data I/O pads through first wires, and the first flag pad is electrically connected to the second flag pad through a second wire. Related methods are also provided.Type: GrantFiled: December 18, 2012Date of Patent: April 19, 2016Assignee: SK HYNIX INC.Inventor: Moon Soo Kim
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Patent number: 9214942Abstract: A complementary push-pull buffer includes complementary transconductance (GM) devices connected as source-followers to drive a load. Current flowing through the GM devices is split, on the source side, between constant-current source circuitry and a push signal current multiplier (e.g., a current mirror) and, on the sink side, between constant-current sink circuitry and a pull signal current multiplier. The devices used to implement the constant-current circuits and the current multipliers are sized such that the current multipliers provide low output impedance, while the current splitting provides low overall power consumption.Type: GrantFiled: February 17, 2014Date of Patent: December 15, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventor: Nishant Singh Thakur
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Patent number: 9148130Abstract: A system and method are provided for boosting a selective portion of a drive signal for chip-to-chip transmission across an interconnection interface. The system includes a driver unit generating a drive signal responsive to an input data signal. The drive signal is provided on to at least one output node for transmission through the device interconnection interface, and defines a peak amplitude during a drive period. A boosting unit is coupled to the driver unit for selectively boosting a portion of the drive signal. The boosting unit actuates responsive to the input data signal to selectively apply a boost signal in self-timed manner to the drive signal, so as to thereby augment the drive signal in amplitude over a selected portion of the drive period thereof. In this manner, the boosting unit maintains the peak amplitude of the drive signal at or above a predetermined level throughout the drive period.Type: GrantFiled: May 10, 2012Date of Patent: September 29, 2015Assignee: Cadence Design Systems, Inc.Inventors: Eric Naviasky, Ali Ulas Ilhan
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Patent number: 9064059Abstract: Provided is a controller for a solid state disk, to control simultaneous switching of pads. The controller for the solid state disk may control simultaneous switching of a plurality of output pads or a plurality of input pads that correspond to a plurality of channels. In particular, the controller may properly delay signals driven to the output pads or input pads, to reduce power supplied to the pads, and to prevent ground bouncing, as well as, maintain a quality of signals.Type: GrantFiled: November 3, 2009Date of Patent: June 23, 2015Assignee: OCZ Storage Solutions Inc.Inventor: Young-Goan Kim
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Patent number: 9030229Abstract: An impedance tuning circuit includes a calibration unit and a post-processing unit. The calibration unit generates an initial pull-up code and an initial pull-down code by performing a calibration operation using an external resistor during an initial impedance tuning operation. The post-processing unit outputs the initial pull-up code and the initial pull-down code as a final pull-up code and a final pull-down code during the initial impedance tuning operation, and generates the final pull-up code and the final pull-down code by using the initial pull-up code and the initial pull-down code during a subsequent impedance tuning operation.Type: GrantFiled: October 25, 2012Date of Patent: May 12, 2015Assignee: Samsung Electronics Co., Ltd.Inventor: Kyung Hoi Koo
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Patent number: 9024659Abstract: A device for passive equalization and slew-rate control of a signal includes a first branch and a second branch. The first branch includes a first driver coupled in series with an equalization capacitor. The second branch includes a second driver coupled in series with a resistor. The second branch may be coupled in parallel to the first branch. The first branch may be configurable to enable either passive equalization or slew-rate control of the signal based on a mode control signal.Type: GrantFiled: November 5, 2013Date of Patent: May 5, 2015Assignee: Broadcom CorporationInventors: Tamer Ali, Hassan Maarefi, Mahmoud Reza Ahmadi, Afshin Momtaz
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Patent number: 9018974Abstract: An impedance calibration device includes: a variable impedance, an operational unit, an analog-digital converter, and a controller. The operational unit receives a first analog signal and a second analog signal, and performs a difference operation to generate an output voltage. The analog-digital converter generates an adjustment code according to the output voltage. The controller is coupled to the analog-digital converter and the variable impedance, and adjusts a resistance value of the variable impedance according to the adjustment code.Type: GrantFiled: February 11, 2013Date of Patent: April 28, 2015Assignee: Realtek Semiconductor Corp.Inventors: Che-Wei Chang, Cheng-Pang Chan, Jian-Ru Lin
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Patent number: 9000800Abstract: A system for calibrating impedance of an input/output (I/O) buffer on a semiconductor die includes: the I/O buffer; a temperature sensor on the semiconductor die; and a supply sensor on the semiconductor die. The temperature sensor is configured to acquire temperature information for calibrating the I/O buffer. The supply sensor is configured to acquire voltage information for calibrating the I/O buffer. The I/O buffer comprises: a memory component coupled to the temperature and supply sensors and configured to store the acquired temperature or voltage information; a logic component coupled to the memory component; and a driver with driver legs. The driver is coupled to the logic component. The logic component is configured to generate driver control signals representing an on/off configuration for the driver legs of the driver based at least in part on the acquired temperature information or the acquired voltage information stored in the memory component.Type: GrantFiled: September 17, 2012Date of Patent: April 7, 2015Assignee: Xilinx, Inc.Inventors: Ionut C. Cical, Edward Cullen, Ivan Bogue
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Patent number: 8994398Abstract: A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level.Type: GrantFiled: June 7, 2013Date of Patent: March 31, 2015Assignee: Rambus Inc.Inventors: Vladimir M. Stojanovic, Andrew C. Ho, Anthony Bessios, Fred F. Chen, Elad Alon, Mark A. Horowitz
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Patent number: 8975920Abstract: A multi-function programmable transceiver is described. The transceiver includes a driver circuit and a receiver circuit, which allows an Application Specific Integrated Circuit (ASIC) device to drive and receive data from other ASIC devices. Both the driver and receiver circuits share a common input/output (I/O) pin. The driver circuit can be programmed to provide one of the several driver functions, such as CMOS, TTL, PCI, HSTL, SSTL and LVDS. Other functional features of the transceiver that can be programmed are driving strengths or output impedance, output power supply voltage, single ended or differential mode of HSTL/SSTL transceivers, and class 1 or class 2 operations for SSTL/HSTL transceivers. The receiver circuit can also be programmed to provide one of the several receiver functions, such as CMOS, TTL, PCI, HSTL, SSTL and LVDS.Type: GrantFiled: August 13, 2012Date of Patent: March 10, 2015Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventor: Jai P. Bansal
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Patent number: 8970248Abstract: A termination network for a receiver device is provided to support both D-PHY signaling and N-factorial signaling. The first end of each of a plurality dynamically configurable switches is coupled to a common node. A first end of each of a plurality of resistances is coupled to a second end of a corresponding switch. A plurality of terminals receive differential signals and each terminal is coupled to a corresponding second end of a resistance. Each of a plurality differential receivers is coupled between two terminals of the termination network, wherein a first differential receiver and a second differential receiver are coupled to the same two terminals, the first differential receiver is used when the differential signals use a first type of differential signal encoding, the second differential receiver is used when the differential signals use a second type of differential signal encoding.Type: GrantFiled: March 13, 2014Date of Patent: March 3, 2015Assignee: QUALCOMM IncorporatedInventors: Shoichiro Sengoku, George Alan Wiley, Chulkyu Lee, Joseph Cheung
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Patent number: 8963578Abstract: The present invention discloses a receiver capable of enhancing accuracy of signal reception. The receiver includes a variable termination resistance unit, coupled to at least one channel, for utilizing at least one termination resistance corresponding to the at least one channel to perform impedance matching, and a signal detection and termination resistance adjustment unit, for detecting at least one external calibration signal corresponding to the at least one channel from at least one external signal generator, and adjusting the at least one termination resistance.Type: GrantFiled: July 23, 2013Date of Patent: February 24, 2015Assignee: NOVATEK Microelectronics Corp.Inventor: Tse-Hung Wu
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Patent number: 8963576Abstract: A switching device driver, which includes switching circuitry and a first capacitive element, which is coupled to the switching circuitry, is disclosed. The switching circuitry receives a logic level input signal and provides a switching control output signal to a switching device based on the logic level input signal. When the logic level input signal has a first logic level, the switching circuitry charges the first capacitive element. When the logic level input signal transitions from the first logic level to a second logic level, the switching circuitry at least partially discharges the first capacitive element to rapidly transition the switching control output signal, thereby causing the switching device to quickly change states.Type: GrantFiled: October 19, 2012Date of Patent: February 24, 2015Assignee: Cree, Inc.Inventor: Robert J. Callanan
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Patent number: 8941411Abstract: A signal transmission circ it includes a main driving unit configured to drive a first signal transmission One in response to an input signal and output a first driven signal, an emphasis driving unit configured to perform an emphasis operation on the first driven signal and output an emphasized signal, and a crosstalk control unit configured to perform an equalizing operation on the emphasized signal.Type: GrantFiled: March 15, 2013Date of Patent: January 27, 2015Assignees: SK Hynix Inc., Industry-University Cooperation Foundation Hanyang UniversityInventors: Chun-Seok Jeong, Young-Hoon Kim, Chang-Sik Yoo
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Patent number: 8941406Abstract: Provided is a method for reducing output data noise of a semiconductor apparatus which includes a plurality of output buffers to output data. The method includes the steps of: driving low data to a specific output buffer among the plurality of output buffers, and driving data transiting from a high level to a low level to the other output buffers; and measuring the magnitude of data noise occurring in output data of the specific output buffer, and deciding slew rates of the plurality of output buffers based on the measurement result.Type: GrantFiled: December 19, 2012Date of Patent: January 27, 2015Assignee: SK Hynix Inc.Inventors: Sung Woo Han, Ic Su Oh, Jun Ho Lee, Boo Ho Jung, Sun Ki Cho, Yang Hee Kim, Tae Hoon Kim
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Patent number: 8912818Abstract: A calibration circuit includes an amplifier, a current steering digital-to-analog converter (DAC), a comparator, a slew calibration network, and an on-die termination (ODT) network. The amplifier generally has a first input, a second input, and an output. The first input generally receives a reference signal. The current steering digital-to-analog converter (DAC) generally has a first input coupled to the output of the amplifier, a first output coupled to the second input of the amplifier, and a second output coupled to a circuit node. The comparator generally has a first input receiving the reference signal, a second input coupled to the circuit node, and an output at which an output of the calibration circuit may be presented. The slew calibration network is generally coupled to the circuit node and configured to adjust a slew rate of the calibration circuit. The on-die termination (ODT) network is generally coupled to the circuit node.Type: GrantFiled: October 30, 2012Date of Patent: December 16, 2014Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Dharmesh Bhakta, Hong-Him Lim, Cheng-Gang Kong, Todd Randazzo
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Patent number: 8901955Abstract: This disclosure provides examples of circuits, devices, systems, and methods for providing high speed operation with high noise immunity. In one implementation, a circuit includes a first buffer configured to receive an incoming signal and to generate a first output signal. The circuit also includes a second buffer configured to receive the incoming signal and to generate a second output signal. The second buffer exhibits hysteresis with lower and upper thresholds. The circuit also includes an output block configured to receive the first and second output signals and to generate a third output signal. The output block is configured to switch a logic state of the third output signal in response to a transition of a logic state of the first output signal, and to lock the logic state of the third output signal until the output block receives a transition of a logic state of the second output signal.Type: GrantFiled: November 5, 2012Date of Patent: December 2, 2014Assignee: SanDisk Technologies Inc.Inventor: Ekram H. Bhuiyan
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Patent number: 8896347Abstract: A synchronous digital signal capture system includes a first flip-flop and a synchronization module. The first flip-flop receives a logic control signal and a first clock signal having a first frequency. The first flip-flop is configured to output a synchronized data signal based on the logic control, and generate a synchronous reset signal that is a logic inverse of the synchronized data signal generated at the data output. The synchronization module receives a primary data signal and is configured to generate the logic control signal based on the primary input signal, a second clock signal, and the synchronous reset signal such that the first flip-flop generates the synchronized signal.Type: GrantFiled: March 29, 2013Date of Patent: November 25, 2014Assignee: Hamilton Sundstrand CorporationInventor: David S. Harman
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Patent number: 8896342Abstract: An integrated circuit of a multiple die package structure having a plurality of semiconductor devices, each of the plurality of semiconductor devices may include an active termination circuit configured to perform an active termination operation to the semiconductor device, and to be turned off in a disable state of an active termination setting code, a multiple die package information transfer unit configured to transfer a multiple die package information signal, and a compulsory termination unit configured to selectively convert the active termination setting code into the disable state in response to the multiple die package information signal.Type: GrantFiled: March 15, 2013Date of Patent: November 25, 2014Assignee: SK Hynix Inc.Inventor: Jong-Ho Jung
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Patent number: 8878568Abstract: A high speed transmit driver is provided, along with methods to improve driver slew rate, decrease transmit jitter, improve termination accuracy, and decrease sensitivity to supply noise.Type: GrantFiled: October 24, 2012Date of Patent: November 4, 2014Assignee: Semtech CorporationInventors: Kamran Farzan, Mehrdad Ramezani, David Cassan, Angus McLaren, Saman Sadr
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Patent number: 8878565Abstract: Disclosed herein is a semiconductor device that includes a first transistor unit coupled to the data terminal, and a plurality of second transistor units coupled to the calibration terminal. The first transistor unit includes a plurality of first transistors having a first conductivity type connected in parallel to each other so that an impedance of the first transistor unit is adjustable. Each of the second transistor units includes a plurality of second transistors having the first conductivity type connected in parallel to each other so that an impedance of each of the second transistor units is adjustable. The semiconductor device further includes an impedance control circuit that reflects the impedance of each of the second transistor units to the first transistor unit.Type: GrantFiled: October 5, 2012Date of Patent: November 4, 2014Assignee: PS4 Luxco S.A.R.LInventor: Kentaro Hara
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Patent number: 8860470Abstract: Input/output (I/O) line driving circuits are provided. The circuit includes a first I/O line driver and a second I/O line driver. The first I/O line driver receives a first input signal in response to an enable signal to generate a first control signal and drives a first I/O line in response to a second control signal. The second I/O line driver receives a second input signal in response to the enable signal to generate the second control signal and drives a second I/O line in response to the first control signal.Type: GrantFiled: October 15, 2013Date of Patent: October 14, 2014Assignee: SK Hynix Inc.Inventor: Nak Kyu Park
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Patent number: 8803550Abstract: This disclosure provides examples of circuits, devices, systems, and methods for providing high speed operation and a high noise margin. In one implementation, a circuit includes a first buffer configured to receive an incoming signal and a control signal and to generate an output signal based on the incoming signal. The first buffer exhibits a first hysteresis range while configured in a first hysteresis state and a second hysteresis range while configured in a second hysteresis state. The first buffer is configured to transition from the first to the second hysteresis state and vice versa in response to the control signal. The circuit includes a second buffer configured to receive the incoming signal and to generate the control signal based on the incoming signal. The second buffer exhibits a third hysteresis range with a lower threshold and an upper threshold.Type: GrantFiled: December 12, 2012Date of Patent: August 12, 2014Assignee: SanDisk Technologies Inc.Inventor: Ekram H. Bhuiyan
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Patent number: 8798206Abstract: A digital input interface is provided which can be checked for its reliability. The configuration of the circuit on the input side allows a high impedance for a DC input signal and a low impedance for induced AC noise, naturally attenuating any AC induced noise while maintaining the DC input signal. The interface also provides a latent failure detection engine. The latent failure detection engine can open and close an optocoupler on the input side of the interface, which discharges and charges a capacitor on the input side. The time taken for the capacitor to recharge when the optocoupler is re-opened is used to determine if there has been any threshold decay in the interface.Type: GrantFiled: January 11, 2012Date of Patent: August 5, 2014Assignee: Thales Canada Inc.Inventors: Gabriel Cristian Ilie, Virgil Lostun, Daniel Sandu, Ovidiu Stan