Abstract: A method and circuit for pre-emphasis equalization of a high speed data communication system can be provided through the use of programmable pulse shaping. A data communication system configured with the pre-emphasis equalization circuit operates by receiving an input data stream and outputting a data stream for transmission through an interconnect or other transmission channel. The data can be passed through an output buffer configured with programmable pre-emphasis equalization, having input inverters at an input stage and output inverters at an output stage. During operation, once an input signal to the input stage transitions, for example from a low to a high state, an input signal to the output stage is configured to a full amplitude to drive the transmission channel. Once the output stage transitions to a full amplitude, the input of the output stage is configured closer to a mid-scale amplitude.

Abstract: A scan flip-flop circuit achieving higher operation speed, lower power consumption, and a simplified selector section, an array of the scan flip-flop circuits, and an integrated circuit device having therein the array are provided. In a scan flip-flop circuit, an output terminal is provided in addition to an output terminal. One of the output terminals is used for a logic circuit and the other output terminal is used for a scan flip-flop circuit of the next stage. At the output terminal for the scan flip-flop circuit 1 of the next stage, an output is fixed in a normal operation, thereby achieving higher operation speed in the normal operation and lower power consumption. A selector section can employ a relatively simple OR-AND-INVERTER structure.

Abstract: According to some embodiments, provided are a first signal line, the first signal line coupled to a first repeater, the first repeater to convert a first signal from a received signal level to an output signal level, the first repeater to convert from a first signal level to a second signal level slower than from the second signal level to the first signal level, and a second signal line adjacent to the first signal line, the second signal line coupled to a second repeater adjacent to the first repeater, the second repeater to convert a second signal from a second received signal level to a second output signal level, the second repeater to convert from the first signal level to the second signal level slower than from the second signal level to the first signal level, wherein the received signal level is substantially equivalent to the second output signal level and wherein the second received signal level is substantially equivalent to the output signal level.

Abstract: A negative impedance device that accelerates signal transitions on a signal is provided. The negative impedance device is highly responsive to high to low and low to high transitions on the signal, and when one of these types of transitions begins to occur on the signal, the negative impedance device senses the transition and quickly drives the signal to the intended value before a point in time when the signal would have reached the intended value had the negative impedance device not been used. Further, a signal transition accelerator design that reduces signal rise and fall times is provided. Further, a method for accelerating a signal transition is provided.

Abstract: The open-drain type output buffer includes a first driver and at least one of (1) at least one secondary driver and (2) at least one tertiary driver. The first driver selectively pulls an output node towards a low voltage based on input data. The secondary and tertiary drivers have first and second states. Each secondary and tertiary driver pulls the output node towards the low voltage when in the first state, and pulls the output node towards the low voltage in the second state. A control circuit, when a secondary driver is included, controls the secondary driver such that the secondary driver is in the second state when it has been determined that at least two consecutive low voltage output data have been generated. The control circuit, when a tertiary driver is included, controls the tertiary driver such that the tertiary driver is in the first state when a transition from a steady high voltage output data to a low voltage output data is determined.

Abstract: This invention provide a new and improved output circuit of a semiconductor integrated circuit device that enables output of a slew-rate waveform with a desired gradient without generating unwanted delay and also enables reduction in switching noise. According to this invention, an output circuit of a semiconductor integrated circuit device for controlling the gradient of an output waveform of a CMOS output transistor using first and second variable resistance units (transfer gates) controlled by a signal of an input part has another CMOS output circuit for delaying rise of a gate by dividing an output part and connecting first and second resistance units (NMOS transistor and PMOS transistor) to the gates.

Abstract: A data-sampling strobe signal generator and an input buffer using the same. The data-sampling strobe signal includes a intermediate signal generator, a comparison circuit and a logic circuit. The intermediate signal generator compares non-inverting/inverting strobe signals and generates an intermediate signal based on the comparison result. The comparison circuit compares a reference voltage with the non-inverting strobe signal and the inverting strobe signal, respectively, and outputs a control signal. The control signal is enabled when one of the non-inverted/inverting strobe signals is higher than the reference voltage and the other is lower than the reference voltage, and disabled when the non-inverting/inverting strobe signals are the same logical level. The logic circuit receives the intermediate signal and the control signal and generates the data-sampling strobe signal from the intermediate signal when the control signal is enabled.

Abstract: A semiconductor integrated circuit device comprises a plurality of MIS transistors, and an integrated circuit unit including logic gate circuits configured by a combination of the plurality of MIS transistors. Each of the MIS transistors has a gate including a circuit element represented by an equivalent circuit in which a capacitance and resistance are parallel-connected.

Abstract: A system for controlling the duty cycle of a clock signal. The system includes a duty cycle adjustment circuit that receives an input clock signal and generates an output clock signal. The duty cycle adjustment circuit charges a capacitor when the input clock signal has a first logic level and discharges the capacitor with the input clock signal has a second logic level. The rates of charge and discharge are controlled by first and second control signals. When the capacitor has been charged to a first transition level, the output clock signal transitions to a first logic level, and when the capacitor has been discharged to a second transition level, the output clock signal transitions to a second logic level. The first and second control signals are supplied by a feedback circuit, which is implemented using an integrator circuit that receives the output clock signal and generates a feedback signal indicative of the duty cycle of the output clock signal.

Abstract: A clock controller and clock generating method are provided for AC self-test timing analysis of a logic system. The controller includes latch circuitry which receives a DC input signal at a data input, and a pair of continuous out-of-phase clock signals at capture and launch clock inputs thereof. The latch circuitry outputs two overlapping pulses responsive to the DC input signal going high. The two overlapping pulses are provided to waveform shaper circuitry which produces therefrom two non-overlapping pulses at clock speed of the logic system to be tested. The two non-overlapping pulses are a single pair of clock pulses which facilitate AC self-test timing analysis of the logic system.

Abstract: A method of enhancing noise margin on digital signal lines of a system includes steps of evaluating impedances and lengths of the digital signal lines. Resonances of each digital signal line are determined, and target waveforms for each digital signal line optimized for noise margin are determined. A configuration is generated for a programmable device driver to configure the device driver to generate the waveform optimized for noise margin. An alternative embodiment selects waveforms, and corresponding configurations, from a group of possible waveforms at boot time to ensure that data is transferred with optimum noise margins. Also claimed is apparatus embodying bus drivers capable of driving a bus with a waveform approximating blended trapezoidal and sinusoidal edge shapes, this waveform being optimum for noise margin in certain systems having multidrop busses.

Abstract: Adjusting a clock duty cycle. An incremental error signal is generated in response to the clock signal. A cumulative error signal is generated in response to the incremental error signal. The incremental error signal is reset and the duty cycle of the clock signal is adjusted in response to the cumulative error signal.

Abstract: The invention relates to a semiconductor module having a plurality of signal paths for carrying external signals that each contain a setup and hold circuit on the basis of a latch circuit with a full latch and a logic circuit. The latch circuit contains at a beginning of the signal path upstream of the logic circuit a hold latch. The hold latch responds to the leading edge of a fast clock signal derived from the clock signal of the external signal, for the early latching of the external signal and for the decoupling of the hold time from the setup time. The full latch is disposed downstream of the logic circuit for the final latching of the external signal or of a signal derived from the latter.

Abstract: A data buffer circuit includes first and second driver circuits coupled to the data latch circuit and operative to respectively pull up and pull down their outputs towards respective first and second voltages responsive to first and second data signals. An output circuit includes first and second transistors connected at an output node and operative to respectively pull up and pull down the output node toward respective ones of the first and second voltages responsive to respective ones of the outputs of the first and second driver circuits. A transition compensation circuit is operative to control relative rates at the output node of the output circuit transitions toward the first and second voltages responsive to a transition rate control signal.

Abstract: A method and circuit for pre-emphasis equalization of a high speed data communication system can be provided through the use of programmable pulse shaping. A data communication system configured with the pre-emphasis equalization circuit operates by receiving an input data stream and outputting a data stream for transmission through an interconnect or other transmission channel. The data can be passed through an output buffer configured with programmable pre-emphasis equalization, having input inverters at an input stage and output inverters at an output stage. During operation, once an input signal to the input stage transitions, for example from a low to a high state, an input signal to the output stage is configured to a full amplitude to drive the transmission channel. Once the output stage transitions to a full amplitude, the input of the output stage is configured closer to a mid-scale amplitude.

Abstract: A buffer having a circuit for reducing the slope of an input signal and a negative feedback circuit that generates a regulating signal dependent on the variation of the output signal and that applies the regulating signal to the input of the buffer. A precise regulation of the slope, independent of variations in the production process and of environmental conditions, is achieved.

Abstract: A circuit selectively adjusts the width of an input pulse. The circuit comprises two stages. The first stage delays a leading edge of the input pulse with respect to a trailing edge of the input pulse in accordance with a first control input. The second stage delays the trailing edge of the input pulse with respect to the leading edge of the input pulse in accordance with a second control input. The input pulse width is adjusted in accordance with a difference between the delay of the leading edge and the delay of the trailing edge.

Abstract: A pulse generation circuit which can be controlled to generate on-signals and off-signals simultaneously for use in testing the protection circuit of a power device's drive circuitry. The protection circuit prevents faulty operation due to dv/dt transient signals which can cause the S and R input signals to a set-reset flip-flop circuit to simultaneously be HI, resulting in an error condition. Protection circuit 26a has the structure as shown in FIG. 1. A pulse generation circuit, as shown in FIG. 3, can be used to provide simultaneous changes of logic value at B and C to test the protection circuit.

Abstract: A driver circuit having shapable transition signals is disclosed. The driver circuit includes multiple branches of inverter banks connected in parallel. Each of the inverter banks includes an equal number of impedance-controllable inverters connected in series, and a capacitor can be connected between two impedance-controllable inverters within an inverter bank. Each of the impedance-controllable inverter includes an up-level impedance control and a down-level impedance control. Within an inverter bank, the impedance of the impedance-controllable inverters and the capacitance of the capacitors form a set of controlled time constants. By selecting the proper time constants, a desirable up transistor shape and a desirable down transition shape can be obtained for the driver circuit.

Abstract: An apparatus includes a clock generator configured to generate a series of new clock pulses, the clock generator having an input port for receiving input clock pulses, an output port for delivering the new clock pulses to a target circuit that uses the new clock pulses to determine at least a start time or a stop time of a signal generated by the target circuit, and, a pulse delay for governing the width of the new clock pulses, the delay including circuits that produces longer delays for faster corners.

Abstract: An apparatus includes a clock generator configured to generate a series of new clock pulses, the clock generator having an input port for receiving input clock pulses, an output port for delivering the new clock pulses to a target circuit that uses the new clock pulses to determine at least a start time or a stop time of a signal generated by the target circuit, and, a pulse delay for governing the width of the new clock pulses, the delay including circuits that produces longer delays for faster corners.

Abstract: A system for controlling the duty cycle of a clock signal. The system includes a duty cycle adjustment circuit that receives an input clock signal and generates an output clock signal. The duty cycle adjustment circuit charges a capacitor when the input clock signal has a first logic level and discharges the capacitor with the input clock signal has a second logic level. The rates of charge and discharge are controlled by first and second control signals. When the capacitor has been charged to a first transition level, the output clock signal transitions to a first logic level, and when the capacitor has been discharged to a second transition level, the output clock signal transitions to a second logic level. The first and second control signals are supplied by a feedback circuit, which is implemented using an integrator circuit that receives the output clock signal and generates a feedback signal indicative of the duty cycle of the output clock signal.

Abstract: A method and circuit for pre-emphasis equalization of a high speed data communication system can be provided through the use of programmable pulse shaping. A data communication system configured with the pre-emphasis equalization circuit operates by receiving an input data stream and outputting a data stream for transmission through an interconnect or other transmission channel. The data can be passed through an output buffer configured with programmable pre-emphasis equalization, having input inverters at an input stage and output inverters at an output stage. During operation, once an input signal to the input stage transitions, for example from a low to a high state, an input signal to the output stage is configured to a full amplitude to drive the transmission channel. Once the output stage transitions to a full amplitude, the input of the output stage is configured closer to a mid-scale amplitude.

Abstract: A digital circuit which transmits information by a multilevel signal having at least two values. A waveform shaping section is provided to which at least first and second presumption values for defining at least first and second presumption ranges based on said at least two values, respectively, are set. The waveform shaping section performs a waveform shaping for eliminating higher harmonic components of a waveform in each of the presumption ranges and performs a waveform shaping for maintaining abrupt changes of the waveform in a transition period from one of the presumption ranges to another.

Abstract: A signal deciding apparatus which can obtain a stable digital signal OUT irrespective of an amplitude and a duty ratio of an input signal IN is provided. The input signal IN is amplified by inverters (51 to 53 and 8) and outputted as a digital signal OUT. A signal (S5) on the input side of the inverter (8) is integrated by a time constant which is equal to a data period of the input signal IN by an integrator (9) and supplied to a differential amplifier (20). A signal (S8) on the output side of the inverter (8) is integrated by a large time constant by an integrator (10), a control voltage VC supplied from a control terminal (13) is multiplexed to the integrated signal S8, and a resultant signal is sent to the differential amplifier (20). An output signal of the differential amplifier (20) is integrated by a resistor (11) and a capacitor (4) and its average level is fed back as a threshold voltage to the input side of the inverter (51) through a resistor (3) and multiplexed to the input signal IN.

Abstract: A pulse width distortion correction logic level converter that converts differential logic while preserving the pulse width of the original signal. The converter converts a differential input signal to a single-ended signal having a same pulse width as the differential input signal. The present invention receives and converts the differential input signal at a first and a second converter, wherein the first converter generates a first output signal and the second converter generates a second output signal, respectively. Latching the first output signal of the first converter and the second output signal of the second converter produces a fill swing single-ended output signal having the same pulse width as the input differential signal. The first output signal sets the latching device with an edge of the first output signal of the first converter and resets the latching device with an edge of the second output signal of the second converter.

Abstract: A pulse generator for providing a pulse signal with a constant pulse width. An edge detection unit, coupled between a node and a ground terminal, detects an edge of an external clock to set a node to a predetermined level. A delay unit selectively delays the voltage level of the node according to the voltage level of the node. A post-charge unit charges the node to in response to an output of the delay unit. An input control unit controls the transferring of the next external clock according to the output of the delay unit and the external clock. An output unit receives the voltage level of the node to generate the pulse signal.

Abstract: A new family of current mode logic (CML) gates (14) which, in one embodiment includes OR/NOR and AND/NAND gates, as well as more complex logic functions. The circuit uses a complementary signal to drive the gate of a feedback transistor (19) which has the effect of pseudo differential operation. Although it uses only single-ended inputs (A, B), because of this feedback aspect, the circuit has many of the advantages of a differential circuit such as low-voltage operation, higher immunity to noise, and less sensitivity to parasitic elements.

Abstract: An enhanced glitch eater circuit for eliminating glitch signals occurring within a predetermined period from a raising edge or a falling edge of a signal pulse is comprised of an inverter connected to a transmission gate which is controlled by a two-input XNOR (exclusive-NOR) gate receiving a latched signal at one input and a delay latched signal at the other input, the latched signal being from the output of the transmission gate. The latched signal may be reset by a transistor.

Abstract: The object of the present invention is to provide a semiconductor integrated circuit device wherein the input signal is made to have a low amplitude to shorten transition time of the input signal, said integrated circuit device operating at a low power consumption, without flowing of breakthrough current, despite entry of the input signal featuring low-amplitude operations, and said integrated circuit device comprising a gate circuit, memory and processor.

Abstract: Switching on a first line, from a first signal level to a second level, tends to induce a change in signal level of a second line. To reduce induced noise, the second line is connected to a power rail for a predetermined time interval, responsive to the switching on the first line. The connecting for the time interval tends to counteract the change induced in the second line by the signal of the first line.

Abstract: A driver circuit has an output node coupled to a chip pad. A first PFET and a first resistor are connected between a power supply and the output node, wherein the first resistor is connected between the first PFET and the output node. A first NFET and a second resistor are connected between a ground potential and the output node, wherein the second resistor is connected between the first NFET and the output node. A third resistor is connected between an input to the driver circuit and a gate electrode of the first PFET. A fourth resistor is connected between the input to the driver circuit and a gate electrode of the first NFET. The pre-drive circuitry for driving the input to the PFET may include an NFET coupled between the ground potential and the input, wherein the gate electrode of the NFET receives the data signal to be driven.

Abstract: Briefly, in accordance with one embodiment of the invention, a slew rate control circuit for a processor includes: a circuit configuration to produce a signal representing the speed of fabricated transistors; and a circuit configuration to adjust, based at least in part on the signal representing the speed of fabricated transistors, the amount of current produced by a pre-driver stage for an output buffer of the processor. Briefly, in accordance with another embodiment of the invention, an integrated circuit includes: a slew rate control circuit for a buffer including: a register capable of storing at least one binary digital signal, a pre-driver, and at least one pre-driver cell coupled to the pre-driver. The at least one pre-driver cell is coupled to the pre-driver and register so as to modify the amount of current produced by the pre-driver based, at least in part, on the at least one binary digital signal.

Abstract: The present invention comprises positive/negative masking signals which are added to an electronic circuit where ring phenomena may happen during high speed transmission of digital data, so as to eliminate the ring effect, and data can be transferred smoothly. Since the present invention uses only digital electronic circuit to solve the ring effect of related signals, no matter how long the cable between different subsystems is, the ring effect can be masked automatically. The problem of impedance matching is not necessarily considered, so the present invention is very valuable.

Abstract: An input pulse signal is applied to an input terminal of a pulse width controlling logic circuit and integrated by an integrating circuit. A desired output signal is obtained at an output terminal via a C-MOS logic element having an input threshold level that depends on a power supply voltage applied thereto, and an ACC circuit. An average level detecting unit detects an average level of the input pulse signal so that an average level converting unit supplied with an output from the average level detecting unit controls the power supply voltage applied to the C-MOS logic element. The pulse width controlling logic circuit operates on a principle that, as a pulse width is decreased, an average level of the pulse is lowered, and, as a pulse width is increased, an average level of the pulse is raised. Since an input threshold level of a C-MOS logic element depends on the power supply voltage applied thereto such that the threshold level is 1/2 the level of the power supply voltage.

Abstract: Described is a circuit for receiving a differential input signal at two substantially symmetrically built up current paths and for providing an output signal therefrom. At least one current path comprises means for adjusting the timing information of the input signal to the timing information of the output signal. The adjustment can be accomplished by modifying a voltage level in the respective current path until the timing information of the output signals at least substantially represents the timing information of the input signal, e.g. by modifying an impedance or a current in the respective current path. The adjusting of the timing information is executed by applying a defined input signal with a known timing information, comparing the timing information of the resulting output signal with the timing information of the input signal, and modifying at least one voltage level in at least one of the current paths until the timing information of the output and input signals at least substantially match.

Abstract: The output (3) of a level shifter (1) is split into two paths (4,5) with a delay (.tau..sub.1, .tau..sub.2) being introduced into at least one path to enable rise delay and fall delay to be controlled independently of one another. In the context of an integrated circuit which includes a memory device, the use of an additional path allows control of the set-up and hold times in that one transition can be speeded up or slowed down independently of the other transition to achieve the best possible set-up and hold times.

Abstract: A twisted-pair current driver is implemented in CMOS. EMI from sharp changes in the current driven is reduced by gradually changing the current driven when the inputs change. The current driver is divided into N differential drivers, each driving one-Nth of the total switching current to the twisted pair. Delay lines delay when input changes are sent to each of the four differential drivers, staggering their response. Either binary or multi-level-transition (MLT-3) data can be transmitted. A binary-to-MLT converter uses a dummy flip-flop to match delays and eliminate encoding glitches. Either the binary or the MLT-3 encoded data is coupled to the inputs of the delay lines and the differential drivers. The mid-level for MLT-3 is driven when both the inputs are high, causing the differential drivers to split the current among the two differential outputs to the twisted pair.

Abstract: A driver circuit for transmitting data via an output node thereof to a transmission line includes a first driving device coupled to the output node and a second driving device coupled to the same output node. The driver circuit further includes a slew rate controller coupled to the first and second driving devices. The slew rate controller includes a first reference device coupled to the first driving device. The first reference device generates a first current. The slew rate controller also includes a second reference device coupled to the second driving device. The second reference device generates a second current. The slew rate controller further includes a summing device, coupled to the first and second reference devices. The summing node is also coupled to the output node, via an integrating device, to the output node. The summing device generates at the output node a slew rate proportional to the first current when the first driving device is substantially conducting.

Abstract: A pulse generating circuit includes a first portion and a second portion. The first portion is coupled to a control signal and a first signal, and generates the rising edge of a pulse signal in response to the control signal transitioning to a first state. The second portion receives the rising edge of the pulse signal and causes the first signal to transition to a second state in response to the rising edge of the pulse. The transitioning of the first signal to the second state causes the first portion to generate a falling edge of the pulse signal.

Abstract: There are provided an input/output buffer circuit having a reduced power consumption, and an electronic equipment using these buffer circuits. An input buffer is located on an input line while an output buffer is disposed on an output line. Each of the buffers is connected to an input/output line having input/output terminals. A latch circuit is connected to the input/output line and is switched between a first ON state in which the latch circuit is latchable and a first OFF state in which an output end of the latch circuit is in high impedance by a first control signal from a first control terminal. The output buffer is switched between a second ON state in which the output buffer can output a signal and a second OFF state in which an output end of the output buffer is in high impedance by a second control signal from a second control terminal.

Abstract: A pulse generator is composed of switch means to switch supply of a first current through a circuit, a first condenser connected to the switch means in series and primary charged by the first current, voltage raising means having a primary winding serially connected to the first condenser and a secondary winding to obtain voltage output by the first current, magnetic switch means of current flow switchable having a primary winding serially connected to the secondary winding of the voltage raising means and a secondary winding, a second condenser connected to the secondary winding of the magnetic switch means and charged by the output therefrom, and discharging means connected to the second condenser to generate pulse discharge when charged voltage of the second condenser is applied thereto by switching the magnetic switch means.

Abstract: A digital LSI chip comprises the principal element of a printer controller. On the chip are output transistors for driving connection pads and external loads connected thereto. The chip performance is influenced by variations in the manufacturing Process, supply Voltage, and Temperature (PVT). All of these influence the time delay and risetime characteristics of the output transistors, as does varying the gain of predrivers supplying drive signals for the output transistors. To minimize the influence of PVT variables on these characteristics, a table of predrive gain needed to compensate the effect of PVT variables is generated for several points over the PVT range. Likewise, the frequency of a ring oscillator sensor is tabulated over the same points. These data are paired and stored in a memory. At startup and other times, a microprocessor determines the sensor frequency, accesses the table and sets appropriate predriver gains, thereby maintaining the output transistor characteristics nominally constant.

Abstract: The invention relates to an integrated circuit, having an output stage with at least two respective output transistors, respective main current channels of which are connected in parallel between a first supply terminal and the output. A control circuit ensures that, in response to a variation in an input signal on the input, the charging of respective control electrodes of the at least two respective output transistors commences with a delay relative to one another. The peak value of the time derivative of a current output together by the at least two output transistors is thus limited. After the start of charging, a speed of charging of the control electrode of at least one of the two respective output transistors is reduced. The peak value of the time derivative of the current applied to the output by the at least one of the at least two output transistors is thus reduced.

Abstract: A gate clamping circuit is disclosed that includes a logic gate and a bias circuit arrangement. Through this clamping circuit the speed of operation of the circuit during both low to high and high-to-low transitions of the output signal are optimized while power consumption is minimized.

Abstract: A bias generator circuit provides a bias control signal to the gate of a PMOS transistor which has been added to the inverter which drives the final NMOS pull-down transistor of a CMOS output driver circuit. The bias generator circuit includes a constant current source flowing from the positive supply. The bias generator circuit also includes a current difference circuit containing a resistive divider which drives the gate of an NMOS ballast transistor. This ballast transistor has process/voltage/temperature (PVT) characteristics corresponding to those of the final NMOS pull-down transistor in the CMOS output driver. The channel length of the NMOS ballast transistor and the final NMOS pull-down transistor are drawn the same. The ballast transistor subtracts a PVT adjusted current from the constant current source to produce a PVT adjusted output charging current.

Abstract: An output buffer circuit is provided which significantly reduces ground/Vcc bounce and glitches of signals provided to an integrated circuit. The circuit includes a plurality of transistors for providing a drive potential at the output of the device. The transistors are coupled such that they increase in size from the input to the output of the output buffer circuit. A control circuit provides control signals for sequentially turning off the transistors from the largest to smallest device thereby substantially reducing the Vcc bounce and glitches of the signals provided to the integrated circuit by the output buffer circuit.

Abstract: The switching noise generated by a data output buffer is greatly reduced by "precharging" the output node to an intermediate voltage during a system's "dead" time. This is done with a precharging output current pulse having a constant time derivative during a first time interval and a constant time derivative of opposite sign during a second time interval, before performing the actual switching with an output current having a constant time derivative, during a third time interval. The partial precharging with a controlled, triangular-shaped, output current pulse, avoids any abrupt change of output current and thus limits switching noise. The buffer of the invention is particularly useful in high-speed memory devices.