Bus Or Line Termination (e.g., Clamping, Impedance Matching, Etc.) Patents (Class 326/30)
  • Patent number: 9780782
    Abstract: A memory subsystem includes a multi-device package including multiple memory devices organized as multiple ranks of memory. A control unit for the memory subsystem sends a memory access command concurrently to some or all of the ranks of memory, and triggers some of all of the memory ranks that receive the memory access command to change on-die termination (ODT) settings. One of the ranks is selected to execute the memory access command, and executes the command while all ranks triggered to change the ODT setting have the changed ODT setting.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: October 3, 2017
    Assignee: INTEL CORPORATION
    Inventors: Kuljit S Bains, Nadav Bonen
  • Patent number: 9779053
    Abstract: An apparatus that includes a physical interface for a serial interconnect is provided. The physical interface includes a buffer that is selectable to function as a drift buffer or an elastic buffer by a voltage level on a buffer control line. The physical interface also includes encoding logic that can be enabled or disabled by a voltage level on a logic control line. Further, the physical interface also includes and an ordered set generator that can be enabled or disabled by a voltage level on a communications control line.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: October 3, 2017
    Assignee: Intel Corporation
    Inventors: Debendra Das Sharma, Daniel S. Froelich, Venkatraman Iyer, Michelle C. Jen, Rahul R. Shah, Eric M. Lee
  • Patent number: 9780785
    Abstract: Calibration circuits and methods to set an on-chip impedance to match a target impedance where the reference voltage does not equal one-half of the positive power supply voltage Vddq are described. In particular, calibration circuits and methods are provided to enable accurate impedance matching at a reference voltage Vref of K*Vddq, where K is a number between 0 and 1. In some embodiments, a calibration circuit for impedance matching at a reference voltage of K*Vddq uses a ratioed current mirror. In another embodiment, a calibration circuit for impedance matching at a reference voltage of K*Vddq uses a ratioed mirror pull-up circuit. In yet another embodiment, a calibration circuit for impedance matching at a reference voltage of K*Vddq uses a ratioed target impedance.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: October 3, 2017
    Assignee: Integrated Silicon Solution, Inc.
    Inventor: Kim C. Hardee
  • Patent number: 9768780
    Abstract: Described is an apparatus which comprises: a reference device; and a processor having a plurality of circuit units, each circuit unit is operable to electronically couple with the reference device such that only one circuit unit of the plurality of circuit units is electronically coupled to the reference device at a given time while other circuit units of the plurality are electronically uncoupled to the reference device during that time.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: September 19, 2017
    Assignee: INTEL CORPORATION
    Inventor: Luke A. Johnson
  • Patent number: 9768945
    Abstract: Embodiments of the present invention may provide a system with a first and second circuit system separated by an electrical isolation barrier but provided in communication by at least one isolator device that bridges the isolation barrier. The first circuit system may include a communication system to transmit data across a common isolator device as a series of pulses, and the second circuit system may receive the series of pulses corresponding to the data. The second circuit system may include a detector coupled to the common isolator device to detect the received pulses, a oneshot to frame the received pulse(s), and a controller to reconstruct the data based on accumulated framed pulse(s). Therefore, noise induced spurious pulses outside the oneshot intervals may be ignored by the second circuit system providing improved noise immunity.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: September 19, 2017
    Assignee: Analog Devices, Inc.
    Inventors: Michael Mueck, Lawrence Getzin
  • Patent number: 9767884
    Abstract: A semiconductor integrated circuit is described. A transmitter-receiver transmits and receives data to and from outside by a first external terminal and transmits a first control signal by a second external terminal. When another data is transmitted after the data is transmitted and when a data transmission interval from a time when the data is transmitted to a time when the another data is transmitted is equal to or smaller than a first threshold, the transmitter-receiver continuously outputs, from the first external terminal, a potential level of about ½ of a potential level obtained by adding a first potential level and a second potential level, during the data transmission interval, and changes the second potential level of the first control signal to the first potential level when the data transmission interval exceeds the first threshold.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: September 19, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Masayasu Komyo, Yoichi Iizuka
  • Patent number: 9767064
    Abstract: Systems and method for operating a low power universal serial bus are described herein. A universal serial bus port includes a link layer and protocol layer that are compatible with a standard USB2 protocol. The link layer and protocol layer to control a physical layer for transmitting and receiving data on a pair of signal lines. The physical layer includes a fully-digital Low-Speed/Full-Speed (LS/FS) transceiver to transmit and receive data on the pair signal lines using single-ended digital communications on the pair of signal lines.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: September 19, 2017
    Assignee: Intel Corporation
    Inventors: Huimin Chen, Kok Hong Chan
  • Patent number: 9767859
    Abstract: A first reception circuit and a second reception circuit are mounted on a printed circuit board, and receive signals via wiring thereof from a transmission circuit. The printed wiring board includes a trunk wiring, a first branched line branching from a first branch connection point, and a second branched line branching from a second branch connection point in order. A wiring area between the start end and the first branch connection point is divided into a first wiring portion and a second wiring portion, in order from the start end, and a wiring area between the first branch connection point and the second branch connection point is a third wiring portion. The characteristic impedance of the first wiring portion is set to equal or lower than the characteristic impedance of the third wiring portion, and the characteristic impedance of the second wiring portion is set higher than the characteristic impedance of the first wiring portion.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: September 19, 2017
    Assignee: Canon Kabushiki Kaisha
    Inventor: Masanori Kikuchi
  • Patent number: 9762415
    Abstract: A driver circuit for driving a transmission line includes a voltage driver and a current driver. The voltage driver is for driving the transmission line with a first voltage gain in a first operation mode. The current driver is activatable in a second operation mode for driving, together with the voltage driver, the transmission line with a second voltage gain. The transmission line may be an Ethernet-over-copper transmission line with electrical data signals from a data generator.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: September 12, 2017
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Francesco Chrappan Soldavini, Michele Fedeli
  • Patent number: 9760156
    Abstract: A display apparatus, a display system having a plurality of display apparatuses, and a method for controlling the display system are disclosed in which a first voltage of a first transmission channel of a first display apparatus is changed according to transition from a power saving state to a wake-up state and a second display apparatus electrically connected to the first display apparatus detects variation of voltage of a first reception channel corresponding to voltage variation of the first transmission channel and transitions from a power saving state to a wake-up state according to the detection.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: September 12, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Keun Kim, Chang Won Lee
  • Patent number: 9753479
    Abstract: A pre-driver circuit generates a driver bias signal based on a swing command, a driver impedance characteristic, and an input signal. A driver receives the driver bias signal and generates, in response, a driver signal having a swing and having an output impedance corresponding to the bias signal. Optionally, the driver receives power from a switchable one of multiple supply rails, according to the swing. Optionally, the driver has voltage controlled resistor elements and the driver bias signal is generated based on the swing command and a replica of the driver voltage controlled resistor elements.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: September 5, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Madjid Hafizi, Jie Xu, Xiaohua Kong, Nam V. Dang
  • Patent number: 9748933
    Abstract: An example circuit includes: a slew rate driver configured to provide an output voltage; a first voltage provider configured to provide a first input voltage to the slew rate driver in response to the output voltage being within a first range; and a second voltage provider configured to provide a second input voltage to the slew rate driver in response to the output voltage being within a second range. The slew rate driver is further configured to change the output voltage based at least in part on the first input voltage or the second input voltage.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: August 29, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chen-Ting Ko, Chih-Hsien Chang, Ruey-Bin Sheen
  • Patent number: 9748953
    Abstract: A memory module includes a command/address (CA) register, memory devices, and a module resistor unit mounted on a circuit board. The centrally disposed CA register drive the memory devices one or more internal CA signal(s) to arrangements of memory devices using multiple CA transmission lines, wherein the multiple internal CA transmission lines are commonly terminated in the module resistor unit.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: August 29, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Jun Lee, Do-Hyung Kim, Yong-Jin Kim, Bo-Ra Kim, Jeong-Hoon Baek, Kwang-Seop Kim, Da-Ae Heo
  • Patent number: 9747999
    Abstract: A array of electrically programmable fuse (eFuse) units includes at least one connecting switch connecting two adjacent eFuse units. Each eFuse unit includes an eFuse, a write switch for passing through a first portion of a write current, a read/write switch for passing through a second portion of the write current or a read current, and a common node. The eFuse, the write switch, the read/write switch, and the at least one connecting switch are connected to each other at the common node. By turning on and off the at least one connecting switch, the current is split among the eFuse units, so that the size of the write switch can be reduced, thus reducing the total area of the array.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: August 29, 2017
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Chia Chi Yang
  • Patent number: 9748956
    Abstract: An integrated circuit includes an input/output pad, a driver circuit connected to the input/output pad, and a receiver circuit connected to the input/output pad, and a code generator. The driver circuit is configured to output an output signal to an external device through the input/output pad. The receiver circuit is configured to receive an input signal from the external device through the input/output pad. The code generator is configured to generate a termination code of the external device in response to a signal output from the receiver circuit.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: August 29, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jangwoo Lee, HyunJin Kim, Daehoon Na, Jeongdon Ihm
  • Patent number: 9735760
    Abstract: In one example, a device may include a first push-pull driver with a first impedance and a push-pull driver unit with a second push-pull driver having a second impedance. The push-pull driver unit may be in parallel with the first push-pull driver. The device may further include a pulse generating unit to activate the push-pull driver unit for a delay time following an edge transition in an input signal. In one example, the device may have an output impedance that is less than the first impedance when the push-pull driver unit is activated.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: August 15, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Dacheng Zhou, Zhubiao Zhu
  • Patent number: 9715262
    Abstract: A wired-line transmitter may include architecture that provides control of the current profile during power-up and/or power-down of the transmitter. The current profile may include a sloped ramp up during power-up and/or a sloped ramp down during power-down. The sloped ramps of the current profile mitigate supply bouncing during power-up and/or power-down. Individual enable signals may be derived from an enable signal provided to the transmitter. These individual enable signals may be provided (or turned off) in a time delayed (e.g., staggered) manner to provide the sloped ramps for the current profile.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: July 25, 2017
    Assignee: Apple Inc.
    Inventors: Wenbo Liu, Raman S. Thiara, Shingo Hatanaka
  • Patent number: 9711189
    Abstract: A buffer circuit with an adjustable reference voltage is presented. The buffer circuit with adjustable reference voltage has an input buffer circuit that is connected to a data input and a reference voltage. The output of the input buffer circuit is connected an eye monitor circuit that generates a transition signal based on a number of transitions of an output of the input buffer circuit. The output from the eye monitor circuit is that processed by a calibration control circuit that transmits a selection signal to a multiplexer. The multiplexer selects a level of the reference voltage based on the selection signal from the calibration control circuit.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: July 18, 2017
    Assignee: Altera Corporation
    Inventors: Bonnie I. Wang, Chiakang Sung, Xiaobao Wang, Yan Chong, Joseph Huang, Khai Nguyen, Pradeep Nagarajan
  • Patent number: 9712344
    Abstract: A receiving device includes a termination circuit to which a received signal is input, a processing circuit which performs a process at a rear stage of the termination circuit, and an error detection circuit which detects an error contained in the received signal. In a case where the error is detected by the error detection circuit, a termination resistance value of the termination circuit is lowered. Therefore, the receiving device can be rapidly restored when a signal containing an error is received.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: July 18, 2017
    Assignee: THINE ELECTRONICS, INC.
    Inventor: Satoshi Miura
  • Patent number: 9705497
    Abstract: System and method for providing precision a self calibrating resistance circuit is described that provides for matching a reference resistor using dynamically configurable resistance networks. The resistor network is coupled to the connection, wherein the resistor network provides a configurable resistance across the connection. In addition, the resistor network comprises a digital resistor network and an analog resistor network. Also, the circuit includes control circuitry for configuring the configurable resistance based on a reference resistance of the reference resistor. The configurable resistance is configured by coarsely tuning the resistor network through the digital resistor network and fine tuning the resistor network through the analog resistor network.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: July 11, 2017
    Assignee: Invensas Corporation
    Inventors: Curtis Dicke, George Courville, David Fisch, Randall Sandusky, Kent Stalnaker
  • Patent number: 9705533
    Abstract: A method includes digital/analog conversion of a digital signal modulated by information to provide a modulated initial analog signal having a crest factor greater than one, and amplification of the initial analog signal to provide an amplified modulated signal. A modulated channel analog signal derived from the modulated amplified analog signal is transmitted over a communications channel, with impedance of the communications channel varying during the transmission. The method further includes at least one determination during the transmission of a peak-clipping rate of the amplified analog signal over at least one time interval, and an adjustment of a level of the initial analog signal as a function of the determined peak-clipping rate.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: July 11, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Mark Wallis
  • Patent number: 9705498
    Abstract: Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: July 11, 2017
    Assignee: Rambus Inc.
    Inventor: Ian Shaeffer
  • Patent number: 9703361
    Abstract: There is provided a memory control apparatus including a deciding unit deciding, among a first main storage apparatus that is a main storage apparatus with low power consumption and a second main storage apparatus with power consumption higher than the power consumption of the first main storage apparatus as memory devices of multiple CPU cores, whether the second main storage apparatus is capable of being suspended, and a power managing unit suppressing a power supplied to the second main storage apparatus and at least one of the multiple CPU cores in a case where the deciding unit decides that the second main storage apparatus is capable of being suspended.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: July 11, 2017
    Assignee: SONY CORPORATION
    Inventors: Tomohiro Katori, Katsuya Takahashi, Hiroki Nagahama
  • Patent number: 9705499
    Abstract: A system, method, and circuits for power efficient margining in a differential output driver that includes segments connected to outputs of the driver. Each segment can be configured independently to different states by activating corresponding transistor combinations. In a transmitting state, the transistors transmit data by establishing current paths between the driver outputs and a positive supply rail or a ground rail. In a margining state, the transistors are statically configured to form current paths that differ from those of the transmitting state, such that the segment contributes substantially a same differential impedance between the driver outputs as would be contributed by the segment when in the transmitting state, while contributing a different common mode impedance than in the transmitting state. The current paths of the margining state extend through transistors that transmit data in the transmitting state.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: July 11, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jean-Francois Delage, Philippe Salib, Guillaume Fortin
  • Patent number: 9698972
    Abstract: Voltage mode drivers and an electronic apparatus having the same are provided. The voltage mode drivers may include a voltage regulator and a ripple compensation unit connected to an output terminal of the voltage regulator and configured to compare a current data bit of a data pattern with a previous data bit of the data pattern in synchronization with a clock signal input into the ripple compensation unit, generate a control signal when the current data bit is equal to the previous data bit, and apply a ground voltage to the output terminal in response to the control signal.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: July 4, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kangjik Kim, Sanghune Park, Jaehyun Park, Jongshin Shin
  • Patent number: 9698778
    Abstract: An on-die termination (ODT)/driving circuit includes a connection pad, and a sub-circuit. A first side of the sub-circuit is connected to the connection pad. The ODT/driving circuit further includes a first switch directly connected to a second side of the sub-circuit. The second side of the sub-circuit is opposite the first side of the sub-circuit. The first switch is configured to selectively connect the second side of the sub-circuit to a supply voltage. The ODT/driving circuit further includes a second switch directly connected to the second side of the sub-circuit. The second switch is configured to selectively connect the second side of the sub-circuit to a reference voltage. The ODT/driving circuit further includes a receiver connected to a node located between the connection pad and the first side of the sub-circuit.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: July 4, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Tien-Chien Huang
  • Patent number: 9698774
    Abstract: An apparatus having a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to translate an input signal in a first voltage domain to generate a complementary pair of first signals in a second voltage domain. The second circuit may be configured to logically switch the first signals to generate a complementary pair of second signals in the second voltage domain. The first signals may be logically switched such that both of the second signals are inactive before one of the second signals transitions from inactive to active. The third circuit may be configured to amplify the second signals to generate a complementary pair of output signals in the second voltage domain. Each of the output signals generally has a current capacity to drive one or more of a plurality of diodes in a diode switch circuit.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: July 4, 2017
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventors: Chengxin Liu, Christopher D. Weigand
  • Patent number: 9685936
    Abstract: A self-feedback control circuit is connected to a controller area network bus for controlling a high-level output and a low-level output, comprising a controller area network driving circuit and a replica circuit. The replica circuit is connected in parallel with the controller area network driving circuit and comprises an upper feedback path and a lower feedback path. The upper feedback path and the lower feedback path are connected jointly to a common mode, and the replica circuit provides a feedback signal from the common mode such that the feedback signal is able to be respectively transmitted to two individual transistors of the controller area network driving circuit through the upper feedback path and through the lower feedback path so as to control DC level stability of the high-level output and the low-level output.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: June 20, 2017
    Assignee: Amazing Microelectronic Corp.
    Inventors: Long-Xi Chang, Ryan Hsin-Chin Jiang
  • Patent number: 9685944
    Abstract: An integrated circuit includes a drive circuit with a first inverter circuit with a first transistor of a first conductivity type and a second transistor of a second conductivity type. The drains of the first and second transistors are connected. An output circuit is provided having a third transistor of the second conductivity with a gate connected to the drains of the first and second transistors. A capacitor is connected between the gate and a drain of the third transistor and has a capacitance greater than 0.5 pF and less than or equal to 3.0 pF. A gate width of the first transistor when divided by a gate width of the third transistor has a value of less than 1/100. The output circuit is configured to output a transmission signal from the drain of the third transistor.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: June 20, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshiki Seshita
  • Patent number: 9678131
    Abstract: A controller area network (CAN) includes a CAN bus having a CAN-H wire, a CAN-L wire, and a pair of CAN bus terminators located at opposite ends of the CAN bus. The CAN further includes a plurality of nodes including controllers wherein at least one of the controllers is a monitoring controller. The monitoring controller includes a detection control routine for isolating faults on the CAN bus including measuring a CAN-H wire voltage, measuring a CAN-L wire voltage, and isolating a short fault based upon the CAN-H wire voltage and the CAN-L wire voltage.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: June 13, 2017
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Shengbing Jiang, Xinyu Du, Atul Nagose
  • Patent number: 9680469
    Abstract: A driver circuit drives data to an output based on an input data signal in a transmission mode. The driver circuit includes transistors. A comparator generates a comparison output in a calibration mode based on a reference signal and a signal at the output of the driver circuit. A calibration control circuit adjusts an equivalent resistance of the transistors in the driver circuit based on the comparison output in the calibration mode. The equivalent resistance of the transistors in the driver circuit can be adjusted to support the transmission of data according to multiple different data transmission protocols using transmission links having different characteristic impedances. The equivalent resistance of the transistors in the driver circuit can also be adjusted to compensate for resistance in the package routing conductors and/or to compensate for parasitic resistance.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: June 13, 2017
    Assignee: Altera Corporation
    Inventors: Kok Siang Tan, Tim Tri Hoang
  • Patent number: 9673822
    Abstract: A system including a first device having a push-pull circuit configured to transmit a synchronization symbol; and a second device coupled to the first device by a single wire interface, and configured to, in response to receiving the synchronization symbol, transmit a data symbol to the first device while the push-pull circuit is in a tristate phase.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: June 6, 2017
    Assignee: Infineon Technologies AG
    Inventors: Thomas Leutgeb, Walter Kargl, Helmut Koroschetz
  • Patent number: 9673815
    Abstract: A circuit may include first and second input nodes, first and second output nodes, first and second intermediate nodes, first and second resistances, a first amplification transistor coupled to the first input node, the first resistance, and the first intermediate node and a second amplification transistor coupled to the second input node, the second resistance, and the second intermediate node. The circuit may also include a first active device coupled to the first output node and the first intermediate node, a second active device coupled to the second output node and the second intermediate node, a first output transistor coupled to the first output node and configured to conduct based on a second intermediate signal on the second intermediate node, and a second output transistor coupled to the second output node and configured to conduct based on a first intermediate signal on the first intermediate node.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: June 6, 2017
    Assignee: FINISAR CORPORATION
    Inventors: Arik Zafrany, Georgios Kalogerakis
  • Patent number: 9673788
    Abstract: A buffer provides a signal at an output node as a function of an input signal. First and second buffer stages have respective current conduction paths for asserting the output signal. An enabling element selectively enables the second buffer stage in response to assertion of an enabling signal in a state where the first and second buffer stages are both simultaneously enabled. The first buffer stage has hysteresis feedback paths from the output node for providing hysteresis in the buffer response. The hysteresis is smaller when the first and second buffer stages are both enabled than when only the first buffer stage is enabled. The response of the second buffer stage to the input signal, when enabled, is faster than the first buffer stage.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: June 6, 2017
    Assignee: NXP USA, INC.
    Inventors: Yi Zhao, Dongling Zhang
  • Patent number: 9673818
    Abstract: A data transmitting method used in a semiconductor device having a controller and a transmitter is described. A first write command is output by the controller and then a second write command is output by the controller. An interval time between the first write command and the second write command is calculated. The transmitter is activated by the controller and a first data is transmitted by the transmitter in accordance with the first write command, and then the transmitter is inactivated based on the interval time. Then the transmitter is activated when the transmitter is inactivated. Then, the second data is transmitted by the transmitter in accordance with the second write command.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: June 6, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Masayasu Komyo, Yoichi Iizuka
  • Patent number: 9666245
    Abstract: An apparatus includes a first channel, a second channel and a calibration circuit. The first channel includes a first command control circuit. The second channel includes a second command control circuit independent of the first command control circuit. The calibration circuit is shared by the first channel and the second channel to generate a calibration code responsive to a calibration command generated responsive to a first calibration command from the first command control circuit and a second calibration command from the second command control circuit.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: May 30, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Tetsuya Arai, Junki Taniguchi
  • Patent number: 9660734
    Abstract: A radio frequency interference (RFI) mitigation module is provided that is coupled to a high speed data link. The RFI mitigation module is to reduce RFI caused by the high speed data link. The RFI mitigation module includes at least one resister, at least one inductor, and at least one capacitor.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 23, 2017
    Assignee: Intel Corporation
    Inventor: Hao-Han Hsu
  • Patent number: 9654106
    Abstract: A dynamic digital filtering system for detecting electrical noise in a discrete I/O circuit. The dynamic digital filtering system has a controller for monitoring the logic signal produced by a logic device monitoring a remote I/O device. The logic device includes a circuit for dynamically adjusting the impedance across a power terminal and a terminal receiving a binary signal from the I/O device. Upon a change of state of the monitored logic signal the controller commands the impedance adjusting circuit to momentarily change its input impedance to determine if the binary signal responsible for the monitored change of state of the logic signal was true or false. If the monitored logic signal does not change state during the momentary change in impedance the binary signal will be verified as “true”. If the monitored logic signal does change state during the momentary change in impedance the binary signal will be considered as “false”.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: May 16, 2017
    Assignee: SCHNEIDER ELECTRIC USA, INC.
    Inventors: Kevin M. Jefferies, Benjamin W. Edwards, Matthew L. White, Konstantin Alexander Filippenko, Richard Karl Weiler
  • Patent number: 9645631
    Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: May 9, 2017
    Assignee: Rambus Inc.
    Inventors: Dinesh Patil, Amir Amirkhany, Farrukh Aquil, Kambiz Kaviani, Frederick A. Ware
  • Patent number: 9647663
    Abstract: An input buffer circuit that receives differential signals includes a first resistive path circuit, a second resistive path circuit and a feedback circuit. The first resistive path circuit may generate a first common mode voltage from the differential signals. The feedback circuit is coupled to the first resistive path circuit. The feedback circuit receives the first common mode voltage as an input. The second resistive path circuit includes a transistor circuit and a resistor formed in a serial circuit configuration. The second resistive path circuit may generate a second common mode voltage on a node formed between the transistor circuit and the resistor by controlling activation of the transistor circuit using outputs from the feedback circuit. The first common mode voltage may be substantially identical to the second common mode voltage.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: May 9, 2017
    Assignee: Altera Corporation
    Inventor: Hoong Chin Ng
  • Patent number: 9647721
    Abstract: The various embodiments herein provide a system and method to provide a high speed data transmission over a wired network. The system comprising a transmitting end, a first electrical circuitry provided at the transmitting end to generate an electrical disturbance according to an input signal received from a source network, a receiving end, a second electrical circuitry provided at the receiving end to detect a signal disturbance, to amplify the signal and to regenerate the transmitted signal data from the received signal and a wired network interconnecting the transmitting end and the receiving end. The generated disturbance is transmitted over the wired network using a single conductor as positive spikes, negative spikes or as signals closely resembling the input signal. The receiving end employs a line disturbance detection scheme without necessarily requiring a common ground connection.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: May 9, 2017
    Assignee: KFX CIRCUITS AND SYSTEMS PRIVATE LIMITED
    Inventor: Nishil Thomas Koshy
  • Patent number: 9647666
    Abstract: A transmitter may include a pre-driver and a main driver. The pre-driver may be configured to generate a pull-up signal and a pull-down signal in response to an enabling signal and a first data. The main driver may receive an external voltage and a ground voltage. The main driver may be configured to generate a transmission data in response to the pull-up signal and the pull-down signal. The pull-up signal and the pull-down signal may be enabled to a voltage level higher than the external voltage applied to the main driver.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: May 9, 2017
    Assignee: SK hynix Inc.
    Inventors: Sang Muk Oh, Jong Chern Lee, Jun Hyun Chun
  • Patent number: 9641177
    Abstract: A data transmitting method used in a semiconductor device having a controller and a transmitter is described. A first write command is output by the controller and then a second write command is output by the controller. An interval time between the first write command and the second write command is calculated. The transmitter is activated by the controller and a first data is transmitted by the transmitter in accordance with the first write command, and then the transmitter is inactivated based on the interval time. Then the transmitter is activated when the transmitter is inactivated. Then, the second data is transmitted by the transmitter in accordance with the second write command.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: May 2, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Masayasu Komyo, Yoichi Iizuka
  • Patent number: 9634653
    Abstract: The disclosure provides a detector that includes a pre-charge circuit. The pre-charge circuit receives a supply voltage. A pre-charged comparator is coupled to the pre-charge circuit and receives the supply voltage. The pre-charged comparator generates a transition signal at a transition node. A slope of the transition signal is greater than a slope of the supply voltage. A first diode connected transistor receives the supply voltage. A first capacitor is coupled to the first diode connected transistor. An inverter is coupled to the first diode connected transistor and generates an enable signal when the supply voltage is below a threshold voltage.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: April 25, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Anand Subramanian, Subramanian J. Narayan
  • Patent number: 9634823
    Abstract: A system for integrated self-interference cancellation, comprising a transmit coupler, coupled to a transmit signal, that samples the transmit signal to create a sampled transmit signal; an analog self-interference canceller, coupled to the transmit coupler, comprising a controller; a signal divider, that splits the sampled transmit signal into a set of signal components; a set of phase shifters, wherein a phase shifter of the set shifts a signal component of the set of signal components by a total phase shift value; a set of scalers, wherein a scaler of the set scales the signal component by a total scale factor; a signal combiner, that combines the set of signal components into a self-interference cancellation signal; and a receive coupler, coupled to a receive signal, that combines the self-interference cancellation signal with the receive signal to remove a portion of self-interference present in the receive signal.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: April 25, 2017
    Assignee: Kumu Networks, Inc.
    Inventors: Wilhelm Steffen Hahn, Alfred Riddle, Ernie Landi
  • Patent number: 9621160
    Abstract: Integrated circuit devices and methods of operating integrated circuit devices are useful in impedance adjustment. Integrated circuit devices include a signal driver circuit having an output node, a voltage node, and a first termination device and a second termination device connected in parallel between the voltage node and the output node. The first termination device and the second termination device each have a particular configuration of switchable resistances, and different strengths. Methods include connecting a node of the integrated circuit device to a first voltage node through a reference resistance, connecting the node to a second voltage node through a termination device, adjusting a resistance value of the termination device and comparing a resulting voltage level to a reference voltage. The reference voltage has a voltage level different than half-way between a voltage level of the first voltage node and a voltage level of the second voltage node.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: April 11, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Qiang Tang
  • Patent number: 9621380
    Abstract: A transmission device of the disclosure includes a first selector configured to select one of a first signal and a second signal, and output the selected signal; a second selector configured to select one of an inversion signal of the first signal, the second signal, and an inversion signal of the second signal, and output the selected signal; a first control signal generator configured to generate a first control signal, a second control signal, and a third control signal, based on the first signal, the second signal, and a third signal; a first driver configured to set a voltage of a first output terminal, based on an output signal of the first selector and the first control signal; and a second driver configured to set a voltage of a second output terminal, based on an output signal of the second selector and the second control signal.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: April 11, 2017
    Assignee: Sony Corporation
    Inventor: Takanori Saeki
  • Patent number: 9614531
    Abstract: A termination resistance adjustment circuit includes a replica circuit having the same characteristics as drive circuits; a current source being able to adjust the amount of a load current of the replica circuit; a voltage generation circuit to generate a plurality of reference voltages respectively corresponding to a plurality of values of the input data with the plurality of bits; a comparison circuit to compare an output voltage of the replica circuit with the reference voltages; and a control circuit to change the amount of the load current by controlling the current source, to calculate values of the output resistances of the replica circuit for each of the plurality of levels, and to adjust the number of use of the drive circuits for each bit of the input data, based on the calculated values of the output resistances for each of the plurality of levels.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: April 4, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Takayuki Shibasaki
  • Patent number: 9608632
    Abstract: A resistance calibration method for a first resistor of a first module includes performing resistance calibration on a calibration unit of a second module, wherein the first module is connected to the second module via a pad coupled to the first resistor and the calibration unit is coupled to the pad; obtaining a resistance value of the calibration unit after the resistance calibration; and calibrating a resistance value of the first resistor according to the resistance value of the calibration unit.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: March 28, 2017
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Chien-Hsi Lee, Yao-Cheng Chuang
  • Patent number: 9606557
    Abstract: An integrated circuit may include a receiver suitable for comparing voltage levels of an external signal and a reference voltage with each other, and generating an internal signal, an adjustment code generation unit suitable for detecting a duty of the internal signal and generating an adjustment code of one or more bits, and a voltage adjustment unit suitable for adjusting the voltage level of the reference voltage in response to the adjustment code.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: March 28, 2017
    Assignee: SK Hynix Inc.
    Inventor: Kwan-Dong Kim