Bus Or Line Termination (e.g., Clamping, Impedance Matching, Etc.) Patents (Class 326/30)
  • Patent number: 9166583
    Abstract: In a memory module having an integrated-circuit buffer device coupled to one or more integrated-circuit memory devices, the buffer device receives write data signals from an external control component via a set of data inputs, the write data signals indicating write data to be stored within one or more of the memory devices. Logic within the buffer device sequentially applies controllable termination impedance configurations at the data inputs based on an indication received from the control component and an internal state of the buffer device, applying a first controllable termination impedance configuration at each of the data inputs during a first internal state of the buffer device corresponding to the reception of the write data signals on the data inputs, and applying a second controllable termination impedance configuration at each of the data inputs during a second internal state of the buffer device that succeeds the first internal state.
    Type: Grant
    Filed: October 26, 2014
    Date of Patent: October 20, 2015
    Assignee: Rambus Inc.
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Patent number: 9160339
    Abstract: Disclosed herein is a device that includes: a data terminal; an output buffer coupled to the data terminal, the output buffer including a first output unit having a plurality of first output transistors of a first conductivity type and a second output unit having a plurality of second output transistors of a second conductivity type; and a calibration circuit including a first code generation unit that generates a first control code that controls an impedance of the first output unit by performing a first calibration operation based on an impedance of a first reference unit and a second code generation unit that generates a second control code that controls an impedance of the second output unit by performing a second calibration operation based on an impedance of a second reference unit. The calibration circuit performs the first and second calibration operations in parallel.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: October 13, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Tatsuya Matano
  • Patent number: 9153296
    Abstract: Described herein are a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory input-output (I/O) interface of a memory in response to a termination signal level. The method comprises: setting a first termination impedance value setting for a termination unit of an input-output (I/O) interface of a memory; assigning the first termination impedance value setting to the termination unit when the memory is not being accessed; and switching from the first termination impedance value setting to a second termination impedance value setting in response to a termination signal level.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: October 6, 2015
    Assignee: Intel Corporation
    Inventors: James A. McCall, Kuljit S. Bains
  • Patent number: 9143121
    Abstract: A method includes receiving an input clock signal at a programmable buffer. The method further includes filtering an output signal from the programmable buffer to generate a filtered signal having a voltage level, where the voltage level indicates a duty cycle of the output signal. The method further includes comparing the voltage level to a reference voltage. The method further includes modifying at least one operating parameter of the programmable buffer to adjust the duty cycle of the output signal.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: September 22, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Jason Gonzalez, Vannam Dang, Zhi Zhu
  • Patent number: 9128716
    Abstract: A memory device and a control method are disclosed herein. The memory device includes a delay locked loop module, a memory bank module and a control module. The delay locked loop module is configured to generate a system clock signal when enabled by a control signal. The memory bank module is configured to read or write data signals in accordance with the system clock signal and a read command or a write command. The control module configured to receive at least one control command to generate the control signal, wherein the control module disables the delay locked loop module, when the memory bank module goes to a precharge mode or a powerdown mode.
    Type: Grant
    Filed: January 20, 2014
    Date of Patent: September 8, 2015
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Jongtae Kwak, Kallol Mazumder
  • Patent number: 9130563
    Abstract: A programmable receiver of an integrated circuit is described. The programmable receiver comprises an input; a first programmable receiver circuit coupled to the input, wherein the first programmable receiver circuit has a first pull-up branch and a first pull-down branch and is controlled by a first enable circuit; a second programmable receiver circuit coupled to the input, wherein the second programmable receiver circuit has a second pull-up branch and a second pull-down branch and is controlled by a second enable circuit; and an output stage coupled to the first programmable receiver circuit and the second programmable receiver circuit, wherein the output stage receives an output of one of the first programmable receiver circuit and the second programmable receiver circuit. A method of implementing a programmable receiver in an integrated circuit is also disclosed.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: September 8, 2015
    Assignee: XILINX, INC.
    Inventor: Gautham S. Jami
  • Patent number: 9124461
    Abstract: Aspects of the disclosure provide a method. The method includes causing a voltage level of a signal transmitted on a transmission line to be non-linearly modified to reduce a voltage variation at a target level, and providing the modified signal to a receiving circuit that is disposed on the transmission line. In an embodiment, the method includes causing the voltage level of the signal transmitted on the transmission line to be non-linearly modified to reduce a first voltage variation at a first target level corresponding to a first digital value and to reduce a second voltage variation at a second target level corresponding to a second digital value.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: September 1, 2015
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventors: Liav Ben Artsi, Ido Bourstein
  • Patent number: 9124252
    Abstract: Provided is a semiconductor apparatus which includes a plurality of output buffers configured to connect a plurality of power sources, and a data noise measuring unit configured to fix an output data of a selected output buffer among the plurality of output buffers to have a specific level, measure a noise of the output data using a capacitance and control a slew rate of the plurality of output buffers based on the noise.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: September 1, 2015
    Assignee: SK Hynix Inc.
    Inventors: Sung Woo Han, Ic Su Oh, Jun Ho Lee, Boo Ho Jung, Sun Ki Cho, Yang Hee Kim, Tae Hoon Kim
  • Patent number: 9118312
    Abstract: An on-die termination circuit includes: a clock signal generation block configured to output a clock signal in response to a clock enable signal, a termination block configured to perform a termination operation on an input/output pad in response to the clock signal, a first termination control signal, and a second termination control signal, a first termination control block configured to generate the first termination control signal in response to the clock signal and a latency control signal, a second termination control block configured to control a latency of a second command and to generate the second termination control signal in response to the clock signal and the latency control signal, and a clock enable signal generation block configured to generate the clock enable signal in response to the first command, the first termination control signal, and the second command.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: August 25, 2015
    Assignee: SK Hynix Inc.
    Inventor: Jong Ho Jung
  • Patent number: 9105317
    Abstract: Provided are a semiconductor memory device and a memory system including the same, which may calibrate a level of an output voltage in consideration of channel environment and a mismatch in on-die termination (ODT) resistance of a memory controller. The memory system includes a memory controller and a semiconductor memory device. The semiconductor memory device is configured to generate a reference voltage based on driving information of the memory controller, and calibrate an output voltage level based on a reference voltage when the semiconductor memory device is electrically connected to the memory controller.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: August 11, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon-Joo Eom, Young-Jin Jeon, Yong-Cheol Bae, Young-Chul Cho
  • Patent number: 9104316
    Abstract: For runtime dynamic performance skew elimination in a computer environment, an exemplary computer environment is configured for calculating a rank heats by utilizing a plurality of fine-grained statistics collected at an extent granularity, including considering bandwidth (BW) and input/outputs per second (IOPS) metrics. An adaptive data placement plan is generated to relocate the data.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: August 11, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence Y. Chiu, Paul H. Muench, Sangeetha Seshadri
  • Patent number: 9106329
    Abstract: A semiconductor chip comprises an internal clock circuit, a first phase shift device, a second phase shift device, a multiplexer, a first output pad, and a controllable pad. The internal clock circuit generates an internal clock signal. The first phase shift device shifts the phase of an external clock signal and outputs a phase shifting clock signal. The multiplexer selectively outputs one of the internal clock signal and the phase shifting clock signal to be a first clock signal. The second phase shift device shifts the phase of the first clock signal and outputs a second clock signal. The first output pad outputs the first clock signal. The controllable pad is controlled to selectively act as an input pad for receiving the external signal, or act as a second output pad for transmitting the second clock signal.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: August 11, 2015
    Assignee: MEDIATEK INC.
    Inventors: Ming-Luen Liou, Rong-Liang Chiou
  • Patent number: 9104817
    Abstract: A method for explicit control message signaling includes sending a single ended 1 signal on a pair of data lines, wherein the pair of data lines includes a first data line and a second data line. A voltage of the first data line is driven to a logic 1, while pulsing the voltage of the second data line between a logic 1 and a logic 0, wherein the pulses represent a control message.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: August 11, 2015
    Assignee: Intel Corporation
    Inventors: Huimin Chen, Kok Hong Chan
  • Patent number: 9106222
    Abstract: A system for controlling the termination impedance of memory device data bus terminals is fabricated on the same die as the memory device. The system includes a termination resistor connected to each data bus terminal, which is connected in parallel with several transistors that are selectively turned on to adjust the termination impedance. The transistors are controlled by a circuit that determines the resistance of the termination resistor and turns on the correct number of transistors to properly set the termination impedance. In one example, the resistance of the termination resistor is determined by measuring a resistor of the same type as the termination resistor. In another example, the resistance of the termination resistor is determined indirectly by measuring parameters that affect the resistance of the termination resistor. In either case, the system can maintain the termination impedance of the data bus terminals constant despite changes in the termination resistor.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: August 11, 2015
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: David Kao
  • Patent number: 9099990
    Abstract: A high-speed bus interface with an adaptive swing driver. A high speed interface includes a transmitter and a receiver coupled via a bus. The transmitter has an adaptive swing driver and a voltage-regulating-module (VRM). The adaptive swing driver includes a post-driver and a pre-driver. The post-driver provides an adaptive swing output with a dedicated adaptive voltage power supply (VDDQ) and transition emphasis driving capacity with an internal logic voltage supply (VDD). The pre-driver provides the transition emphasis driving capacity with a pull-up and a pull-down signal path to the post-driver. The voltage-regulating-module is configured to supply signal to the adaptive swing driver. The receiver includes a comparator and a bit-error-rate detector. The comparator amplifies the adaptive swing output received from the transmitter via a bus, while the bit-error-rate detector diagnoses the amplified adaptive swing output received from the comparator.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: August 4, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying-Yu Hsu, Yung-Chow Peng, Min-Shueh Yuan, Chih-Hsien Chang
  • Patent number: 9094000
    Abstract: Some of the embodiments of the present disclosure provide an integrated circuit communicating with a device over a multi-pin parallel bus, the integrated circuit comprising: at least a first pin and a second pin to communicate with the device over the multi-pin parallel bus; and an impedance tuning module disposed in the integrated circuit and configured to tune an impedance value of a first impedance associated the first pin separately from tuning an impedance value of a second impedance associated with the second pin.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: July 28, 2015
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventors: Eldad Bar-Lev, Ofer Benjamin
  • Patent number: 9093991
    Abstract: A line driving circuit in which a signal characteristic is improved and a semiconductor device including the same are provided. The semiconductor device includes: a line controller arranged in a first portion of at least one line; a first driver arranged in the first portion and configured to output through the at least one line a first signal according to a control of the line controller; and a second driver arranged in a second portion of the at least one line and configured to output through the at least one line a second signal according to a level of the first signal.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: July 28, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Won-ho Choi, Jae-jung Park, Chang-eun Kang, Hyeok-jong Lee
  • Patent number: 9078301
    Abstract: Output stage circuit is added to the gate driving circuit of the LCD. The output stage circuit moderates the falling slope of the gate driving signal so as to reduce the feed-through phenomenon. The output stage circuit includes a discharge circuit which discharges the voltage of the gate driving signal with programmable speeds. The discharge circuit has a plurality of discharge units which are turned on sequentially and designed with different driving abilities. At beginning of falling of the gate driving signal, the discharge circuit discharges the gate driving signal with lower driving ability so that the gate driving signal falls with a lower speed. As time passes, the falling speed of the gate driving signal increases by the increasing of the driving ability of the discharge circuit. The entire falling period of the gate driving signal is prolonged by the output stage circuit and the feed-through phenomenon is eased.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: July 7, 2015
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Po-Ching Li, Chao-Chih Hsiao
  • Patent number: 9077332
    Abstract: An impedance control circuit includes a pull-up code generator configured to generate pull-up impedance control codes using a voltage of a first node, a pull-up impedance unit configured to pull-up-drive the first node in response to the pull-up impedance control codes, a plurality of dummy impedance units enabled in response to respective select signals and each configured to pull-up-drive a second node in response to the pull-up impedance control codes, a pull-down code generator configured to generate pull-down impedance control codes using a voltage of the second node, and a plurality of pull-down impedance units enabled in response to the respective select signals and each configured to pull-down-drive the second node in response to the pull-down impedance control codes.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: July 7, 2015
    Assignee: SK Hynix Inc.
    Inventor: Hyeong-Jun Ko
  • Patent number: 9058998
    Abstract: An input signal having a high level or a low level is input to a pad. A first protection element includes a first transistor configured as an N-channel MOSFET designed so as to withstand ESD. A second protection element includes a second transistor configured as a P-channel MOSFET designed so as to withstand ESD. A capacitance element is connected to a second line, and forms an RC filter together with a filter resistor. The capacitance element includes at least one from among a third transistor having the same device structure as that of the first transistor and a fourth transistor having the same device structure as that of the second transistor.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: June 16, 2015
    Assignee: ROHM CO., LTD.
    Inventor: Kenji Arai
  • Patent number: 9048814
    Abstract: A resistance adjusting circuit including, a reference resistor, a first power source configured to output a first voltage, a first current source configured to output a first current based on a reference current set by using the reference resistor, a first variable resistor, a second current source configured to output a second current obtained by multiplying the first current by a reciprocal ratio, the reciprocal ratio being obtained as a reciprocal number of a ratio of a target resistance of the first variable resistor to a resistance of the reference resistor, and a controller configured to set a resistance of the first variable resistor so that a voltage at a second terminal of the reference resistor and a voltage at a connecting part of the first variable resistor and the second current source become equal to each other.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: June 2, 2015
    Assignees: FJUITSU LIMITED, SOCIONEXT INC.
    Inventors: Naoya Shibayama, Masatoshi Yoshida
  • Patent number: 9047986
    Abstract: To decrease the circuit scale necessary for the calibration of the output circuit and to decrease the time required for the calibration operation. The invention includes a first output buffer and a second output buffer that are connected to a data pin, and a calibration circuit that is connected to a calibration pin. The first output buffer and the second output buffer include plural unit buffers. The unit buffers have mutually the same circuit structures. With this arrangement, the impedances of the first output buffer and the second output buffer can be set in common, based on the calibration operation using the calibration circuit. Consequently, both the circuit scale necessary for the calibration operation and the time required for the calibration operation can be decreased.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: June 2, 2015
    Assignee: PS4 LUXCO S.A.R.L.
    Inventor: Hiroki Fujisawa
  • Publication number: 20150145556
    Abstract: An IO driver for an integrated circuit and a method for calibrating such an IO driver are provided. The IO driver comprises a plurality of IO driver cells, a plurality of IO partial driver cells and an external resistor. The IO driver cells control IO operations for a corresponding plurality of data channels of the integrated circuit. The IO partial driver cells are coupled to respective cells of the plurality of IO driver cells. The external resistor provides a reference impedance. The reference partial driver cell is coupled to the external resistor and is arranged to determine the reference impedance and to provide information depending on the reference impedance to the IO partial driver cells. The IO partial driver cells are arranged to calibrate the respective IO driver cells based on the provided information.
    Type: Application
    Filed: May 30, 2012
    Publication date: May 28, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Michael Priel, Dan Kuzmin, Sergey Sofer
  • Publication number: 20150130507
    Abstract: Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.
    Type: Application
    Filed: January 16, 2015
    Publication date: May 14, 2015
    Inventor: Huy Nguyen
  • Patent number: 9030229
    Abstract: An impedance tuning circuit includes a calibration unit and a post-processing unit. The calibration unit generates an initial pull-up code and an initial pull-down code by performing a calibration operation using an external resistor during an initial impedance tuning operation. The post-processing unit outputs the initial pull-up code and the initial pull-down code as a final pull-up code and a final pull-down code during the initial impedance tuning operation, and generates the final pull-up code and the final pull-down code by using the initial pull-up code and the initial pull-down code during a subsequent impedance tuning operation.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: May 12, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kyung Hoi Koo
  • Patent number: 9024654
    Abstract: An active termination circuit for a differential receiver includes a first receiver element configured to receive a first component of a differential signal, a second receiver element configured to receive a second component of a differential signal, a common mode measurement element configured to receive the differential signal and generate a transmit common mode signal (Vcm) representing an average value of the differential signal, and a receiver (RX) common mode signal node. The termination circuit also comprises an active element configured to receive the transmit common mode signal (Vcm) and provide an output to the receiver common mode signal node, the output configured to drive the value of the signal at the receiver common mode signal node to the value of the transmit common mode signal (Vcm), and a capacitive element coupled to the receiver common mode signal node in parallel with the active element.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: May 5, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Robert Thelen, Michael Farmer, Jade Kizer
  • Publication number: 20150115999
    Abstract: A semiconductor memory device includes a ZQ calibration unit configured to generate an output high level voltage (VOH) code according to a VOH control code obtained from a result of comparing a reference voltage with a first VOH; and an output driver configured to generate a data signal having a second VOH determined by the VOH code. The VOH control code includes a pull-up VOH control code and a pull-down VOH control code and the VOH code includes a pull-up VOH code and a pull-down VOH code.
    Type: Application
    Filed: August 15, 2014
    Publication date: April 30, 2015
    Inventor: Ki Won Lee
  • Patent number: 9018974
    Abstract: An impedance calibration device includes: a variable impedance, an operational unit, an analog-digital converter, and a controller. The operational unit receives a first analog signal and a second analog signal, and performs a difference operation to generate an output voltage. The analog-digital converter generates an adjustment code according to the output voltage. The controller is coupled to the analog-digital converter and the variable impedance, and adjusts a resistance value of the variable impedance according to the adjustment code.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: April 28, 2015
    Assignee: Realtek Semiconductor Corp.
    Inventors: Che-Wei Chang, Cheng-Pang Chan, Jian-Ru Lin
  • Patent number: 9018973
    Abstract: A device, comprising an output terminal; an output circuit coupled to the output terminal and having an adjustable impedance; and an impedance adjustment circuit adjusting stepwise the adjustable impedance so as to head toward a first reference impedance. The impedance adjustment circuit changes the adjustable impedance by a first amount when the adjustable impedance is within a first range, and changes the adjustable impedance by a second amount when the adjustable impedance is out of the first range. The first amount is smaller than the second amount.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: April 28, 2015
    Assignee: PS4 Luxco S.A.R.L.
    Inventors: Nakaba Kaiwa, Yutaka Ikeda
  • Publication number: 20150109023
    Abstract: An output driver for driving a data output signal through an output pad includes a plurality of calibration paths to calibrate the impedance of the output pad. Depending upon the desired impedance, various ones of the calibration paths are selectively coupled to the output pad. Each selected calibration path adds a capacitive load to a data node, which affects the slew rate for the data output signal. To adjust the capacitive load on the data node in light of the calibration path selections, the output driver includes a plurality of selectable capacitors corresponding to the plurality of calibration paths. If a calibration path is not selected to couple to the output pad, the corresponding selectable capacitor capacitively loads the data node.
    Type: Application
    Filed: October 17, 2013
    Publication date: April 23, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Michael Brunolli, Mark Wayland
  • Patent number: 9007114
    Abstract: A semiconductor device for stably generating a clock signal from a strobe signal includes a processor, a clock signal generation unit receiving a first strobe signal and a second strobe signal to generate the clock signal, and a data reception unit receiving at least one data signal to provide the received data signal to the processor. The clock signal generation unit may comprise a strobe comparator comparing a voltage of a first input terminal with that of a second input terminal to output logic high or logic low, a first switch selectively connecting one of a first and a second signal line to the first input terminal, a second switch selectively connecting one of the second signal line and a reference line to the second input terminal, and a voltage stabilizing circuit pulling up/down at least one of a voltage of the first and the second signal line.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: April 14, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kyunghoi Koo
  • Patent number: 9000850
    Abstract: A method and an apparatus for self-calibration of a driving capability and a resistance of an on-die termination are provided. The apparatus includes an output interface physical layer (PHY) and a ring oscillator. The output interface PHY receives an operation voltage. The ring oscillator surrounds the output interface PHY to sense a work temperature or the operation voltage and accordingly outputs a sensing result. The driving capability or the resistance of the on-die termination of the output interface PHY is adjusted according to the sensing result.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: April 7, 2015
    Assignee: Novatek Microelectronics Corp.
    Inventors: Yao-Cheng Chuang, I-Huan Huang
  • Patent number: 9000800
    Abstract: A system for calibrating impedance of an input/output (I/O) buffer on a semiconductor die includes: the I/O buffer; a temperature sensor on the semiconductor die; and a supply sensor on the semiconductor die. The temperature sensor is configured to acquire temperature information for calibrating the I/O buffer. The supply sensor is configured to acquire voltage information for calibrating the I/O buffer. The I/O buffer comprises: a memory component coupled to the temperature and supply sensors and configured to store the acquired temperature or voltage information; a logic component coupled to the memory component; and a driver with driver legs. The driver is coupled to the logic component. The logic component is configured to generate driver control signals representing an on/off configuration for the driver legs of the driver based at least in part on the acquired temperature information or the acquired voltage information stored in the memory component.
    Type: Grant
    Filed: September 17, 2012
    Date of Patent: April 7, 2015
    Assignee: Xilinx, Inc.
    Inventors: Ionut C. Cical, Edward Cullen, Ivan Bogue
  • Patent number: 9001597
    Abstract: A semiconductor device includes a first input terminal receiving a termination resistance control signal, and a termination resistance circuit that is able to be controlled to be turned on or off by the termination resistance control signal. The termination resistance circuit is turned off, irrespective of a level of said termination resistance control signal when the semiconductor device outputs data in response to a read command.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: April 7, 2015
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Atsuo Koshizuka
  • Publication number: 20150091611
    Abstract: Impedance calibration circuits are provided. The impedance calibration circuit includes an operation control signal generator and an impedance calibrator. The operation control signal generator receives temperature code signals to generate an operation control signal enabled when an internal temperature is changed from a first temperature to a second temperature. The impedance calibrator receives an external command signal or the operation control signal to generate pull-up code signals for pulling up an output signal and pull-down code signals for pulling down the output signal according to an external resistor.
    Type: Application
    Filed: February 11, 2014
    Publication date: April 2, 2015
    Applicant: SK hynix Inc.
    Inventor: Hyun Sik JEONG
  • Patent number: 8994399
    Abstract: A transmission line driver including an output configured to have a load impedance is provided. The transmission line driver includes a pull-up circuit coupled in series with the output. The transmission line driver also includes a pull-down circuit coupled in series with the output. The transmission line driver includes a shunt circuit having an adjustable impedance. The shunt circuit is coupled in parallel to the output. The shunt circuit is coupled to the pull-up circuit and the pull-down circuit. The shunt circuit is configured to receive a shunt control signal to adjust the adjustable impedance to provide linear control of an output swing at the output.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: March 31, 2015
    Assignee: Broadcom Corporation
    Inventor: Tamer Ali
  • Publication number: 20150084672
    Abstract: An integrated circuit device transmits to a dynamic random access memory (DRAM) one or more commands that specify programming of a digital control value within the DRAM, the digital control value indicating a termination impedance that the DRAM is to couple to a data interface of the DRAM in response to receiving a write command and during reception of write data corresponding to the write command, and that the DRAM is to decouple from the data interface after reception of the write data corresponding to the write command. Thereafter, the integrated circuit device transmits to the DRAM a write command indicating that write data is to be sampled by a data interface of the DRAM during a first time interval and that cause the DRAM to couple the termination impedance to the data interface during the first time interval and decouple the termination impedance from the data interface after the first time interval.
    Type: Application
    Filed: December 4, 2014
    Publication date: March 26, 2015
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Patent number: 8988100
    Abstract: Described are amplifiers that facilitate high-speed communication with calibrated drive strength and termination impedance. Drivers and termination elements can be divided into a number N of parallel portions, one or more of which can be disabled and updated without interfering with signal (e.g., clock or data) transmission. Some embodiments identify inactive elements by examining incoming signals.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: March 24, 2015
    Assignee: Rambus Inc.
    Inventors: Huy M. Nguyen, Vijay Gadde, Sivakumar Doraiswamy
  • Patent number: 8988102
    Abstract: Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: March 24, 2015
    Assignee: Rambus Inc.
    Inventor: Ian Shaeffer
  • Patent number: 8988916
    Abstract: A memory structure with reduced-reflection signals at least includes a processing unit; a lumped circuit unit, connected to the processing unit; a plurality of memories, connected to the lumped circuit unit; and a reflected signal absorption unit, disposed at one end of the lumped circuit unit. Thereby, with the cooperation of the processing unit with each memory for signal transmission, the reflected signal absorption unit can be used to absorb the reflected signals so as to reduce the number of reflected signals during signal transmission, achieving the effect of stable operation for the memories.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: March 24, 2015
    Assignee: Eorex Corporation
    Inventor: Cheng-Lung Lin
  • Patent number: 8988101
    Abstract: According to example embodiments, a method for operating a memory device includes receiving an on-die termination (ODT) signal through an ODT pin, and issuing a command or controlling an ODT circuit according to the ODT signal.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In Dal Song, Jung Hwan Choi, Yun Seok Yang
  • Publication number: 20150077157
    Abstract: This disclosure relates generally to devices, systems, and methods that include conductive lines configured to transmit electrical signals between a first electronic component and a second electronic component between which the conductive lines are coupled. The devices, systems, and methods further include a transmitter, configured to generate the electrical signals, the transmitter including a source impedance based, at least in part, on a resistive coupling between individual ones of the conductive lines, a source impedance matrix of the source impedance being substantially proportional to the characteristic impedance matrix of the plurality of conductive lines.
    Type: Application
    Filed: September 19, 2013
    Publication date: March 19, 2015
    Inventor: Henning Braunisch
  • Patent number: 8981811
    Abstract: An integrated circuit memory device stores a plurality of digital values that specify respective termination impedances. The memory device switchably couples respective sets of load elements to a data input/output (I/O) to apply the termination impedances specified by the digital values, including, applying a first termination impedance to the data I/O during an idle state of the memory device, applying a first one of two non-equal termination impedances to the data I/O while the memory device receives write data in a memory write operation and applying a second one of the two non-equal termination impedances to the data I/O while another memory device receives write data in a memory write operation. When outputting read data via the data I/O in a memory read operation, the memory device switchably couples to the data I/O at least a portion of the load elements included in the sets of load elements.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: March 17, 2015
    Assignee: Rambus Inc.
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Patent number: 8970248
    Abstract: A termination network for a receiver device is provided to support both D-PHY signaling and N-factorial signaling. The first end of each of a plurality dynamically configurable switches is coupled to a common node. A first end of each of a plurality of resistances is coupled to a second end of a corresponding switch. A plurality of terminals receive differential signals and each terminal is coupled to a corresponding second end of a resistance. Each of a plurality differential receivers is coupled between two terminals of the termination network, wherein a first differential receiver and a second differential receiver are coupled to the same two terminals, the first differential receiver is used when the differential signals use a first type of differential signal encoding, the second differential receiver is used when the differential signals use a second type of differential signal encoding.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: March 3, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Shoichiro Sengoku, George Alan Wiley, Chulkyu Lee, Joseph Cheung
  • Patent number: 8963578
    Abstract: The present invention discloses a receiver capable of enhancing accuracy of signal reception. The receiver includes a variable termination resistance unit, coupled to at least one channel, for utilizing at least one termination resistance corresponding to the at least one channel to perform impedance matching, and a signal detection and termination resistance adjustment unit, for detecting at least one external calibration signal corresponding to the at least one channel from at least one external signal generator, and adjusting the at least one termination resistance.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: February 24, 2015
    Assignee: NOVATEK Microelectronics Corp.
    Inventor: Tse-Hung Wu
  • Patent number: 8963577
    Abstract: A termination impedance apparatus includes a variable pull-up resistor, a variable pull-down resistor, and a small-signal calibration circuit. The variable pull-up resistor is coupled between a first power supply voltage terminal and an output terminal. The variable pull-down resistor is coupled between the output terminal and a second power supply voltage terminal. The small-signal calibration circuit is for calibrating the variable pull-up resistor and the variable pull-down resistor to achieve a desired small-signal impedance.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: February 24, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Warren R. Anderson, Shyam S. Sivakumar, Austen J. Hypher
  • Patent number: 8957700
    Abstract: Apparatus and method for digital configuration of integrated circuits (ICs) are provided herein. In certain implementations, an IC includes an impedance sensing circuit and at least one pin used for digital configuration. The impedance sensing circuit can detect an impedance value of an external passive network electrically connected to the pin, and can digitally configure the IC based on the detected impedance. For example, an end-user can connect an external resistor of a particular resistance to the pin, and the impedance sensing circuit can sense or detect the external resistor's resistance and digitally configure the IC based on the detected resistance. Accordingly, an end-user can digitally configure the IC by connecting a passive external component corresponding to a desired digital configuration to the pin. In certain implementations, the IC includes multiple pins, and the digital configuration is based on the impedances detected on each of the pins.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: February 17, 2015
    Assignee: Analog Devices, Inc.
    Inventor: Reuben P. Nelson
  • Publication number: 20150042378
    Abstract: In a memory module having an integrated-circuit buffer device coupled to one or more integrated-circuit memory devices, the buffer device receives write data signals from an external control component via a set of data inputs, the write data signals indicating write data to be stored within one or more of the memory devices. Logic within the buffer device sequentially applies controllable termination impedance configurations at the data inputs based on an indication received from the control component and an internal state of the buffer device, applying a first controllable termination impedance configuration at each of the data inputs during a first internal state of the buffer device corresponding to the reception of the write data signals on the data inputs, and applying a second controllable termination impedance configuration at each of the data inputs during a second internal state of the buffer device that succeeds the first internal state.
    Type: Application
    Filed: October 26, 2014
    Publication date: February 12, 2015
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Publication number: 20150042379
    Abstract: A method for calibrating an output buffer including adjusting a first impedance code applied to a first plurality of first transistor units connected in parallel between a calibration terminal and a first power supply potential so that the potential on the calibration terminal substantially equals a reference potential, applying the first impedance code to a second plurality of first transistor units connected in parallel between a node and the first power supply potential, adjusting a second impedance code applied to a second transistor unit connected between the node and a second power supply potential so that the potential on the node substantially equals the reference potential, applying the first impedance code to a third plurality of first transistor units connected in parallel between a data terminal and the first power supply potential, and applying the second impedance code to a fourth plurality of second transistor units.
    Type: Application
    Filed: October 27, 2014
    Publication date: February 12, 2015
    Inventor: Kentaro Hara
  • Patent number: 8952718
    Abstract: A termination circuit for a plurality of memories controlled by a controller is provided. The termination circuit includes a plurality of drivers, a plurality of resistors and a plurality of capacitors. Each of the drivers is coupled to the memories via a transmission line. Each of the resistors is coupled to the corresponding driver via the corresponding transmission line. Each of the capacitors is coupled between the corresponding resistor and a reference voltage. The controller is coupled to the memories via the drivers, and the controller provides a specific code to one of the drivers when a quantity of logic “0” and a quantity of logic “1” transmitted to the memories via the transmission line corresponding to the one of the drivers are unbalanced, so as to adjust a termination voltage of the capacitor corresponding to the one of the drivers.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: February 10, 2015
    Assignee: Mediatek Inc.
    Inventors: Yan-Bin Luo, Sheng-Ming Chang, Bo-Wei Hsieh, Ming-Shi Liou, Chih-Chien Hung, Shang-Ping Chen