Abstract: A termination resistance adjustment circuit includes a replica circuit having the same characteristics as drive circuits; a current source being able to adjust the amount of a load current of the replica circuit; a voltage generation circuit to generate a plurality of reference voltages respectively corresponding to a plurality of values of the input data with the plurality of bits; a comparison circuit to compare an output voltage of the replica circuit with the reference voltages; and a control circuit to change the amount of the load current by controlling the current source, to calculate values of the output resistances of the replica circuit for each of the plurality of levels, and to adjust the number of use of the drive circuits for each bit of the input data, based on the calculated values of the output resistances for each of the plurality of levels.

Abstract: An integrated circuit may include a receiver suitable for comparing voltage levels of an external signal and a reference voltage with each other, and generating an internal signal, an adjustment code generation unit suitable for detecting a duty of the internal signal and generating an adjustment code of one or more bits, and a voltage adjustment unit suitable for adjusting the voltage level of the reference voltage in response to the adjustment code.

Abstract: A resistance calibration method for a first resistor of a first module includes performing resistance calibration on a calibration unit of a second module, wherein the first module is connected to the second module via a pad coupled to the first resistor and the calibration unit is coupled to the pad; obtaining a resistance value of the calibration unit after the resistance calibration; and calibrating a resistance value of the first resistor according to the resistance value of the calibration unit.

Abstract: System and method of automatically performing repeater insertions in physical design of an integrated circuit. Repeaters are inserted in interconnects in a staggered fashion and spaced apart to accommodate potential flip-flop insertions. The sufficient spacing between the repeaters in combination with the staggered pattern ensures that flip-flop insertions can be performed at any of the repeater locations without space limitation. When rerouting is needed following a flip-flop insertion on an interconnect, automatic rerouting is performed but restricted to a short and specified region along the interconnect. Thereby, the resulted alteration from the current routing configuration is minimal and deterministic.

Abstract: Described herein are a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory input-output (I/O) interface of a memory in response to a termination signal level. The method comprises: setting a first termination impedance value setting for a termination unit of an input-output (I/O) interface of a memory; assigning the first termination impedance value setting to the termination unit when the memory is not being accessed; and switching from the first termination impedance value setting to a second termination impedance value setting in response to a termination signal level.

Abstract: A buffer circuit may include an amplification unit and an active load unit. The amplification unit is electrically coupled to an output node and configured to sense and amplify first and second signals. The active load unit is configured to form a peak of a signal outputted from the output node when the signal transitions.

Abstract: A driver circuit for receiving input data and generating an output signal to a termination element is disclosed, wherein the input data has a first bit and second bit, and the driver circuit includes: a pair of differential output terminals, arranged for outputting the output signal, wherein the pair of differential output terminals has a first output terminal and a second output terminal; a current mode drive unit, coupled to the pair of differential output terminals, for outputting a current from one of the first output terminal and the second output terminal, and receiving the current from the other of the first output terminal and the second output terminal according to the first bit; and a voltage mode drive unit, coupled to the pair of differential output terminals, for providing voltages to the first output terminal and the second output terminal according to at least the second bit.

Abstract: A driver circuit for receiving input data and generating an output signal to a termination element is provided, wherein the input data has a first bit and second bit, and the driver circuit includes: a pair of differential output terminals for outputting the output signal, wherein the pair of differential output terminals has a first output terminal and a second output terminal; at least one current mode drive unit, coupled to the pair of differential output terminals, for outputting a current from one of the first output terminal and the second output terminal, and receiving the current from the other of the first output terminal and the second output terminal according to the first bit; and at least one voltage mode drive unit, coupled to the pair of differential output terminals, for providing voltages to the first output terminal and the second output terminal according to the second bit.

Abstract: A method of operating an input/output interface includes selecting one of a plurality of output driver circuits according to a mode selection signal, and outputting a data signal using the selected one of the plurality of output driver circuits. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an on-die termination (ODT) circuit included in the input/output interface according to the mode selection signal. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an ODT circuit included in the input/output interface according to the mode selection signal.

Abstract: The present invention provides a level conversion circuit. The circuit is as follows: A cathode of a first equivalent diode is connected to a reference voltage, and an anode of the first equivalent diode is separately connected to a gate of a first switching transistor and a first end of a first capacitor; a second end of the first switching transistor and a first end of a second switching transistor are connected together; a second end of the second capacitor is separately connected to a cathode of a second equivalent diode and a gate of the second switching transistor; and a second end of the second switching transistor is grounded, and an anode of the second equivalent diode is connected to a reference voltage.

Abstract: A method for determining the sensitivity of an analog output node of a mixed-signal module on a system on a chip (SoC) to noise coupling on the analog input nodes of the mixed-signal module includes (i) selecting an IP block for testing, (ii) selecting the output node, (iii) compiling a list of input nodes for testing, (iv) for each input node of the list, providing excitation signals at different frequencies, (v) for each provided excitation signal, determining the output node's noise sensitivity, and (vi) if any individual and/or cumulative noise sensitivity result exceeds a preset threshold, then modifying the SoC design to take corrective action.

Abstract: An operation control method of a semiconductor memory device includes executing a Delay Locked Loop (DLL) locking in response to a DLL reset signal and measuring a loop delay of a DLL. The operation control method further includes storing measured loop delay information and DLL locking information; and performing a delay control of a command path using the stored loop delay information and DLL locking information independent of the DLL, during a latency control operation.

Abstract: Techniques for trimming an on chip ZQ calibration resistor are disclosed. The on chip ZQ calibration resistor alleviates the need for an external ZQ calibration resistor. The on chip ZQ calibration resistor allows for a faster ZQ calibration. The trimming of on chip ZQ calibration resistor may be used to account for process variation. A correction mechanism may be used to account for temperature variation. Some of the circuitry that is used for ZQ calibration is also used for trimming the on-chip calibration resistor. This circuitry may include operational amplifiers, current mirrors, transistors, etc. The dual use of the circuitry can eliminate offset errors in an operational amplifier. The dual use can eliminate current mirror mismatch. Therefore, the trimming accuracy may be improved. The dual use also reduces the amount of circuitry that is needed for trimming the on chip ZQ calibration resistor. Thus, transistor count and chip size is reduced.

Abstract: A variable series resistance termination circuit for wireline serial link transceivers is provided. Some embodiments include a pad for coupling to a wireline serial link and a termination circuit. The termination circuit includes a plurality of resistive components coupled in series with the pad and a plurality of switches. Each switch is to couple one or more of the plurality of resistive components in series between the pad and a termination voltage node when the switch is closed. A subset of the plurality of switches can be selectively closed to establish a resistive component of an impedance of the termination circuit.

Abstract: A reference voltage generator including an electrostatic discharge (ESD) resistor, a first branch coupled to the ESD resistor and including a first capacitor, a second branch coupled to the ESD resistor and including a second capacitor, wherein the first and second capacitors are coupled in parallel, a first switch configured to control a first charge transfer path leading to the first branch, and a second switch configured to control a second charge transfer path leading to the second branch.

Abstract: A system for power transfer is provided. In one exemplary embodiment, the system includes an inductive power device, such as a device that transmits or receives power over an inductive coupling. For example, an adjustable impedance is coupled to the inductive power device, where the adjustable impedance is used for dynamically controlling the power gain in the inductive power device, such as by damping power generated by circuit impedances, such as inductances, capacitances or resistances, and combinations thereof.

Abstract: An embodiment may include a first replica driver group configured for replicating an output driver of a physical area. A second replica driver group configured for replicating an output driver of a test electrode area for direct access of a memory, and an impedance calibration unit configured to independently perform an impedance matching operation of the first replica driver group and the second replica driver group.

Abstract: The single removable cable is capable of transporting both the power and the data between a powering device and one or more powered devices. At least one signal line is configured to transport data over the single removable cable. At least one electrical conductor configured to transport power for operating the one or more powered devices.

Abstract: Embodiments are generally directed to smart impedance matching for high-speed I/O. In some embodiments, a circuit includes an impedance sensing block; a finite state machine to provide impedance tuning for a driver; and a control block, the control block to provide a feedback loop to check and tune impedance of the driver. The impedance sensing block is to sample an output voltage of the driver to determine whether the impedance of the driver is greater than or less than an impedance of the channel; and the finite state machine is to produce a signal to decrease or increase the impedance of the driver based on the determination whether the impedance of the driver is greater than or less than the impedance of the channel.

Abstract: Impedance matching circuitry is positioned on a signal line intermediate the terminals of the signal line in an integrated circuit. The impedance matching circuitry can include discrete components off the integrated circuit and on a substrate, e.g., a board. The impedance matching circuitry can operate to match the impedance of a signal line in the integrated circuit, e.g., a memory device such as a DRAM or DDR DRAM.

Abstract: A memory controller comprises a connection interface connected or connectable to a memory. The memory controller is arranged to read data from the memory via the connection interface. The memory controller further comprises a clock unit arranged to provide a data transfer clock signal having a first frequency. The data transfer clock signal may be provided to the memory via the connection interface. The data transfer clock signal is arranged for clocking a data transfer from the memory to the memory controller via the connection interface as well as an oversampling circuit arranged to sample a calibration data pattern read by the memory controller via the connection interface at a second frequency to provide an over-sampled calibration data pattern. The second frequency is larger than the first frequency. The memory controller is arranged to determine a timing shift of a data transfer from the memory to the memory controller based on the oversampled calibration data pattern.

Abstract: A semiconductor device includes a receiver configured to receive a reference voltage via a first input terminal, receive an input signal via a second input terminal, and generate an output signal by comparing the reference voltage to the input signal with each other. A termination circuit associated with the input signal terminal may be adjusted and a logic threshold voltage may be adjusted to accommodate the adjustment in the termination circuit.

Abstract: Embodiments include apparatuses, methods, and systems for transmitting a data signal over one or more transmission lines. In one embodiment, a transmitter circuit includes a plurality of programmable impedance driver (PID) circuits coupled in parallel with one another to drive a data signal on a transmission line. The individual PID circuits may include a pull-up transistor to receive a pull-up signal, a pull-down transistor to receive a pull-down signal, and first and second resistors coupled in series with one another between the pull-up and pull-down transistors. An output contact may be coupled to a node between the first and second resistors to pass an output signal that is responsive to the pull-up and pull-down signals.

Abstract: Apparatuses for interconnecting integrated circuit dies. A first set of single-ended transmitter circuits are included on a first die. The transmitter circuits are impedance matched and have no equalization. A first set of single-ended receiver circuits are included on a second die. The receiver circuits have no termination and no equalization. Conductive lines are coupled between the first set of transmitter circuits and the first set of receiver circuits. The lengths of the conductive lines are matched. The first die, the first set of single-ended transmitter circuits, the second die, the first set of single ended receiver circuits and the conductive lines are disposed within a first package. A second set of single-ended transmitter circuits are included on the first die. The transmitter circuits are impedance matched and have no equalization. Data transmitted from the second set of transmitter circuits is transmitted according to a data bus inversion (DBI) scheme.

Abstract: An integrated circuit which includes a pre-driver configured to receive a first high supply voltage and to generate an input signal and at least one post-driver configured to receive at least one second high supply voltage and to receive the input signal. The at least one post-driver includes an input node configured to receive the input signal and an output node configured to output an output signal. The at least one post-driver further includes a pull-up transistor configured to be in a conductive state during an entire period of operation, and a pull-down transistor. The at least one post-driver further includes at least one diode-connected device coupled between the pull-down transistor and the output node. Each post-driver of the at least one post-driver is configured to supply the output signal having a second voltage level corresponding to a high logic level which is higher than an input voltage level.

Abstract: A semiconductor system may include first semiconductor device including a first pad, a second pad and a first test input pad, and suitable for storing data inputted in series through the first test input pad and outputting the stored data in parallel through the first pad and the second pad; a second semiconductor device including a third pad, a fourth pad and a second test output pad, and suitable for storing data inputted in parallel through the third pad and the fourth pad, a first through via connecting the first pad and the third pad so that the stored data outputted in parallel through the first pad is inputted in parallel through the third pad; and a second through via connecting the second pad and the fourth pad so that the stored data outputted in parallel through the second pad is inputted in parallel through the fourth pad.

Abstract: A power supply controller is provided for providing a drive current to a control terminal of a power transistor in three time intervals. The controller includes control circuits configured to control the drive current in multiple stages. During a first time interval, first drive current includes a current spike for turning on the power transistor in response to a start of the control signal pulse. During a second time interval, a second drive current includes a ramping current substantially proportional to a magnitude of a current through the power transistor. During a third time interval, current flow to the power transistor is at least partially turned off before an end of the control signal pulse.

Abstract: A semiconductor device may include a termination resistor circuit including a first termination resistor connected to a power voltage and a second termination resistor between the first termination resistor and a ground, a value of the first termination resistor and the second termination resistor changes based on a feedback signal; a mismatch detector may generate a compared result based on a potential difference between a voltage of a center node, between the first and second termination resistors, and a reference voltage; a code generator may generate the feedback signal based on the compared result, and generate a feedback code based on the compared result; a code register may generate a mismatch code controlling a mismatch between the first and second termination resistors based on the feedback code; and a corrector may compensate for the mismatch between the first and second termination resistors based on the mismatch code.

Abstract: A driving circuit used in a transmission line includes an operational amplifier and an output circuit. The operational amplifier is used for receiving a voltage signal to generate an output. The output circuit is coupled to the operational amplifier and used for receiving the output of the operational amplifier and determining current(s) passing through the output circuit to generate an output signal of the driving signal so as to adjust the output impedance of the driving circuit to match the transmission line; the output impedance of driving circuit is adjustable and determined by the current(s) passing through the output circuit.

Abstract: Aspects disclosed in the detailed description include apparatuses, methods, and systems for glitch-free clock switching. In this regard, in one aspect, an electronic circuit is switched from a lower-frequency reference clock to a higher-frequency reference clock. An oscillation detection logic is configured to determine the stability of the higher-frequency reference clock prior to switching the electronic circuit to the higher-frequency reference clock. The oscillation detection logic derives a sampled clock signal from the higher-frequency reference clock, wherein the sampled clock signal has a slower frequency than the lower-frequency reference clock. The oscillation detection logic then compares the sampled clock signal against the lower-frequency reference clock to determine the stability of the higher-frequency reference clock.

Abstract: Internal voltage generation circuits are provided. The internal voltage generation circuit includes a code signal generator and an internal voltage generator. The code signal generator generates input code signals having a logic level combination corresponding to a difference between a frequency of an external clock signal and a frequency of an internal clock signal. The internal voltage generator is selectively activated according to the logic level combination of the input code signals to drive an internal voltage signal.

Abstract: A bus driver circuit may include a first and a second circuit node, wherein the first circuit node is operably coupled to a bus line, which causes a bus capacitance between the first and the second circuit node. A switching circuit is coupled to the first circuit node and configured to apply an output voltage between the first and the second circuit node. Thereby the bus capacitance is charged when a control signal indicates a dominant state. A discharge circuit comprises at least one resistor. The discharge circuit is coupled between the first and the second circuit node and configured to allow the bus capacitance to discharge via the resistor when the control signal indicates a recessive state. The switching circuit is further configured to provide a temporary current path for discharging the bus capacitance during a transition period from a dominant to a recessive state.

Abstract: A data transmitter may include a transmitter circuit and a calibration controller. The transmitter circuit is configured to be coupled to a receiver through a channel, and configured to provide an output signal to the channel based on an input signal and adjust an output impedance value according to a bias signal. The calibration controller is configured to adjust the bias signal by comparing the output signal of the transmitter circuit to a reference signal during a calibration operation.

Abstract: An integrated circuit with on-chip termination (OCT) circuitry is provided. In particular, the integrated circuit may include an input-output (IO) buffer, an OCT circuit coupled between the IO buffer and a physical IO interface, and adaptive external OCT calibration circuitry for impedance matching the IO buffer to a transmission line that is coupled to the IO buffer. The adaptive external OCT calibration circuitry may include a waveform measurement circuit for selectively sampling a waveform at the IO interface, and a waveform analyzer and control circuit for analyzing the sampled waveform and adjusting the OCT circuit until the impedance provided by the OCT circuit matches with the external impedance of the transmission line. A switch that is interposed between the OCT circuit and the measurement module may be enabled during calibration and disabled during normal device operation.

Abstract: A semiconductor memory apparatus may include a memory cell array. The semiconductor memory apparatus may include an impedance calibration circuit configured to perform an impedance matching operation by generating an impedance code based on a voltage of an interface node determined by an external reference resistor or an internal reference resistor unit according to whether or not to the external reference resistor is coupled to the impedance calibration circuit. The semiconductor memory apparatus may include a data input/output (I/O) driver configured to receive input data from the memory cell array and generate output data in response to the impedance code.

Abstract: Disclosed here is an apparatus that comprises a data terminal, a data output circuit including a plurality of output buffers coupled in common to the data terminal, and an impedance control circuit coupled to the data output circuit, wherein the impedance control circuit is configured to generate first impedance code and second impedance code different from the first impedance code and to apply a selected one of the first impedance code and the second impedance code to at least one of the output buffers.

Abstract: A data transmission circuit may include first, second, and third pads, generate a pull-up code and a pull-down code in accordance with a resistance value between the third pad and a ground terminal, and drive data with drivability adjustable by the pull-up code and the pull-down code to output the data. The data reception circuit may include a resistor coupling circuit coupled between the first pad and the second pad to include a second resistance value, include an external resistor coupled to the third pad through a first wiring resistor having a first resistance value, and receive the data through a second wiring resistor.

Abstract: A full-duplex transceiver circuit comprises: a line driver configured to output a first current to a first node and a second current to a second node; a first resistor configured to shunt the first node to ground; a second resistor configured to shunt the second node to ground; a first capacitor configured to couple the first node to a third node; a second capacitor configured to couple the second node to the third node; an operational amplifier configured to receive a first input from a reference node and a second input from the third node and output an output voltage at a fourth node; a feedback network comprising a parallel connection of a third resistor and a third capacitor configured to provide a feedback from the fourth node to the third node; and a transmission line of a characteristic impedance configured to couple the first node to a remote transceiver.

Abstract: A method for performing signal driving control in an electronic device and an associated apparatus are provided. The method includes: generating a first driving control signal and a second driving control signal according to a data signal, wherein the second driving control signal transits in response to a transition of the data signal, and the first driving control signal includes a pulse corresponding to the transition of the data signal; and utilizing a first switching unit to control a first signal path between a first voltage level and an output terminal of an output stage according to the first driving control signal, and utilizing a second switching unit to control a second signal path between the first voltage level and the output terminal according to the second driving control signal, wherein a first impedance of the first signal path is less than a second impedance of the second signal path.

Abstract: Embodiments disclosed herein include an I/O module with multiple level shifters that establish a plurality of voltage domains. Using the level shifters, the I/O module converts data signals in a core logic voltage domain to data signals in an external voltage domain. In one embodiment, when transmitting data signals to an external device, the I/O module level shifts the data signals from a core logic voltage domain to a low voltage domain. The I/O module then level shifts the data signals from the low voltage domain to an intermediate voltage domain. The I/O module may further shift the data signals from the intermediate voltage domain to both a low voltage domain and a high voltage domain. Using the data signals from both of these domains, the I/O module outputs the data signals in a voltage domain corresponding to a communication technique used to transmit data to the external device.

Abstract: A semiconductor system includes a first semiconductor device including an offset signal generation circuit configured to compare at least one sensing code and a temperature code and generate an input offset signal, and a second semiconductor device including a temperature code generation circuit configured to be inputted with the input offset signal, compare a reference voltage controlled according to the input offset signal and a temperature signal, and generate the temperature code.

Abstract: A driver for semiconductor memory, comprising: a storage unit configured to match and store a memory cell address and bucket charge current data corresponding to the memory cell address; a selection controller configured to receive the memory cell address and a target charge current data, and output a bucket charge current select signal and a target charge current select signal corresponding to the bucket charge current data and the target charge current data, respectively, by referring to the storage unit; and a current supply unit configured to supply a bucket charge current and a target charge current in response to the bucket charge current select signal and the target charge current select signal, respectively.

Abstract: An amplifier topology achieves enhances DC gain to improve linearity while maintaining a good signal to noise ratio. The amplifier includes an amplifier output stage that supplies an amplifier output signal. The amplifier also includes a sense amplifier that augments the output stage. The sense amplifier is coupled to the amplifier input to control current through the output stage in order to achieve reduced voltage variation at the amplifier input as a function of the amplifier output signal voltage as compared to a basic common source amplifier and thereby enhances DC gain of the amplifier.

Abstract: In one embodiment, a receiver comprises a differential common-gate amplifier having a differential input and a differential output, wherein the differential input comprises a first input and a second input, and the differential common-gate amplifier is configured to amplify an input differential signal at the differential input into an amplified differential signal at the differential output. The receiver also comprises a common-mode voltage sensor configured to sense a common-mode voltage of the input differential signal, a replica circuit configured to generate a replica voltage that tracks a direct current (DC) voltage at at least one of the first and second inputs, and a comparator configured to compare the sensed common-mode voltage with the replica voltage, and to adjust a first bias voltage input to the differential common-gate amplifier based on the comparison, wherein the DC voltage depends on the first bias voltage.

Abstract: A parallel test device and method are disclosed, which relates to a technology for performing a multi-bit parallel test by compressing data. The parallel test device includes: a pad unit through which data input/output (I/O) operations are achieved; a plurality of input buffers configured to activate write data received from the pad unit in response to a buffer enable signal, and output the write data to a global input/output (GIO) line; a plurality of output drivers configured to activate read data received from the global I/O (GIO) line in response to a strobe delay signal, and output the read data to the pad unit; and a test controller configured to activate the buffer enable signal and the strobe delay signal during a test mode in a manner that the read data received from the plurality of output drivers is applied to the plurality of input buffers such that the read data is operated as the write data.

Abstract: An output driver is provided that adapts an output impedance of the output driver to the voltage level of a power supply, thereby providing a constant output impedance over a range of different operating voltages. The output driver includes a plurality of individual driver circuits, each one of the plurality of individual driver circuits configured to provide a plurality of predetermined output impedances in response to a plurality of power supply voltage level inputs and a decoder.

Abstract: An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting.

Abstract: A memory module includes a command/address (CA) register, memory devices, and a module resistor unit mounted on a circuit board. The centrally disposed CA register drive the memory devices one or more internal CA signal(s) to arrangements of memory devices using multiple CA transmission lines, wherein the multiple internal CA transmission lines are commonly terminated in the module resistor unit.

Abstract: A circuit may include first and second input nodes, first and second output nodes, first and second intermediate nodes, first and second resistances, a first amplification transistor coupled to the first input node, the first resistance, and the first intermediate node and a second amplification transistor coupled to the second input node, the second resistance, and the second intermediate node. The circuit may also include a first active device coupled to the first output node and the first intermediate node, a second active device coupled to the second output node and the second intermediate node, a first output transistor coupled to the first output node and configured to conduct based on a second intermediate signal on the second intermediate node, and a second output transistor coupled to the second output node and configured to conduct based on a first intermediate signal on the first intermediate node.

Abstract: In a power supply impedance optimizing apparatus, first and second noise detecting circuits detect noises of first and second power supplies by magnetic field coupling between bonding wires of the first and second power supplies and bonding wires for first and second noise detection. A noise determining circuit determines a noise level using a frequency component in each of one or more frequency ranges as extracted from each of the noises of the first and second power supplies. The noise determining circuit controls ON/OFF state of the first switch connected between pads of the first and second power supplies and the second switch connected between pins of the first and second power supplies based on a determination result of the noise level.