Having Details Of Setting Or Programming Of Interconnections Or Logic Functions Patents (Class 326/38)
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Patent number: 10536124Abstract: A power stage includes a power stage amplifier, selectable matching networks, and phase-change material (PCM) radio frequency (RF) switches. Each of the PCM RF switches includes a heating element transverse to a PCM, the heating element approximately defining an active segment of the PCM. A power stage amplifier output is connected to the PCM RF switches. Each of the PCM RF switches is connected to one of the selectable matching networks. A power stage amplifier output is coupled to or decoupled from one of the selectable matching networks by one of the PCM RF switches. In one approach, the power stage is included in a power amplifier module of a communications device. The power amplifier module further includes a bias and match controller that biases the power stage amplifier, and that uses one of the PCM RF switches to couple or decouple the power stage amplifier output.Type: GrantFiled: May 21, 2019Date of Patent: January 14, 2020Assignee: Newport Fab, LLCInventors: Chris Masse, Nabil El-Hinnawy, Gregory P. Slovin, David J. Howard
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Patent number: 10534836Abstract: A method to add a first one bit variable with a second one bit variable and a carry-in bit, to generate a sum bit and a carry-out bit, the method includes initiating the sum bit to the value of the second one bit variable, initiating the carry-out bit to a value of the carry-in bit and modifying the sum bit and the carry-out bit if a comparison of a sequence of the first one bit variable, the second one bit variable and an inverse value of the carry-in bit matches one of a predefined set of a change trigger sequences.Type: GrantFiled: September 19, 2017Date of Patent: January 14, 2020Assignee: GSI Technology Inc.Inventors: LeeLean Shu, Avidan Akerib
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Patent number: 10536139Abstract: A power-gate circuit includes a power-gate transistor operable to switch to decouple a first supply voltage from a second supply voltage during an idle mode, and to couple the first supply voltage to the second supply voltage during a full operational mode. Part of the charge stored at a gate terminal of the power-gate transistor, would have been otherwise flushed to ground while turning on the power-gate transistor, is routed to the rail of the second supply voltage of the logic block. Part of the charge on the rail of the second supply voltage is used to charge the gate terminal of the power-gate transistor to deactivate the power-gate transistor if the logic block goes to the idle mode. Energy is saved both ways because of the charge recycling and the ability to use the power-gate circuit even in cases where the duration of the idle mode may be short.Type: GrantFiled: April 20, 2018Date of Patent: January 14, 2020Assignee: Intel CorporationInventors: Shai Rotem, Norbert Unger, Michael Zelikson
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Patent number: 10530386Abstract: A digital sigma-delta modulator may be provided that includes: a multiplexer which receives N-bit input data from each of M number of input terminals and sequentially outputs; an adder which outputs carry out (CO) data and N-bit added data obtained by adding the N-bit input data and N-bit added data output in a previous cycle; a memory which divides the N-bit added data output from the adder into A-bit added data and (N?A)-bit added data and stores the A-bit added data and the (N?A)-bit added data; and a demultiplexer which receives the output carry out (CO) data and outputs to each of M number of output terminals.Type: GrantFiled: June 8, 2018Date of Patent: January 7, 2020Assignee: RAONTECH, Inc.Inventors: Je-Kwang Cho, Min Seok Kim
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Patent number: 10523209Abstract: An integrated circuit comprising a plurality of logic tiles, wherein, during operation, each logic tile is configurable to connect with at least one other logic tile, and wherein each logic tile includes: (1) a normal operating mode, (2) a test mode, (3) an interconnect network including a plurality of multiplexers, wherein during operation, the interconnect network of each logic tile is configurable to electrically connect with the interconnect network of at least one adjacent logic tile of the plurality of logic tiles via one or more tile-to-tile interconnects in the normal operating mode and (4) isolation circuitry, connected between the associated interconnect network and the interconnect network of each adjacent logic tile, configurable to responsively disconnect tile-to-tile interconnects disposed between the interconnect network of each adjacent logic tile in the test mode to thereby electrically disconnect interconnect networks of adjacent logic tiles in the test mode.Type: GrantFiled: November 12, 2018Date of Patent: December 31, 2019Assignee: Flex Logix Technologies, Inc.Inventor: Cheng C. Wang
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Patent number: 10523207Abstract: Systems and methods relating to a programmable circuit. The programmable circuit includes multiple sectors. Each sector includes configurable functional blocks, configurable routing wires, configuration bits for storing configurations for the functional blocks and routing wires, and local control circuitry for interfacing with the configuration bits to configure the sector. The programmable circuit may include global control circuitry for interfacing with the local control circuitry to configure the sector. Each sector may be independently operable and/or operable in parallel with other sectors. Operating the programmable circuit may include using the local control circuitry to interface with the configurations bit and configure the sector. Additionally, operating the programmable circuit may include using the global control circuitry to interface with respective local control circuitry and configure the sector.Type: GrantFiled: August 15, 2014Date of Patent: December 31, 2019Assignee: Altera CorporationInventors: Dana How, Sean R. Atsatt, Michael David Hutton, Herman Henry Schmit
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Patent number: 10509757Abstract: Integrated circuits may have programmable logic circuitry and hard-coded circuitry. The hard-coded circuitry may include data circuitry, a processor, and memory. As the hard-coded circuitry has a limited capacity, a portion of the programmable logic circuitry may be configured using configuration data to serve as expanded soft-coded memory for the hard-coded processor. Instructions for controlling settings of the data circuitry may be stored on the hard-coded and soft-coded memory. An additional portion of the programmable logic circuitry may be configured using the configuration data to serve as a soft-coded processor that executes the instructions stored on the soft-coded memory. Use of the soft-coded processor and/or expanded soft-coded memory may allow for more advanced algorithms for initialization and calibration of the data circuitry than when only hard-coded memory is used and may allow for updated processor circuitry to be implemented.Type: GrantFiled: September 22, 2016Date of Patent: December 17, 2019Assignee: Altera CorporationInventors: Paul Kim, Alfredo de la Cruz, Gary Brian Wallichs, Yi Peng
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Patent number: 10509995Abstract: A state machine engine having a program buffer. The program buffer is configured to receive configuration data via a bus interface for configuring a state machine lattice. The state machine engine also includes a repair map buffer configured to provide repair map data to an external device via the bus interface. The state machine lattice includes multiple programmable elements. Each programmable element includes multiple memory cells configured to analyze data and to output a result of the analysis.Type: GrantFiled: April 4, 2016Date of Patent: December 17, 2019Assignee: Micron Technology, Inc.Inventors: Harold B Noyes, David R. Brown
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Patent number: 10498341Abstract: Sparse representation of information performs powerful feature extraction on high-dimensional data and is of interest for applications in signal processing, machine vision, object recognition, and neurobiology. Sparse coding is a mechanism by which biological neural systems can efficiently process complex sensory data while consuming very little power. Sparse coding algorithms in a bio-inspired approach can be implemented in a crossbar array of memristors (resistive memory devices). This network enables efficient implementation of pattern matching and lateral neuron inhibition, allowing input data to be sparsely encoded using neuron activities and stored dictionary elements. The reconstructed input can be obtained by performing a backward pass through the same crossbar matrix using the neuron activity vector as input. Different dictionary sets can be trained and stored in the same system, depending on the nature of the input signals.Type: GrantFiled: December 28, 2018Date of Patent: December 3, 2019Assignee: The Regents of the University of MichiganInventors: Wei Lu, Fuxi Cai, Patrick Sheridan, Chao Du
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Patent number: 10496580Abstract: In one or more embodiments, one or more systems, methods, and/or systems may provide an output signal via a first port of multiple ports; may determine that the output signal is detected via a second port of the multiple ports; if the first port and the second port are not capable of being coupled, may provide a notification that indicates that the first port and the second port are not capable of being coupled; and if the first port and the second port are capable of being coupled: may configure a Serializer/Deserializer (SerDes) associated with the first port to communicate with a SerDes associated with the second port; and may configure a first processor of multiple processors to communicate with a second processor of the multiple processors via the SerDes associated with the first port.Type: GrantFiled: August 2, 2018Date of Patent: December 3, 2019Assignee: Dell Products L.P.Inventors: Timothy M. Lambert, Jordan H. Chin, Jeffrey Leighton Kennedy
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Patent number: 10482208Abstract: The present invention provides theoretical bases and practical schematic diagrams for a state machine which is coded in HDL and synthesized to generate a circuit that comprises one or more state groups each of which has an independent clock gating device. A state group will receive a clock pulse on the next cycle when either a synchronous initialization input signal for a state machine is asserted on the current cycle or the state group will change states on the next cycle, reducing power consumption and simplifying the final logic, compared with a traditionally generated state machine circuit. In addition the invention also provides a code designer with a proposed method for HDL standard on how to divide all states in a state machine into state groups at his discretion.Type: GrantFiled: December 31, 2018Date of Patent: November 19, 2019Inventor: Tianxiang Weng
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Patent number: 10474427Abstract: There is provided an apparatus and method for comparing wide data types. The apparatus comprises processing circuitry to perform a plurality of comparison operations in order to compare a first value and a second value, each of the first value and the second value having a length greater than N bits, and each comparison operation operating on a corresponding N bits of the first and second values. The plurality of comparison operations are chained to form a sequence such that each comparison operation is arranged to output an accumulated comparison result incorporating the comparison results of any previous comparison operations in the sequence, and such that for each comparison operation other than a final comparison operation in the sequence the accumulated comparison result is provided for use as an input by a next comparison operation in the sequence.Type: GrantFiled: May 25, 2016Date of Patent: November 12, 2019Assignee: ARM LimitedInventor: Jørn Nystad
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Patent number: 10474390Abstract: A circuit includes a memory and an address generator configured to generate a write address signal and a read address signal, where the write address signal has a first delay relative to the read address signal. The memory is configured to receive a first plurality of write addresses, from the write address signal, including a first plurality of addresses of the memory in a first order, and write, to the first plurality of write addresses, a first plurality of data words during a first time period. The memory is further configured to receive a first plurality of read addresses, from the read address signal, including the first plurality of addresses in a second order, and read, from the first plurality of read addresses, the first plurality of data words during a second time period. The first and second time periods partially overlap.Type: GrantFiled: May 4, 2017Date of Patent: November 12, 2019Assignee: XILINX, INC.Inventor: Andrew M. Whyte
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Patent number: 10468084Abstract: The present disclosure relates to a structure including a memory array circuit with a magnetic tunnel junction array and an inverter between at least two data magnetic tunnel junctions and configured to enable logic-in-memory computations.Type: GrantFiled: April 3, 2018Date of Patent: November 5, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Akhilesh R. Jaiswal, Ajey Poovannummoottil Jacob
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Patent number: 10456800Abstract: To implement a complex math function, i.e. a math function with multiple input variables, a configurable computing array comprises at least an array of configurable computing elements. Each configurable computing element comprises at least a memory which stores a look-up table (LUT) for a math function with a single input variable.Type: GrantFiled: September 5, 2018Date of Patent: October 29, 2019Assignees: HangZhou HaiCun Information Technology Co., Ltd.Inventor: Guobiao Zhang
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Patent number: 10453106Abstract: The invention provides systems and methods for maximizing revenue generating throughput of a multi-user parallel data processing platform across a set of users of the service provided with the platform. The invented techniques, for any given user contract among the contracts supported by the platform, and on any given billing assessment period, determine a level of a demand for the capacity of the platform associated with the given contract that is met by a level of access to the capacity of the platform allocated to the given contract, and assess billables for the given contract at least in part based on such met demand and a level of assured access to the capacity of the platform associated with the given contract, as well as billing rates, applicable for the given billing assessment period, for the met demand and the level of assured access associated with the given contract.Type: GrantFiled: October 23, 2014Date of Patent: October 22, 2019Assignee: THROUGHPUTER, INC.Inventor: Mark Henrik Sandstrom
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Patent number: 10453533Abstract: Memory device having a tile architecture are disclosed. The memory device may include a first plane having multiple pairs of tiles, wherein at least some of the pairs of tiles of the first plane include a distributed block select circuit and page buffer circuitry. Another memory device may include a memory array, and a CMOS under array region. At least some tile regions may include portions of a total amount of block select circuitry distributed throughout the CUA region, vertical string drivers located outside of the memory array, and page buffer circuitry coupled with the memory array. Another memory device may include a first tile pair including a first tile, a second tile, a first vertical string driver therebetween, a first page buffer region that is greater than 50% of area for the first tile pair, and a first portion of a distributed block select circuitry.Type: GrantFiled: November 17, 2017Date of Patent: October 22, 2019Assignee: Micron Technology, Inc.Inventor: Eric N. Lee
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Patent number: 10453543Abstract: Disclosed in some examples are methods, systems, memory devices, machine readable mediums configured to intentionally degrade NAND performance when a value of a NAND health metric indicates a potential for failure to encourage users to replace or backup their devices before data loss occurs. For example, the system may track a NAND health metric and when that metric reaches a predetermined threshold or state, the system may intentionally degrade performance. This performance degradation may be more effective than a warning to effect device backup or replacement.Type: GrantFiled: October 31, 2017Date of Patent: October 22, 2019Assignee: Micron Technology, Inc.Inventor: Sebastien Andre Jean
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Patent number: 10447276Abstract: A power management integrated circuit (PMIC) includes: a plurality of high voltage power field effect transistors (FETs); and a programmable fabric configured to programmably connect one or more of the plurality of high voltage power FETs to provide one or more high power voltage outputs. The plurality of high voltage power FETs and the programmable fabric are integrated in a single chip.Type: GrantFiled: October 27, 2016Date of Patent: October 15, 2019Assignee: AnDAPT, Inc.Inventors: Kapil Shankar, Thomas Chan, Patrick J. Crotty, John Birkner
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Patent number: 10445457Abstract: Disclosed are techniques for implementing a physical design of an electronic design with design for manufacturing DFM and design specification awareness. These techniques identify one or more design specifications for generating a floorplan or a placement layout of an electronic design. Floorplanning or placement requirements are determined based in part or in whole upon pertinent electrical parasitics. The floorplan or the placement layout is generated at least by inserting a set of blocks based in part or in whole upon the floorplanning or placement requirements.Type: GrantFiled: June 30, 2016Date of Patent: October 15, 2019Assignee: Cadence Design Systems, Inc.Inventor: Kwang-Tatt Loo
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Patent number: 10447463Abstract: An ultra-low latency communication device includes a clock recovery module, a de-serializer module, an FPGA fabric and a serializer module. The clock recovery module receives an incoming electrical physical layer serial signal and recovers a recovered clock signal therefrom. The de-serializer module converts the incoming electrical physical layer serial signal to an incoming electrical physical layer parallel signal according to driving signals generated based on the recovered clock signal. The FPGA fabric processes the incoming electrical physical layer parallel signal to output an incoming data-link layer parallel signal, receives an outgoing data-link layer parallel signal generated based on electronic information contained in the incoming data-link layer parallel signal, and processes the outgoing data-link layer parallel signal to output an outgoing electrical physical layer parallel signal.Type: GrantFiled: July 13, 2018Date of Patent: October 15, 2019Assignee: ORTHOGONE TECHNOLOGIES INC.Inventor: Alexandre Raymond
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Patent number: 10446747Abstract: A method can include, by operation of a controller circuit, writing data into a volatile memory portion formed in an integrated circuit substrate of a memory device. In response to first conditions, date can be written from the volatile memory portion into a nonvolatile memory portion formed in the same integrated circuit substrate as the volatile memory portion. The nonvolatile memory portion can store the data in two terminal memory elements re-programmable between at least two different resistance states.Type: GrantFiled: August 31, 2017Date of Patent: October 15, 2019Assignee: Adesto Technology CorporationInventors: Narbeh Derhacobian, Shane Charles Hollmer
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Patent number: 10447273Abstract: A method for allocating field-programmable gate array (FPGA) resources includes monitoring a first operating metric for one or more computing devices, identifying a first portion of plurality of macro components of a set of one or more FPGA devices in the one or more computing devices, where the first portion is allocated for implementing one or more user defined functions. The method also includes, in response to a first change in the first operating metric, reallocating the first portion of the macro components for implementing a system function associated with the first operating metric, and generating a first notification indicating the reallocation of the first portion.Type: GrantFiled: September 11, 2018Date of Patent: October 15, 2019Assignee: Advanced Micro Devices, Inc.Inventors: David A. Roberts, Shenghsun Cho
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Patent number: 10438670Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.Type: GrantFiled: June 15, 2018Date of Patent: October 8, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shinya Okuno, Shigeki Nagasaka, Toshiyuki Kouchi
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Patent number: 10431317Abstract: A memory system comprising: a memory cell. The memory cell comprising a poly-fuse-resistor; and a bipolar junction transistor having a collector-emitter channel and a base-terminal. The collector-emitter channel of the bipolar junction transistor is connected in series with the poly-fuse resistor between a supply-voltage-terminal and a ground-terminal. The base-terminal of the bipolar junction transistor is configured to receive a transistor-control-signal to selectively control a current flow through the poly-fuse-resistor.Type: GrantFiled: March 1, 2018Date of Patent: October 1, 2019Assignee: NXP B.V.Inventor: Antonius Martinus Jacobus Daanen
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Patent number: 10431294Abstract: Devices and methods include utilizing memory including a group of storage elements, such as memory banks. A command interface is configured to receive a write command to write data to the memory. A data strobe is received to assist in writing the data to the memory. Phase division circuitry is configured to divide the data strobe into a plurality of phases to be used in writing the data to the memory. Arbiter circuitry is configured to detect which phase of the plurality of phases captures a write start signal for the write command.Type: GrantFiled: July 31, 2018Date of Patent: October 1, 2019Assignee: Micron Technology, Inc.Inventor: Daniel B. Penney
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Patent number: 10423552Abstract: A data structure is accessed that defines configuration parameters of one or more integrated blocks in an integrated circuit device. One or more of the integrated blocks is configured based on corresponding configuration parameters defined in the data structure. The configuration parameters are set prior to runtime and are to be persistently stored in the data structure.Type: GrantFiled: December 23, 2013Date of Patent: September 24, 2019Assignee: Intel CorporationInventor: David J. Harriman
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Patent number: 10419000Abstract: A Look Up Table (LUT) includes a data storage circuit including a plurality of nonvolatile memory elements respectively corresponding to a plurality of applications, the data storage circuit being configured to select one of the plurality of nonvolatile memory elements according to an application selection signal; an amplification circuit configured to amplify a signal output from the selected nonvolatile memory element according to an enable signal output from a decoder; and a write control circuit configured to program the selected nonvolatile memory element with information corresponding to a data signal according to a write signal.Type: GrantFiled: August 21, 2018Date of Patent: September 17, 2019Assignees: SK HYNIX INC., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITYInventors: Jeongbin Kim, Kitae Kim, Kyungseon Cho, Seungjin Lee, Daehyung Cho, Eui-Young Chung, Hongil Yoon
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Patent number: 10418995Abstract: A reconfigurable circuit suitable for a redundant circuit of a storage device is provided. A programmable logic element (PLE) includes k logic circuits (e.g., XNOR circuits), k configuration memories (CM), and another logic circuit (e.g., an AND circuit) to which the outputs of the k logic circuits are input. The output of the AND circuit represents whether k input data of the PLE all correspond to configuration data stored in the k CMs. For example, when the address of a defective block in the storage device is stored in the CM and address data of the storage device the access of which is requested is input to the PLE, whether the defective block is accessible can be determined from the output of the AND circuit.Type: GrantFiled: November 28, 2016Date of Patent: September 17, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Yoshiyuki Kurokawa
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Patent number: 10417078Abstract: Various techniques are provided to efficiently implement deterministic read back and error detection for programmable logic devices (PLDs). In one example, a PLD includes an array of memory cells arranged in rows and columns, where at least one row includes an enable bit. The PLD further includes an address logic circuit configured to selectively assert the columns of the array by respective address lines. The PLD further includes a register configured to store a value of the enable bit in response to an assertion of an address line corresponding to the enable bit. The PLD further includes a read back circuit configured to selectively provide, for each memory cell, a data bit value stored by the memory cell or a predetermined data bit value based at least on the stored value of the register. Additional systems and related methods are provided.Type: GrantFiled: April 7, 2017Date of Patent: September 17, 2019Assignee: Lattice Semiconductor CorporationInventors: Loren McLaury, Brad Sharpe-Geisler
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Patent number: 10419001Abstract: A look up table (LUT) includes a decoder configured to decode input signals and to output decoded signals, a storage unit including a plurality of magnetic elements an being configured to select one or more of the plurality of magnetic elements in response to the decoded signals and a signal input/output (TO) unit configured to output an output signal corresponding to the selected one or more magnetic elements and to program the selected one or more magnetic elements by receiving a write signal.Type: GrantFiled: November 2, 2017Date of Patent: September 17, 2019Assignees: SK Hynix Inc., Industry-Academic Cooperation Foundation Yonsei UniversityInventors: Kangwook Jo, Jeongbin Kim, Minyoung Im, Taehee You, Eui-Young Chung, Hongil Yoon
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Patent number: 10411010Abstract: Disclosed are methods of forming improved fin-type field effect transistor (FINFET) structures and, particularly, relatively tall single-fin FINFET structures that provide increased drive current over conventional single-fin FINFET structures. The use of such a tall single-fin FINFET provides significant area savings over a FINFET that requires multiple semiconductor fins to achieve the same amount of drive current. Furthermore, since only a single fin is used, only a single leakage path is present at the bottom of the device. Thus, the disclosed FINFET structures can be incorporated into a cell in place of multi-fin FINFETs in order to allow for cell height scaling without violating critical design rules or sacrificing performance.Type: GrantFiled: January 4, 2018Date of Patent: September 10, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Ruilong Xie, Andreas Knorr, Murat Kerem Akarvardar, Lars Liebmann, Nigel Graeme Cave
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Patent number: 10411712Abstract: An integrated circuit comprising a field programmable gate array including a plurality of logic tiles, wherein, during operation of the field programmable gate array, each logic tile is configurable to connect with at least one logic tile of the plurality of logic tiles, and wherein each logic tile of the plurality of logic tiles includes an interconnect network, including a plurality of multiplexers, and logic circuitry. The field programmable gate array, in a first operational mode, includes a first group of logic tiles that are programmed in a powered-up state wherein each logic tile of the first group of logic tiles consumes electrical power during operation, and a second group of logic tiles of the plurality of logic tiles are programmed in a powered-down state wherein each logic tile of the second group of logic tiles does not consume electrical power during operation.Type: GrantFiled: July 23, 2018Date of Patent: September 10, 2019Assignee: Flex Logix Technologies, Inc.Inventors: Cheng C. Wang, Anthony Kozaczuk, Valentin Ossman
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Patent number: 10409338Abstract: A semiconductor device package includes a substrate including, on an edge thereof, a connector that is connectable to a host, a nonvolatile semiconductor memory device disposed on a surface of the substrate, a memory controller disposed on the surface of the substrate, an oscillator disposed on the surface of the substrate and electrically connected to the memory controller, and a seal member sealing the nonvolatile semiconductor memory device, the memory controller, and the oscillator on the surface of the substrate.Type: GrantFiled: March 1, 2016Date of Patent: September 10, 2019Assignee: Toshiba Memory CorporationInventors: Manabu Matsumoto, Katsuya Murakami, Akira Tanimoto, Isao Ozawa, Yuji Karakane, Tadashi Shimazaki
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Patent number: 10404627Abstract: Systems and methods are disclosed for buffering data using a multi-function, multi-protocol first-in-first-out (FIFO) circuit. For example, a data buffering apparatus is provided that includes a mode selection input and a FIFO circuit that is operative to buffer a data signal between a FIFO circuit input and a FIFO circuit output, wherein the FIFO circuit is configured in an operating mode responsive to the mode selection signal.Type: GrantFiled: August 14, 2017Date of Patent: September 3, 2019Assignee: Altera CorporationInventors: Huy Ngo, Keith Duwel, Vinson Chan, Divya Vijayaraghavan, Curt Wortman
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Patent number: 10396778Abstract: A device is disclosed that includes a circuit block coupled to a local power node, and a power gating circuit coupled between the local power node and a global power supply. In one embodiment, the power gating circuit includes a first plurality of first switching devices with a first threshold voltage, and a second plurality of second switching devices with a second threshold voltage that is different from the first voltage threshold. The power gating circuit may isolate the local power node from the global power supply based on an isolation signal.Type: GrantFiled: May 31, 2017Date of Patent: August 27, 2019Assignee: Apple Inc.Inventors: Sambasivan Narayan, Suparn Vats, Sangeetha Mani
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Patent number: 10397251Abstract: A system for securing an electronic circuit including: plural regions, activity of each of which may be controlled; plural sensors integrated into the electronic circuit, each sensor being sensitive to variations in manufacturing process and to provide a measurement representative of a local activity of the electronic circuit; a processing unit including an integrity verification module configured to: determine, based on the measurements provided by the sensors, and for each of the regions, a partition of the sensors between sensors affected and sensors not affected by an activation of the region; compare each of the partitions with a model partition to detect possible presence of a hardware Trojan horse liable to infect the electronic circuit. The system can carry out an authentication of the electronic circuit by its intrinsic physical characteristics by response to a challenge or by generation of a key.Type: GrantFiled: September 18, 2015Date of Patent: August 27, 2019Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Maxime Lecomte, Jacques Fournier, Philippe Maurine
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Patent number: 10387357Abstract: In a field-programmable gate array (FPGA) configuration circuit, and a radio-frequency unit and a magnetic resonance system having a configuration circuit, the configuration circuit has at least two FPGA modules, each FPGA module being individually connected to a bus; at least two storage devices, each storage device storing a configuration file; one of the at least two FPGA modules being connected to the at least two storage devices separately, and an input end, connected separately to the at least two storage devices. A selection signal is provided for selecting one of the at least two storage devices. The FPGA module connected to the at least two storage devices reads a configuration file stored in a storage device selected on the basis of the selection signal, and sends, via the bus, the configuration file that has been read to the FPGA module other than the FPGA module connected to the at least two storage devices.Type: GrantFiled: April 29, 2016Date of Patent: August 20, 2019Assignee: Siemens Healthcare GmbHInventors: Shu Qun Xie, Hai Bo Yu, Wen Bin Zhu
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Patent number: 10381092Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.Type: GrantFiled: June 15, 2018Date of Patent: August 13, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shinya Okuno, Shigeki Nagasaka, Toshiyuki Kouchi
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Patent number: 10379875Abstract: A solid state storage device includes a control circuit and a non-volatile memory. The control circuit includes a first storage zone and a second storage zone. A boot code loader is stored in the first storage zone. The non-volatile memory includes a memory cell array. The memory cell array includes a third storage zone and a fourth storage zone. A specified program is stored in the third storage zone. The third storage zone contains a first block. A first page of the first block is divided into a first portion and a second portion. A first binary code of the specified program is repeatedly stored in plural bytes of the first portion of the first page. The one's complement of the first binary code is repeatedly stored in plural bytes of the second portion of the first page.Type: GrantFiled: January 16, 2018Date of Patent: August 13, 2019Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, LITE-ON TECHNOLOGY CORPORATIONInventors: Ping-Jie Chen, Sheng-Yu Chang, Chien-Chih Weng
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Patent number: 10380063Abstract: Systems, methods, and apparatuses relating to a sequencer dataflow operator of a configurable spatial accelerator are described. In one embodiment, an interconnect network between a plurality of processing elements receives an input of a dataflow graph comprising a plurality of nodes forming a loop construct, wherein the dataflow graph is overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements and at least one dataflow operator controlled by a sequencer dataflow operator of the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements and the sequencer dataflow operator generates control signals for the at least one dataflow operator in the plurality of processing elements.Type: GrantFiled: September 30, 2017Date of Patent: August 13, 2019Assignee: Intel CorporationInventors: Jinjie Tang, Kermin E. Fleming, Simon C. Steely, Kent D. Glossop, Jim Sukha
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Patent number: 10372655Abstract: Systems and devices are provided for broadcasting a message to addressed logic blocks in lieu of, or in addition to, programming individual status registers of an integrated circuit. One such device may be an integrated circuit that includes a broadcast bus and addressed logic blocks. The broadcast bus may broadcast an addressed message that includes content and a target address. Each of the addressed logic blocks may receive the addressed message from the broadcast bus and use the content of the addressed message only when the target address matches an address assigned to that logic block.Type: GrantFiled: March 20, 2017Date of Patent: August 6, 2019Assignee: Altera CorporationInventor: Steven Perry
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Patent number: 10361702Abstract: An architecture in a user-programmable integrated circuit includes a hard logic block having inputs and outputs, a first group of user-configurable general-purpose routing resources coupled to first selected ones of the inputs of the hard logic block, a soft logic block having inputs and outputs, first selected ones of the inputs of the soft logic block coupled to the first group of user-configurable general-purpose routing resources, first selected ones of the outputs of the soft logic block having dedicated connections to second selected ones of the inputs to the hard logic block, and a second group of user-configurable general-purpose routing resources coupled to second selected ones of the outputs of the soft logic block and to first selected ones of the outputs of the hard logic block.Type: GrantFiled: October 31, 2018Date of Patent: July 23, 2019Assignee: Microsemi SoC Corp.Inventors: Jonathan W. Greene, Fei Li
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Patent number: 10360332Abstract: This application discloses a computing system configured to determine that a first bind command is configured to prompt instantiation of an assertion module in a target module of a circuit design, which creates a mixed-language environment for the circuit design. The computing system, in response to the determination that the first bind command is configured to create the mixed-language environment for the circuit design, configured to generate a wrapper module configured to prompt instantiation of the assertion module in the wrapper module. The computing system configured to generate a second bind command configured to prompt instantiation of the wrapper module in the target module.Type: GrantFiled: November 20, 2014Date of Patent: July 23, 2019Assignee: Mentor Graphics CorporationInventor: Gaurav Kumar Verma
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Patent number: 10360040Abstract: The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.Type: GrantFiled: February 20, 2018Date of Patent: July 23, 2019Assignee: Movidius, LTD.Inventors: David Moloney, Richard Richmond, David Donohoe, Brendan Barry
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Patent number: 10355003Abstract: A memory cell of the present disclosure includes: anti-fuses that are respectively inserted into a plurality of paths, one ends of the respective plurality of paths being coupled to one another; a resistor that is inserted into one or more of the plurality of paths; and a selection transistor that is turned on to couple a first coupling terminal to the one ends of the respective paths.Type: GrantFiled: November 27, 2015Date of Patent: July 16, 2019Assignee: SONY CORPORATIONInventor: Yuki Yanagisawa
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Patent number: 10355690Abstract: An apparatus is provided which comprises: a data sampler coupled to an output of a driver, wherein the data sampler is to sample data and to compare it with a first threshold voltage and a second threshold voltage, and wherein the data sampler is to generate an up or down indicator according to comparing the data with the first and second threshold voltages; and logic coupled to the data sampler, wherein the logic is to receive the up or down indicator and to increment or decrement a number of already DC compensated impedance legs of the driver according to the up or down indicator.Type: GrantFiled: September 28, 2016Date of Patent: July 16, 2019Assignee: Intel CorporationInventors: Siti Suhaila Mohd Yusof, Amit Kumar Srivastava, Lay Hock Khoo, Chin Boon Tear
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Patent number: 10346343Abstract: Encryption of a BIOS using a programmable logic device (PLD) is described. A PLD may include a static random-access memory area including programmable logic in a Lookup Table to receive a request to authenticate a basic input/output system (BIOS) executing on a processor coupled to the PLD. The PLD may calculate a hash value of a message associated with the BIOS using a Secure Hash Algorithm (SHA). The PLD may also include a random-access memory area including a first embedded random access memory block (EBR) to store a first portion of a 256-bit message digest associated with the message, a fifth portion of the 256-bit message digest, and second, third, fourth, sixth, seventh, and eighth EBRs to store second, third, fourth, sixth, seventh, and eighth portions of the 256-bit message digest, respectively.Type: GrantFiled: June 24, 2016Date of Patent: July 9, 2019Assignee: Intel CorporationInventors: Vikram Suresh, Sudhir Satpathy, Sanu Mathew, Neeraj Upasani
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Patent number: 10338554Abstract: The system generally includes a crosspoint switch in the local data collection system having multiple inputs and multiple outputs including a first input connected to the first sensor and a second input connected to the second sensor. The multiple outputs include a first and second output configured to be switchable between a condition in which the first output is configured to switch between delivery of the first sensor signal and the second sensor signal and a condition in which there is simultaneous delivery of the first sensor signal from the first output and the second sensor signal from the second output. Each of multiple inputs is configured to be individually assigned to any of the multiple outputs. Unassigned outputs are configured to be switched off producing a high-impedance state. The local data collection system is configured to manage data collection bands. The local data collection system includes a neural net expert system using intelligent management of the data collection bands.Type: GrantFiled: November 1, 2018Date of Patent: July 2, 2019Assignee: Strong Force IOT Portfolio 2016, LLCInventors: Charles Howard Cella, Gerald William Duffy, Jr., Jeffrey P. McGuckin
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Patent number: 10338136Abstract: An integrated circuit operable in a scan mode includes a scan chain formed by cascaded flip-flop cells. Each flip-flop cell includes a master latch that receives a first data signal and generates a first latch signal, a slave latch that receives the first latch signal and generates a second latch signal, and a multiplexer having first and second inputs respectively connected to the master and slave latches that receives a first input signal and the second latch signal, and generates a scan data output signal depending on an input trigger signal. The first input signal is one of the first data signal and the first latch signal. The clock signal provided to the slave latch is gated by the input trigger signal.Type: GrantFiled: November 30, 2016Date of Patent: July 2, 2019Assignee: NXP USA, INC.Inventors: Ling Wang, Wanggen Zhang, Wei Zhang