Sequential (i.e., Finite State Machine) Or With Flip-flop Patents (Class 326/46)
  • Patent number: 8933725
    Abstract: A state machine circuit switching between multiple states is provided. The state machine circuit has: a state patch circuit for generating a patched predicted state value, a patched output value, and a selection signal according to a current state value and at least one of a second input signal, a predicted state value, and an output value of the state machine circuit; a first selection circuit for outputting the patched predicted state or the predicted state to a register according to the selection signal; and a second selection circuit for outputting the patched output value or the output value according to the selection signal, wherein the predicted state value and the output value are generated according to a first input signal and the current state value of the state machine circuit, and the predicted state value and the output value are not generated according to the second input signal.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: January 13, 2015
    Assignee: Via Technologies, Inc.
    Inventor: Hung-Yi Kuo
  • Patent number: 8928381
    Abstract: Configurable flip-flop cells for use in scan chain configurations include one or more multiplexers, a flip-flop, and one or more logic gates. The logic gates are configurable, through modification of different metallization or semiconductor layers, to operate as spare gates or to disable flip-flop cell outputs based selection signal switching between scan shift and capture mode. When disabling flip-flop cell outputs, the logic gates are configured to receive both a test signal and a data input signal and select one of the two to pass to the flip-flop based on the selection signal. When used as spare gates, the logic gates receive external inputs and provide spare gate outputs to circuitry on an integrated circuit that is external to the flip-flop cells.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: January 6, 2015
    Assignee: STMicroelectronics Asia Pacific Pte Ltd
    Inventor: Beng-Heng Goh
  • Patent number: 8912824
    Abstract: A method and apparatus for detecting rising and falling transitions of internal signals of an array or integrated circuit. The apparatus comprises a delay line with a plurality of first to Nth delay elements, latches, and first to Nth groups of logic gates. Each of the first to Nth groups of the logical gates includes an AND gate and a NOR gate. The method and apparatus determines rising and falling signals based on output signals of the logic gates; in odd numbered groups of the logic gates, the AND gate detects the rising transition and the NOR gate detects the falling transition; in even numbered groups of the logic gates, the AND gate detects the falling transition and the NOR gate detects the rising transition.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Andreas Arp, Guenther Hutzl, Michael Koch, Matthias Ringe
  • Patent number: 8901960
    Abstract: There is provided a field programmable gate array (FPGA) mounted apparatus included in a first node of a plurality of nodes connected on a network, the FPGA mounted housing apparatus including a printed circuit board (PCB) on which an FPGA is mounted, and a controller configured to issue a request to acquire configuration data of the FPGA to a second node of the plurality of nodes, and configure the FPGA based on the configuration data acquired from the second node in response to the request.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: December 2, 2014
    Assignee: Fujitsu Limited
    Inventors: Asuka Takano, Hideki Matsui
  • Publication number: 20140347097
    Abstract: A multi-rail module having mutually exclusive outputs. The module includes first and second-rail logic circuits, first and second-rail driver circuits, and a PMOS transistor sourcing VDD to both the first and second driver circuits. The first-rail logic circuit is coupled to VDD and ground and has a first logic input and a first logic output. The second-rail logic circuit is coupled to VDD and ground and has a second logic input and a second logic output. The first-rail driver circuit is coupled to ground, receives the first logic output, and has a first-rail output Q1. The second-rail driver circuit is coupled to ground, receives the second logic output, and has a second-rail output Q0. The PMOS transistor has a gate driven by a SLEEP signal.
    Type: Application
    Filed: May 24, 2013
    Publication date: November 27, 2014
    Inventors: Scott C. Smith, Jia Di, Jerry Frenkil, Aaron Arthurs, Ron Foster
  • Patent number: 8896347
    Abstract: A synchronous digital signal capture system includes a first flip-flop and a synchronization module. The first flip-flop receives a logic control signal and a first clock signal having a first frequency. The first flip-flop is configured to output a synchronized data signal based on the logic control, and generate a synchronous reset signal that is a logic inverse of the synchronized data signal generated at the data output. The synchronization module receives a primary data signal and is configured to generate the logic control signal based on the primary input signal, a second clock signal, and the synchronous reset signal such that the first flip-flop generates the synchronized signal.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: November 25, 2014
    Assignee: Hamilton Sundstrand Corporation
    Inventor: David S. Harman
  • Patent number: 8892806
    Abstract: An integrated circuit, a memory device, a method of operating an integrated circuit and a method of designing an integrated circuit are provided. An integrated circuit comprises a plurality of logical elements and a bus carrying signals for said plurality of logical elements. The integrated circuit also comprises a routing unit having an input coupled to said bus and a plurality of outputs to route signals received at said input to at least one of said outputs. The integrated circuit also comprises a plurality of lines coupled to said plurality of outputs to conduct said signals from said routing unit to at least one of said plurality of logical elements, wherein at least one of said plurality of lines couples said routing unit to only one of said logical elements.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: November 18, 2014
    Assignee: Intel Mobile Communications GmbH
    Inventor: Hans Joachim Janssen
  • Patent number: 8866509
    Abstract: Integrated circuits having groups of flip-flops with the option to ignore control signals are disclosed. For example, an integrated circuit comprises a first group and a second group of flip-flops that share a common reset signal, and a first selection unit for selecting a first output from among the common reset signal and a logical low signal to be sent to the second group of flop-flops. A selection of the logical low signal is for preventing the common reset signal from being applied to the flip-flops in the second group. The integrated circuit may also include a second selection unit for selecting a second output from among the common reset signal and a logical low signal to be sent to the first group of flop-flops. A selection of the logical low signal is for preventing the common reset signal from being applied to the flip-flops in the first group.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 21, 2014
    Assignee: Xilinx, Inc.
    Inventors: Robert I. Fu, Chi M. Nguyen, James M. Simkins, Brian C. Gaide, Brian D. Philoksky
  • Patent number: 8854079
    Abstract: A system on chip (SoC) has a nonvolatile memory array of n rows by m columns coupled to one or more of the core logic blocks. M is constrained to be an odd number. Each time a row of m data bits is written, parity is calculated using the m data bits. Before storing the parity bit, it is inverted. Each time a row is read, parity is checked to determine if a parity error is present in the recovered data bits. A boot operation is performed on the SoC when a parity error is detected.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: October 7, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Steven Craig Bartling, Sudhanshu Khanna
  • Patent number: 8836369
    Abstract: A latch circuit switches a differential operation performed by a differential operation circuit including a first logic circuit, a second logic circuit, a third logic circuit, and a fourth logic circuit and a single end operation performed by a single end operation circuit according to a logic level of an inputted selection signal. The latch circuit performs an operation to output an input signal and an inverted input signal without change from a first output terminal and a second output terminal of the latch circuit, respectively, and an operation to set the input signal and the inverted input signal in a hold state in the differential operation and performs an operation to output the input signal from the first output terminal without change and an operation to set the input signal in a hold state in the single end operation, according to a clock signal and an inverted clock signal.
    Type: Grant
    Filed: October 3, 2012
    Date of Patent: September 16, 2014
    Assignee: Fujitsu Limited
    Inventors: Yuuki Ogata, Yoichi Koyanagi
  • Patent number: 8836400
    Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SSN and PREN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: September 16, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Steven Bartling, Sudhanshu Khanna
  • Patent number: 8791718
    Abstract: The disclosure relates generally to triple-redundant sequential state (TRSS) machines formed as integrated circuits on a semiconductor substrate, such as CMOS, and computerized methods and systems of designing the triple-redundant sequential state machines. Of particular focus in this disclosure are sequential state elements (SSEs) used to sample and hold bit states. The sampling and holding of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines. In particular, the clock signal may oscillate between a first clock state and a second clock state to synchronize the operation of the SSE according to the timing provided by the clock states. The SSEs have a self-correcting mechanism to protect against radiation induced soft errors. The SSE may be provided in a pipeline circuit of a TRSS machine to receive and store a bit state of bit signal generated by combinational circuits within the pipeline circuit.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: July 29, 2014
    Assignee: Arizona Board of Regents for and on behalf of Arizona State University
    Inventors: Lawrence T. Clark, Nathan D. Hindman, Dan Wheeler Patterson
  • Publication number: 20140197864
    Abstract: A latch circuit and method includes providing a first tri-gate non-volatile device, providing a second tri-gate non-volatile device, coupling the first tri-gate non-volatile device to the second tri-gate non-volatile device, erasing the first tri-gate non-volatile device, programming the second tri-gate non-volatile device, and latching an output node of the latch device to a logic state determined by respective thresholds of the first and second tri-gate non-volatile devices. Coupling the first tri-gate non-volatile device to the second tri-gate non-volatile device can include direct coupling, or indirect coupling through a cross-coupled circuit.
    Type: Application
    Filed: March 14, 2013
    Publication date: July 17, 2014
    Inventor: Venkatraman Prabhakar
  • Patent number: 8782624
    Abstract: A device including a data analysis element including a plurality of memory cells. The memory cells analyze at least a portion of a data stream and output a result of the analysis. The device also includes a detection cell. The detection cell includes an AND gate. The AND gate receives result of the analysis as a first input. The detection cell also includes a D-flip flop including an output coupled to a second input of the AND gate.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: July 15, 2014
    Assignee: Micron Technology, Inc.
    Inventors: David R. Brown, Harold B Noyes
  • Publication number: 20140184268
    Abstract: A multiplexer tree operable to control an output a sequence of data stored in a plurality of storage units in accordance with a non-linear address sequence that has less bit transition counts than a linear address sequence. The non-linear address sequence is provided to the selection inputs of the multiplexer tree and causes the levels having greater numbers of multiplexers to toggle less frequently than the levels having smaller numbers of multiplexers. The non-linear address sequence may comprise a Gray code sequence where every two adjacent addresses differ by a single bit. The non-linear address sequence may be optimized to minimize transistor switching in the multiplexer tree.
    Type: Application
    Filed: December 31, 2012
    Publication date: July 3, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Robert A. Alfieri, Kelvin Kwok-Cheung Ng
  • Patent number: 8766666
    Abstract: Programmable devices, hierarchical parallel machines and methods for providing state information are described. In one such programmable device, programmable elements are provided. The programmable elements are configured to implement one or more finite state machines. The programmable elements are configured to receive an N-digit input and provide a M-digit output as a function of the N-digit input. The M-digit output includes state information from less than all of the programmable elements. Other programmable devices, hierarchical parallel machines and methods are also disclosed.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: July 1, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Paul Dlugosch
  • Patent number: 8732646
    Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
    Type: Grant
    Filed: March 20, 2013
    Date of Patent: May 20, 2014
    Assignee: Altera Corporation
    Inventors: Andy L. Lee, Cameron R. McClintock, Brian D. Johnson, Richard G. Cliff, Srinivas T. Reddy, Christopher F. Lane, Paul Leventis, Vaughn Betz, David Lewis
  • Patent number: 8717062
    Abstract: Apparatuses for reducing power consumption in a programmable logic device (PLD) with a self power down mechanism are disclosed. Methods and a machine readable medium for restoring a prior known state are provided. The prior known state is stored in a memory module before the PLD is powered down and the same state is restored from the memory module when the PLD is powered up. The memory module may be an internal or an external non-volatile or volatile memory source. One sector of the memory may be used to store the previous known state. The memory sector can be partitioned into different sections. One section may be used as a header section associated with a data storage section. Partitioning the memory sector into different sections and utilizing multiple addresses from each section ensure less read and write cycles during the powering down and the powering up of the PLD.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: May 6, 2014
    Assignee: Altera Corporation
    Inventor: Chee Wai Yap
  • Patent number: 8680888
    Abstract: A device includes a routing buffer. The routing buffer includes a first port configured to receive a signal relating to an analysis of at least a portion of a data stream. The routing buffer also includes a second port configured to selectively provide the signal to a first routing line of a block of a state machine at a first time. The routing buffer further includes a third port configured to selectively provide the signal to a second routing line of the block of the state machine at the first time.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: March 25, 2014
    Assignee: Micron Technologies, Inc.
    Inventors: David R. Brown, Harold B Noyes, Irene Junjuan Xu, Paul Glendenning
  • Publication number: 20140070841
    Abstract: A circuit for implementing latch array functions on an integrated circuit. Portions of the logic devices included in the implementation of the latch array functions that are controlled by a common signal, may be arranged in a particular alignment. A single layer uni-directionally conductive material may connect the common signal to the logic devices.
    Type: Application
    Filed: September 13, 2012
    Publication date: March 13, 2014
    Inventors: Michael R. Seningen, Gregory D. Roberts, Robert Kenney, James De Leon
  • Patent number: 8664976
    Abstract: The invention provides a shift register which can operate normally while suppressing a delay of signal and a rounding of waveform. The shift register of the invention includes a plurality of stages of flip-flop circuits each of which includes a clocked inverter. The clocked inverter includes a first transistor and a second transistor which are connected in series, a first compensation circuit including a third transistor and a fourth transistor which are connected in series, and a second compensation circuit including a fifth transistor and a transmission gate. According to the first compensation circuit, a timing at which a signal outputted from the flip-flop circuit rises or falls can be controlled in synchronization with an output of two stages before. The second compensation circuit can control a clock signal input can be controlled.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: March 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mitsuaki Osame, Aya Anzai
  • Publication number: 20140049286
    Abstract: The disclosure relates generally to sequential state elements (SSEs), triple-mode redundant state machines (TMRSMs), and methods and systems for testing triple-mode redundant pipeline stages (TMRPSs) within the TMRSMs using triple-mode redundant SSEs (TMRSSEs). The SSEs, TMRSMs, TMRPSs, and TMRSSEs may be formed as integrated circuits on a semiconductor substrate. Of particular focus in this disclosure are SSEs used to sample and hold bit states. Embodiments of the SSEs have a self-correcting mechanism to protect against radiation-induced soft errors. The SSE may be provided in a pipeline circuit of a TMRSM to receive and store a bit state of a bit signal generated by combinational circuits within the pipeline circuit. More specifically, the SSEs may be provided in a TMRSSE configured to perform self-correction. Also disclosed are methods for using the TMRSSE to test redundant pipeline stages of the TMRSM.
    Type: Application
    Filed: October 24, 2013
    Publication date: February 20, 2014
    Applicant: Arizona Board of Regents, a body corporate of the State of Arizona, acting for and on behalf of Ariz
    Inventor: Lawrence T. Clark
  • Patent number: 8648621
    Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may include a counter suitable for counting a number of times a programmable element in the lattice detects a condition. The counter may be configured to output in response to counting the condition was detected a certain number of times. For example, the counter may be configured to output in response to determining a condition was detected at least (or no more than) the certain number of times, determining the condition was detected exactly the certain number of times, or determining the condition was detected within a certain range of times. The counter may be coupled to other counters in the device for determining high-count operations and/or certain quantifiers.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: February 11, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Harold B Noyes, David R. Brown, Paul Glendenning
  • Patent number: 8643400
    Abstract: To provide a semiconductor device which operates stably with few malfunctions due to noise, with low power consumption, and little variation in characteristics; a display device including the semiconductor device; and an electronic device including the display device. An output terminal is connected to a power supply line, thereby reducing variation in electric potential of the output terminal. In addition, a gate electrode potential which turns ON a transistor is maintained due to the capacitance of the transistor. Further, change in characteristics of the transistor is reduced by a signal line for reverse bias.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: February 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasunori Yoshida
  • Patent number: 8629691
    Abstract: Systems and methods are disclosed for interfacing between hard logic elements and soft logic elements implemented on an integrated device. In particular, a configurable interface is provided that includes interconnects between hard logic and soft logic, which enable signals to be selectively routed between the inputs and outputs of hard logic blocks and soft logic modules. The interconnects allow for certain hard logic blocks to be bypassed in favor of soft logic functionality. Moreover, the interconnects allow soft logic to augment the processing of hard logic blocks, e.g., by providing additional signals to the hard logic block.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: January 14, 2014
    Assignee: Altera Corporation
    Inventors: Michael Fitton, Kulwinder Dhanoa, Benjamin Thomas Cope, Kellie Marks, Lei Xu
  • Patent number: 8624623
    Abstract: According to an embodiment, an apparatus includes: a first node configured to receive a data input signal of a data latch; a second node configured to receive a data output signal of the data latch; process and hold circuitry configured to process a difference between a value of the data input signal received at the first node and a value of the data output signal received at the second node and hold respective values at the first and second nodes responsive to the difference; and comparison circuitry configured to compare the value held at the first node and a value of the data output signal of the data latch; wherein the process and hold circuitry is configured to be biased toward the signal received at one of the first node and the second node.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: January 7, 2014
    Assignee: STMicroelectronics International N.V.
    Inventors: Navneet Gupta, Prashant Dubey, Kaushik Saha, AtulKumar Kashyap
  • Patent number: 8604833
    Abstract: An integrated circuit device comprising one or more data processing circuits, each having an input stage, a combinatorial logic stage and an output stage. The input stage is responsive to a clock signal, and receives at least a first and second set of data signals and provides the first set to an input of the logic stage during a first portion of a clock signal period, and provides the second set to the input during a second portion of the period. The output stage is responsive to the clock signal, and receives from an output of the logic stage at least a first result signal as a function of the first set during a first portion of a subsequent clock signal period and receives from the output at least a second result signal as a function of the second set during a second portion of the subsequent period.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: December 10, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Shai Kowal, Assaf Babay, Ilan Cohen
  • Patent number: 8598909
    Abstract: Some embodiments provide a configurable integrated circuit (IC) comprising multiple deskew circuits for delaying data passage. Each of the deskew circuits comprises a stepwise delay circuit with multiple outputs and an input selection circuit with multiple inputs. Multiple outputs connect to multiple inputs. In some embodiments the configurable IC is a subcycle reconfigurable IC. In some such embodiments each of the deskew circuits further includes a space-time load control circuit for commanding the stepwise delay circuit to load during a selected subcycle. In some embodiments the multiple deskew circuits send data to a trigger circuit. In some such embodiments the trigger circuit triggers a trace buffer to stop recording a data stream. In some such embodiments the trigger circuit triggers the trace buffer to stop after a programmable delay.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: December 3, 2013
    Assignee: Tabula, Inc.
    Inventor: Brad Hutchings
  • Patent number: 8593175
    Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: November 26, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Harold B Noyes, David R. Brown, Paul Glendenning, Irene Junjuan Xu
  • Publication number: 20130293265
    Abstract: A signal transfer circuit includes a signal transfer unit configured to transfer an input signal applied to an input node to an output node in response to a control signal and a driving unit configured to drive an output signal of the output node to a level of the input signal in response to the control signal.
    Type: Application
    Filed: June 28, 2013
    Publication date: November 7, 2013
    Inventor: Young-Kyu NOH
  • Patent number: 8561007
    Abstract: A distributable and serializable finite state machine and methods for using the distributable and serializable finite state machine are provided wherein finite state machine instance can be location-shifted, time-shifted or location-shift and time-shifted, for example by serializing and deserializing each instance. Each instance can be located-shifted between agents, and a persistent memory storage location is provided to facilitate both location-shifting and time-shifting. Finite state machine instances and the actions that make up each instance can be run in a distributed fashion among a plurality of agents.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: October 15, 2013
    Assignee: International Business Machines Corporation
    Inventors: James R. Challenger, Louis R. Degenaro, James R. Giles, Paul Reed, Rohit Wagle
  • Publication number: 20130234757
    Abstract: To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion configured to hold data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element. In addition, a capacitor electrically connected to a source electrode or a drain electrode of the transistor is included.
    Type: Application
    Filed: April 29, 2013
    Publication date: September 12, 2013
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Jun Koyama
  • Patent number: 8530880
    Abstract: A reconfigurable multilayer circuit (400) includes a complimentary metal-oxide-semiconductor (CMOS) layer (210) having control circuitry, logic gates (515), and at least two crossbar arrays (205, 420) which overlie the CMOS layer (210). The at least two crossbar arrays (205, 420) are configured by the control circuitry and form reconfigurable interconnections between the logic gates (515) within the CMOS layer (210).
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: September 10, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Dmitri Borisovich Strukov, R. Stanley Williams, Yevgeniy Eugene Shteyn
  • Patent number: 8531208
    Abstract: A flip-flop is provided. The flip-flop includes a first latch circuit configured to latch a data signal in response to a plurality of first control signals or latch a scan input signal in response to a plurality of second control signals, and a second latch circuit configured to latch a signal output from the first latch circuit in response to complementary clock signals.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: September 10, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gun Ok Jung, Min Su Kim, Uk Rae Cho, Dae Young Moon, Hyoung Wook Lee
  • Patent number: 8519742
    Abstract: A latch includes three circuits. The first circuit drives a first output (QB) to a first level when a first input (D) and a first clock phase (CK) are both low, to a second level when D and CK are both high, and provides high impedance (HI-Z) when different logic levels are applied to D and CK. The second circuit drives a second output (Q) to the first level when a third input (DB) and a complimentary clock phase (CKB) are both low, to the second level when DB and CKB are both high, and provides HI-Z when different logic levels are applied to DB and CKB. The third circuit maintains voltages of Q and QB when the first and second circuits provide HI-Z at Q and QB. Odd-number dividers constructed with such latches produce 50% duty cycle operation without restricting output pulse widths to integer multiples of input periods.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: August 27, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Kun Zhang, Kenneth Barnett
  • Patent number: 8513977
    Abstract: A semiconductor device which stores data, and in which refresh operation is not needed, is described. The semiconductor device comprises at least a transistor and a capacitor. A first electrode of the capacitor is connected to a reference voltage terminal and a second electrode of the capacitor is connected to one of a source and a drain of the transistor. The semiconductor device is configured to put, when necessary, the other of the source and the drain of the transistor to the same potential as the one of the source and the drain, so that charge accumulated in the capacitor, which is connected to the one of the source and the drain of the transistor, does not leak through the transistor.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: August 20, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Takanori Matsuzaki
  • Patent number: 8508255
    Abstract: A method and apparatus that controls the clock of a digital circuit, and therefore power consumption, without substantially comprising performance is provided. The apparatus may include monitoring the utilization of a First in First Out (FIFO) buffer. For example in a systems and methods according to the invention, clock speed may be reduced when the FIFO is relatively empty and increased when the FIFO is relatively full. The clock speed may be controlled by a phase locked loop, a clock divider, a clock masking device or a combination of more than one of these methods. Power reduction may also be obtained by controlling the clocking of different stages of a pipelined device. One or more aspects of the inventions may be implemented in combination with other aspects of the invention to further reduce power use.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: August 13, 2013
    Assignee: Broadcom Corporation
    Inventors: Aviran Kadosh, Golan Schzukin
  • Patent number: 8502561
    Abstract: A D-type flip-flop includes tristate inverter circuitry passing a processing signal through to storage circuitry 8 from where the processing signal passes via a transmission gate to slave storage circuitry. A transition detector is coupled to the input node of the storage circuitry and serves to generate an error signal if a transition is detected upon that input node during an error detecting period. Other forms of this technique may provide clock gating circuitry.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: August 6, 2013
    Assignee: ARM Limited
    Inventors: David William Howard, David Michael Bull, Shidhartha Das
  • Patent number: 8495550
    Abstract: This invention comprises a layout method to effectively protect electronic circuits against soft errors (non-destructive errors) and circuit cells, which are protected against soft errors. The invention applies a layout method to sequential and combinational logic to generate specific circuit cells with netlists and layouts which are hardened against single event generated soft-errors. It also devices methods of how two or more such cells should be laid out and placed relative to each other, in order to have the best global soft-error protection.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: July 23, 2013
    Inventor: Klas Olof Lilja
  • Publication number: 20130181740
    Abstract: A Static Sleep Convention Logic (SSCL) circuit. The circuit improves upon Multi-Threshold NULL Convention Logic (MTNCL), disclosed in U.S. Pat. No. 7,977,972, by utilizing the SECRII architecture along with the Bit-Wise MTNCL technique, to produce a new SSCL gate without an nsleep input, which yields a smaller and faster circuit that utilizes less energy per operation than the patented SMTNCL gate design, while only very slightly increasing leakage power during sleep mode.
    Type: Application
    Filed: January 11, 2013
    Publication date: July 18, 2013
    Applicant: THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ARKANSA
    Inventors: Scott Christopher Smith, Jia Di
  • Patent number: 8487647
    Abstract: System and method for deglitching an input signal. An output signal may be delayed to generate a delayed signal, the delayed signal determining a guard time interval following a desired transition in the input signal, and a logic circuit is used to keep the output signal unchanged during the guard time interval, and to allow the output signal to equal the input signal outside the guard time interval, based on a value of the delayed signal.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: July 16, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Juan Luis Lopez Rodriguez, Marina Ferran Farres, Pere Esterri Pedra
  • Patent number: 8476927
    Abstract: An object of the present invention is to provide a programmable logic device which has short start-up time after supply of power is stopped, is highly integrated, and operates with low power. In a programmable logic device including an input/output block, a plurality of logic blocks each including a logic element, and a wiring connecting the plurality of logic blocks, the logic element has a configuration memory for holding configuration data and a look-up table including a selection circuit. The configuration memory includes a plurality of memory elements each of which includes a transistor whose channel region is in an oxide semiconductor film and an arithmetic circuit provided between the transistor and the selection circuit. Configuration data is selectively changed and output by the selection circuit in accordance with an input signal.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: July 2, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tatsuji Nishijima
  • Patent number: 8476951
    Abstract: A latch circuit, such as a memory cell or a flip-flop, that is immune to single-event upset at any single node. The latch circuit includes two banks of four logic gates each. The output of each logic gate in the first bank is connected to inputs of two logic gates in the second bank, and the output of each logic gate in the second bank is connected to inputs of two logic gates in the first bank. Each logic gate includes a logic function receiving an input node and an enable signal, such as a load signal. The interconnection of the logic gates corrects single-event upset at any one of the nodes. In the memory cell arrangement, redundant data paths are used to produce two input nodes provides single-event upset immunity at those input nodes. A layout of the latch circuit that ensures that random ionization affects only a single node is also disclosed.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: July 2, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Hugh Pryor McAdams
  • Patent number: 8476929
    Abstract: In the case where data is rewritten in a delay period of a signal in a flip flop and a shift register which use an inverted clock signal, current inhibiting charging may flow, whereby data cannot written quickly, so that charging is not completed, which makes operation unstable. In view of the above, a flip flop and a shift register without using an inverted clock signal, which have high stability are provided. Current inhibiting charging of a node where that current inhibiting charging flows is cut off at the time of rewriting data so that data is rewritten quickly.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: July 2, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 8471597
    Abstract: A circuit is described including a clock input for at least one clock signal. Only one clock buffer is connected to the clock input to generate, based on the at least one clock signal, at least a first modified clock signal and a second modified clock signal. A plurality of flip-flops are connected to the clock buffer. Each of the flip-flops receive the first and second modified clock signals. A plurality of data inputs are each connected to at least one of the plurality of flip-flops to provide input data to the plurality of flip-flops. A plurality of data outputs each are connected to at least one of the plurality of flip-flops to provide output data from the plurality of flip-flops. Each of the plurality of flip-flops transform the input data to the output data utilizing the first modified clock signal and the second modified clock signal.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: June 25, 2013
    Assignee: Qualcomm Incorporated
    Inventors: Shenghong Wang, Mayan Moudgill, Gary Nacer
  • Patent number: 8471595
    Abstract: A selectable latch has a pair of parallel pass gates (a first parallel pass gate that receives a seed signal, and a second parallel pass gate that receives a data signal). A first latch logic circuit performs logic operations using signals output by the parallel pass gates to produce an updated data signal. An additional pass gate is operatively connected to the first latch logic circuit. An additional pass gate controls passage of the updated data signal. The output of the parallel pass gates and the additional pass gate is connected to a feedback loop. The feedback loop operates as a dynamic latch for high frequency applications or as a static latch for low frequency applications. Thus, the selectable latch comprises two inputs into the pair of parallel pass gates and performs only one of four logical operations on a received data signal.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: June 25, 2013
    Assignee: International Business Machines Corporation
    Inventors: John S. Austin, Kai D. Feng, Shiu Chung Ho, Zhenrong Jin, Michael R. Ouellette
  • Patent number: 8461865
    Abstract: A logic built-in self test (LBIST) system comprises a device under test having a first plurality of first bistable multivibrator circuits an LBIST controller, and a second plurality of second bistable multivibrator circuits. Each second bistable multivibrator circuit is coupled to a corresponding first bistable multivibrator circuit to swap a second state value kept by the second bistable multivibrator circuit with a first state value kept by the corresponding first bistable multivibrator circuit depending on a first control signal from the LBIST controller and the second bistable multivibrator circuits are coupled to form one or more scan chains when receiving a second control signal from the LBIST controller.
    Type: Grant
    Filed: November 24, 2008
    Date of Patent: June 11, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Rolf Schlagenhaft
  • Patent number: 8461871
    Abstract: On an interface between LSIs, boards, devices (units), and others, the data transfer efficiency per signal line is improved. A shift circuit 710-0 shifts a piece of digital signal D1(0) for output as three digital signals D1S(00) to (02). An analog conversion circuit 720-0 converts the three digital signals D1S(00) to (02) into a piece of analog signal A2(0) for transfer. A digital conversion circuit 730-0 converts the piece of analog signal A2(0) into three digital signals D3(00) to (02). A selection circuit 740-0 makes a sequential selection from the three digital signals D3(00) to (02) to output a piece of digital signal D4(0).
    Type: Grant
    Filed: October 9, 2009
    Date of Patent: June 11, 2013
    Assignee: Sony Corporation
    Inventor: Akira Ishizuka
  • Patent number: 8456193
    Abstract: Specific logic gates for q-gating are selected by determining the minimum leakage state for a circuit design and then selecting logic gates that hold the circuit design in its lowest leakage state. Depending on the input desired to implement the minimum leakage state, the gate may be selected as a NOR or OR gate. Q-gating that is implemented with gates chosen to implement the minimum leakage state may be enabled during selected operating modes. The minimum leakage state of a circuit can be determined with an automatic test pattern generation (ATPG) tool.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: June 4, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Rajamani Sethuram, Karim Arabi
  • Patent number: 8456191
    Abstract: The exemplary embodiments provide a reconfigurable integrated circuit architecture comprising: a configurable circuit element configurable for a plurality of data operations, each data operation corresponding to a context of a plurality of contexts; a plurality of input queues; a plurality of output queues; one or more configuration and control registers to store, for each context of the plurality of contexts, a plurality of configuration bits, a run status bit, and a plurality of bits designating at least one data input queue and at least one data output queue; and an element controller coupled to the configurable circuit element and to the one or more configuration and control registers, the element controller to allow loading of a context configuration and execution of a data operation upon the arrival of input data in the context-designated data input queue when the context run status is enabled and the context-designated data output queue has a status to accept output data.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: June 4, 2013
    Assignee: Element CXI, LLC
    Inventors: Steven Hennick Kelem, Brian A. Box, John M. Rudosky, Stephen L. Wasson