Abstract: A nonvolatile semiconductor memory apparatus includes a control unit configured to generate a select signal and a driving control signal in response to a first enable signal and a second enable signal; a level shifting unit configured to enable a first shifting signal or a second shifting signal to a level of a pumping voltage in response to the select signal and the driving control signal; a first switching unit configured to apply a program voltage to a word line when the first shifting signal is enabled to the level of the pumping voltage; and a second switching unit configured to apply a pass voltage to the word line when the second shifting signal is enabled to the level of the pumping voltage.

Abstract: A device and method for dc isolation and level shifting includes a driver circuit powered by a first voltage range, a capacitor connected to the driver circuit, and a latching circuit connected to the capacitor. The latching circuit is powered by a second voltage range and is configured to restore and/or minimize charge loss of the capacitor during a voltage transition at the capacitor. A device and method for analog isolation and measurement configured to measure an analog voltage at a second potential without requiring analog circuits at the second potential.

Abstract: A level shifting circuit having an input and an output where the level shifting circuit is configured to receive a logical high level having a first voltage level at the input and to output a logical high level having a second voltage level at the output where the second voltage level is higher than the first voltage level. Level shifting circuit embodiments having two or more parallel coupled depletion mode transistors coupled to a high voltage source and further coupled to the output by an enhancement mode transistor, and an additional transistor coupled between a first signal and the output of the level shifting circuit where the first signal has the same logic level of the input are disclosed.

Abstract: A voltage translator circuit includes an input stage adapted for receiving an input signal referenced to a first voltage supply, a first latch circuit adapted for connection with a second voltage supply and operative to at least temporarily store a logic state of the input signal, and a voltage clamp coupled between the input stage and the first latch circuit. The voltage clamp is operative to set a maximum voltage across the input stage to a prescribed level. The voltage translator circuit generates a first output signal at a first output formed at a junction between the first latch circuit and the voltage clamp. A second latch circuit is connected to the first output in a feedback configuration. The second latch circuit is operative to retain a logical state of the first output signal as a function of at least a first control signal supplied to the second latch circuit regardless of a state of the first voltage supply.

Abstract: Some of the embodiments of the present disclosure provide a method comprising providing an integrated circuit with a level shifting circuit having a pull up device that is configured to selectively pull up a voltage level of an output signal from a low voltage level to a high voltage level, and having a pull down device that is configured to selectively pull down the voltage level of the output signal from the high voltage level to the low voltage level; ascertaining a high level of an input control signal; and when the output signal is at the high voltage level, deasserting the pull up device. Other embodiments are also described and claimed.

Abstract: A design support method for causing a computer using layout data for providing a layout in which macro cells are arranged and in which power supply wirings are formed at certain intervals in each wiring layer to execute, the method including: extracting a set of adjacent macro cells from the layout data; specifying a region located between macro cells that constitute the set of adjacent macro cells extracted in the extracting step from among row regions included in the layout represented by the layout data; detecting a power supply wiring of a specific wiring layer in a projection area located above the region specified in the specifying step, the specific wiring layer being higher than a bottom layer of the layout represented by the layout data; and outputting a region where no power supply wiring of the specific wiring layer is detected in the detecting step.

Abstract: A test controller switches the operation of output stages in an integrated circuit between a normal operation mode and a test mode. The output stages are respectively connected to switch elements. A level shifter generates a switch signal for controlling activation and deactivation of the switch elements in accordance with the normal operation mode and the test mode.

Abstract: An input buffer system with a dual-input buffer switching function includes a first input buffer, a second input buffer, and a multiplexer. The first input buffer is used for outputting a first signal when an input signal is at a logic-high voltage, and the first input buffer is turned off when the input signal is at a logic-low voltage. The second input buffer is used for outputting a second signal when the input signal is at the logic-low voltage. The multiplexer is coupled to the first input buffer and the second input buffer for outputting the first signal or the second signal according to a self refresh signal.

Abstract: An IO buffer module optimized for a wide range of drive levels both in terms of area and performance that includes an IO cell module and at least one IO adder module operatively coupled to said IO cell module for enabling the IO buffer module for the wide range of drive levels. The IO adder module can be added with the IO cell module in a number of different combinations for providing the wide range of drive levels, and the IO buffer module can provide drive solutions from 1 mA to 10 mA or higher, in steps of 0.5 mA drive level.

Abstract: A digital signal voltage level shifter includes an edge detector that detects assertion of a digital input signal from a first logic circuit in a source voltage domain, and an output module triggered by the edge detector for asserting a digital output signal corresponding to the digital input signal for a second logic circuit in a destination voltage domain. The edge detector and the output module are supplied with power only from a power supply of the destination voltage domain and are not connected to a power supply of the source voltage domain.

Abstract: A semiconductor device includes: two level shift circuits having substantially the same circuit configuration; an input circuit that supplies complementary input signals to the level shift circuits, respectively; and an output circuit that converts complementary output signals output from the level shift circuits into in-phase signals and then short-circuits the in-phase signals. According to the present invention, the two level shift circuits having substantially the same circuit configuration are used, and the complementary output signals output from the level shift circuits are converted into in-phase signals before short-circuited. This avoids almost any occurrence of a through current due to a difference in operating speed between the level shift circuits.

Abstract: A static complementary transistor type logic gate circuit includes a plurality of input terminals for receiving a corresponding plurality of input signals, and an output terminal. The logic gate circuit further includes a first plurality of transistors of one conductivity type, arranged to form a plurality of pullup paths for selectively connecting the output terminal, through one or more intermediate nodes, to a positive supply voltage based on the plurality of input signals; and a second plurality of transistors of the complementary conductivity type, arranged to form a plurality of pulldown paths for selectively connecting the output terminal, through one or more intermediate nodes, to a negative supply voltage based on the plurality of input signals. A precharge device is configured to selectively charge an intermediate node to the far-side supply voltage when the intermediate node is disconnected from the near-side supply voltage and disconnected from the output terminal.

Abstract: Disclosed is a level shifter that includes an input node; first and second voltage shifter circuits configured to generate an output clock of a second voltage domain in response to an input clock of a first voltage domain input via the input node, and an output node configured to output the output clock, wherein the first and second voltage shifter circuits have the same structure and are connected in parallel between the input node and an output node.

Abstract: A semiconductor device includes a first input circuit to which a first supply voltage is supplied, a second input circuit to which a second supply voltage that is lower than the first supply voltage is supplied, and a control circuit which activates the first input circuit in a first mode and activates the second input circuit in a second mode. The control circuit controls the first input circuit and the second input circuit such that the first input circuit and the second input circuit are activated during a certain time period when switching between the first mode and the second mode.

Abstract: A level shifting circuit includes a string of diodes and an active load across which the control voltage is applied. A resistor is coupled across the lowermost diode to develop a switch control voltage. At low control voltage, the diode string allows no current to be developed across the resistor. At higher control voltage, the diodes conduct and the active load takes up the difference between the control voltage and the diode string voltage. A switch responds to the resistor voltage, for switching a load On and OFF. A second active load takes up excess load supply voltage.

Abstract: A level shift circuit is disclosed. The circuit includes a series circuit of a resistor and a switching device connected between a high voltage side power supply voltage in a secondary side voltage system and a low voltage side power supply voltage in a primary side voltage system, a series circuit of a resistor and a switching device connected between the high voltage side power supply voltage in the secondary side voltage system and the low voltage side power supply voltage in the primary side voltage system, and a latch malfunction protecting circuit operated in the secondary side voltage system to have voltages at a connection point of the resistor and the switching device and at a connection point of the resistor and the switching device inputted.

Abstract: The memory system includes a semiconductor memory that has an internal circuit, which operates according to a first power supply voltage, and a memory input/output circuit coupled to the internal circuit and operates according to a second power supply voltage, a first control unit that includes a control input/output circuit, coupled to the memory input/output circuit and operates according to the second power supply voltage, a voltage generating unit that generates the second power supply voltage and changes the second power supply voltage according to a voltage adjustment signal, a clock generating unit that generates the clock signal and changes the frequency of the clock signal according to a clock adjustment signal, and a second control unit that generates the voltage adjustment signal and the clock adjustment signal according to an access state of the semiconductor memory by the first control unit.

Abstract: A voltage level translator circuit has a digital logic circuit having a digital logic signal, at least one high-voltage capacitor having a first and second connection, wherein one of the first and second connections is electrically coupled to the digital logic signal, and a cross-coupled inverter pair having, the output of at least one inverter of the pair electrically coupled to the other connection of the at least one high-voltage capacitor.

Abstract: The present invention provides a self-aware power control system and a method for determining the circuit state. The self-aware adaptive power control architecture comprises of a multi-mode power gating network, a current monitoring translator, a variable threshold comparator, a slack detector, and a bi-directional shift register. The multi-mode power gating network controls the amount of supply current and hence the circuit speed. The power gating network can be composed of either N-type MOSFETs for virtual ground insertion or P-type MOSFETs for virtual supply insertion. The number of MOSFETs in the multi-mode power gating network can be configured according to the supply range and step difference of the supply current. Then, by monitoring the current characteristics drained by target circuit, the circuit state can be determined. No delay matching circuit is required. Together with other peripherals, the supply current can be down controlled to a minimum acceptable level.

Abstract: A signal driver for an interface circuit has a first stage level shifter to accept input signals and output signals at a first signal level. The signal driver also has a second stage level shifter coupled to the first stage level shifter to output signals at a second signal level. Electronic components of the first and second stage level shifter have reliability limits less than the second signal level. The first and second stage configurations of the first stage level shifter and the second stage level shifter prevents exposing the electronic components to terminal to terminal signal levels higher than the reliability limits when processing signals for output at the second signal level.

Abstract: A fast current generating element in a current generating unit, used by the present invention, provides a large current for accelerating the switching of transistor switches when the transistor switches are switched. The fast current generating element includes a capacitor to provide a large differential current when a voltage level transiently changes during the switching of the transistor switches. Therefore, a transient response time of a signal transformer is shortened.

Abstract: A digital signal voltage level shifter includes an edge detector that detects assertion of a digital input signal from a first logic circuit in a source voltage domain, and an output module triggered by the edge detector for asserting a digital output signal corresponding to the digital input signal for a second logic circuit in a destination voltage domain. The edge detector and the output module are supplied with power only from a power supply of the destination voltage domain and are not connected to a power supply of the source voltage domain.

Abstract: A flip-flop circuit with an internal level shifter includes an input stage, a clock input stage, an output stage and a level shifting stage. The output stage generates an output signal based on an input signal received by the input stage and a clock signal received by the clock input stage. The level shifting stage shifts-up the voltage level of the output signal.

Abstract: A virtual zero delay unidirectional high voltage logic to low voltage CMOS logic voltage level translator can be achieved using a capacitive voltage divider coupled with the standard protection diodes commonly incorporated in low side logic (e.g. Xilinx Spartan-3E FPGA's). The complete voltage level translator will work equally well on frequencies from DC up to the rated operational frequency of the driver and receiver. Load side parasitic CMOS input capacitance in this case is ironically an asset rather than a liability since it can be used effectively as one element of the capacitive voltage divider. High voltage logic (e.g. 0 to 5V) can thus interface to lower voltage CMOS logic (e.g. 2.5V or 3.3V) with a minimum of additional external components and with virtually zero time delay.

Abstract: A high-voltage selecting circuit generates an output voltage with no voltage drop by means of an auxiliary NMOS transistor turning on the corresponding selecting PMOS transistor of the high-voltage selecting circuit when the voltage levels of a first input voltage and a second input voltage are equal. In addition, when one of the first input voltage and the second input voltage is higher than the other one, the high-voltage selecting circuit avoids the leakage current by means of an auxiliary PMOS transistor turning off the corresponding selecting PMOS transistor of the high-voltage selecting circuit. In this way, the high-voltage selecting circuit can correctly generate the output voltage according to the first input voltage and the second input voltage, and avoid the leakage current at the same time.

Abstract: Methods and apparatus provide for voltage level shifting with concurrent synchronization. The apparatus includes level shifting logic that in response to a non-level shifted clock signal from a first voltage domain, provides level shifted concurrently synchronous differential data signals in a second voltage domain based on pre-level shifted differential data signals from the first voltage domain. The first voltage domain may be, for example, a core logic voltage domain in which core logic operates. The second voltage domain may be, for example, an input/output (I/O) voltage domain in which an I/O buffer operates. The voltage level of the level shifted concurrently synchronous differential data signals is shifted from the pre-level shifted differential data signals, and the timing of the level shifted concurrently synchronous differential data signals is concurrently referenced to the non-level shifted clock signal.

Abstract: In embodiments of the present invention, the problems of poor low-frequency response, slow speed, high cost and high power consumption in conventional voltage translators are addressed by processing high frequency and low frequency components of an input signal separately in two parallel stages without the use of large passive components or slow devices. At the output, the processed high frequency and low frequency components are seamlessly merged at a combining stage that maintains the integrity of the frequency response over the complete translator bandwidth.

Abstract: A level shifter has at least one of either a pull up or a pull down circuit. The circuit is made of electronic components with reliability limits less than a maximum signal level output by the level shifter. The level shifter also has a timing circuit coupled to at least on of either the pull up or pull down circuit. The timing circuit controls a time of application of an input signal to at least one of either the pull up or pull down circuit preventing a terminal to terminal signal level experienced by the electronic components exceeding the reliability limits.

Abstract: A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) is disclosed, the voltage level shifting circuit comprises a pair of cross coupled PMOS transistors connected to the VCCH, a NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a first blocking device coupled between the drain of the first PMOS transistor and a drain of the first NMOS transistor, the first blocking device being configured to conduct active current when the first signal is in static state or transitions from a logic HIGH to a logic LOW, and the first blocking device being configured to shut off active current when the first signal transitions from the logic LOW to the logic HIGH.

Abstract: A voltage level translator circuit has a digital logic circuit having a digital logic signal at least one high-voltage capacitor having a first and second connection, wherein one of the first and second connections is electrically coupled to the digital logic signal, and a cross-coupled inverter pair having, the output of at least one inverter of the pair electrically coupled to the other connection of the at least one high-voltage capacitor.

Abstract: A microprocessor control unit (MCU) is mounted on a printed circuit board. The MCU includes first and second clocked serial interface (CSI) circuits. The first CSI circuit is configured to serially transmit a first xCP packet to a first encoder circuit, which in turn is configured to generate an encoded first xCP packet as a function of the first xCP packet and a first clock signal. A first low voltage differential signal (LVDS) circuit is coupled to the first encoder circuit and configured to serially receive the encoded first xCP packet therefrom. The first LVDS circuit is configured to generate a first differential signal as a function of the encoded first xCP packet.

Abstract: An output stage includes a system input and a system output, a first transistor having a first control input and a first controlled path, and a second transistor having a second control input and a second controlled path. The second controlled path is in series with the first controlled path and the system output. A first current-controlled voltage source has an input that is electrically connected to the system input. The first current-controlled voltage source has an output that is electrically connected to the first control input of the first transistor. A second current-controlled voltage source has an input that is electrically connected to the system input. The second current-controlled voltage source has an output that is electrically connected to the second control input of the second transistor.

Abstract: An integrated circuit includes multiple power domains. Supply current switch circuits (SCSCs) are distributed across each power domain. When a signal is present on a control node within a SCSC, the SCSC couples a local supply bus of the power domain to a global supply bus. An enable signal path extends through the SCSCs so that an enable signal can be propagated down a chain of SCSCs from control node to control node, thereby turning the SCSCs on one by one. When the domain is to be powered up, a control circuit asserts an enable signal that propagates down a first chain of SCSCs. After a programmable amount of time, the control circuit asserts a second enable signal that propagates down a second chain. By spreading the turning on of SCSCs over time, large currents that would otherwise be associated with coupling the local and global buses together are avoided.

Abstract: In one aspect, a level shifter for shifting a voltage level from a first voltage level to a second voltage level and having a predictable power-up state is provided. The level shifter comprises a first input and a second input forming a differential input to receive signals at the first voltage level, a first output and a second output forming a differential output to provide output signals at the second voltage level, and at least one circuit element coupled between the differential input and the differential output to pull the first output to a lower voltage level than the second output during power-up so that the level shifter powers-up in a desired state.

Abstract: The present invention provides a display device which can achieve the high breakdown voltage proof property, the enhancement of reliability or the expansion of the designing/process tolerance of transistors by the improvement of a circuit. A display device includes a plurality of pixels and a drive circuit which drives the plurality of pixels.

Abstract: A level shifter for a flat panel display device includes: first and second transistors that are different type transistors and serially coupled between first and second power supplies, the second power supply for supplying a lower voltage power than the first power supply; a first capacitor between gate electrodes of the first and second transistors; an input line for a first input signal coupled to the gate electrode of the first or second transistor; a third transistor between a second electrode of the first capacitor and a third power supply, the third transistor having a gate electrode coupled to an input line of a second input signal; and a fourth transistor between the second electrode of the first capacitor and the third transistor, the fourth transistor having first and gate electrodes that are coupled to the second electrode of the first capacitor, such that the fourth transistor is diode-connected.

Abstract: A system having an input and output buffer includes a dynamic driver reference generator to generate dynamic driver reference signals based on a data signal and an IO buffer supply voltage, a level shifter to generate level shifted signals based, in part, on the dynamic driver reference signals, and a driver having at least one stress transistor. The driver dynamically adjusts a voltage across the stress transistor based on at least one of dynamic driver reference signals, the level shifted signals, and a current state of an IO pad.

Abstract: A level shifter receives an input signal of either a first lower voltage or a first upper voltage which form a voltage pair, and level-shifts the input signal to output an output signal of either a second lower voltage or a second upper voltage. An SR flip-flop generates an output signal which is switched to the second upper voltage upon receiving a positive edge via its set terminal, and is switched to the second lower voltage upon receiving a positive edge via its reset terminal. An AND gate generates the logical AND of a feedback signal having the inverted logical level of the output signal of the SR flip-flop and the input signal, which is output to the set terminal of the SR flip-flop. A NOR gate generates the logical NOR of the feedback signal and the input signal, which is output to the reset terminal of the SR flip-flop.

Abstract: CMOS circuitry having mixed threshold voltages is disclosed. Circuits may be implemented using PMOS transistors, NMOS transistors, or both. For at least one given type of transistor (PMOS or NMOS), a circuit includes at least one transistor configured to switch at a first nominal threshold voltage and at least one transistor configured to switch at a second nominal threshold voltage. The different threshold voltages among a given transistor type are realized by varying the thickness of the transistor gate oxides and/or the channel dopant density, for example.

Abstract: An electronic clamp is provided for an integrated circuit having a first voltage island (1) to which an output signal (clamp out) of the clamp is applied and a second voltage island (2) operative to produce an input signal (clamp in) to the clamp, where power to the second voltage island can be switched off to save power. The clamp comprises a latch (22) which stores or retains the clamp value (0 or 1) of the input signal (clamp in) during a reset period and clamps the output signal (clamp out) to the stored or retained value in response to a clamp enable signal, (clamp in) in order to protect the first voltage island from a non-stabilised input signal.

Abstract: Apparatus and methods efficiently provide compatibility between CMOS integrated circuits and voltage levels that are different from that typically used by modern integrated circuits. For example, backwards compatibility can be desirable. Older signaling interfaces operate at different voltage levels than modern CMOS integrated circuits and conventional circuits to interface with these other signaling interfaces exhibit relatively high power consumption. In the context of a transmitter with a P-type substrate, an output driver is embodied in a deep N-well with retrograde P-wells and is biased with voltage biases that can float with respect to the VDD and VSS supplies provided to the CMOS integrated circuit. In the context of a receiver with a P-type substrate, a portion of a receiver is embodied in a deep N-well and biased with floating voltage biases such that the receiver is compatible with signaling received from a signaling technology with disparate voltage levels.

Abstract: A level shifting circuit including a driving circuit, a reset circuit, a coupling circuit and an output-stage circuit is provided. The driving circuit, controlled by the input signal, controls the first driving signal having a high voltage level in the first period and controls the first driving signal having a low reference level in the second period. The reset circuit, controlled by the first driving signal in the first period, resets the second driving signal having the low reference level. The coupling circuit, controlled by the falling edge of the input-inversed signal, controls the second driving signal having a low voltage coupling level in the second period. The output-stage circuit, controlled by the first and the second driving signal, controls the output signal having a high voltage level in the second period and controls the output signal having a low voltage level in the first period.

Abstract: A semiconductor integrated circuit device including an I/O circuitry capable of low-voltage high-speed operation at low cost is provided. In the I/O circuitry, when an I/O voltage (for example, 3.3 V) is lowered to a predetermined voltage (for example, 1.8 V), portions causing a speed deterioration are a level conversion unit and a pre-buffer unit for driving a main large-sized buffer. In view of this, a high voltage is applied to a level up converter and a pre-buffer circuit. By doing so, it is possible to achieve an I/O circuitry capable of low-voltage high-speed operation at low cost.

Abstract: A power supply system for providing power to a powered device over a communication link includes a power supply device capable of supporting an AC disconnect-detect function. The power supply device has a controller, an output port coupled to the communication link, and a bipolar junction transistor (BJT) controlled by the controller to provide power to the output port. The BJT may be turned off to present a high impedance required to support the AC disconnect-detection function.

Abstract: The invention is directed to an interface circuit for bridging voltage domains. The interface circuit receives an input signal, having a larger voltage domain, and safely provides the signal to an electronic device which has a smaller voltage domain. The interface circuit may include a transistor configured as a source follow so that an output of the transistor follows the input of the transistor. A blocking voltage may be provided at the input of the transistor to provide a voltage bias, blocking a range of input voltages to the transistor. The transistor may also have a blocking voltage at a drain terminal of the transistor, to block any output voltage above the blocking voltage.

Abstract: A level-shift circuit converts a first voltage level into a second voltage level different from the first voltage level. The level-shift circuit includes a first high-side signal detection circuit, a second high-side signal detection circuit, a drive circuit and electric current detection circuits. The first high-side signal detection circuit sets a logical voltage state of the second voltage level via a first capacitor. The second high-side signal detection circuit resets the logical voltage state of the second voltage level via a second capacitor. The drive circuit on-off drives a high-side switch connected to a low-side switch in series by a set signal of the first high-side signal detection circuit and a reset signal of the second high-side signal detection circuit. The electric current detection circuits detect an electric current flowing into or from the first and/or second capacitors.

Abstract: Circuit blocks and respectively convert high-voltage logic signals in which two logical values are expressed by a first signal potential and a second signal potential into low-voltage logic signals in which the two logical values are expressed by a third signal potential at least as large as the first signal potential and a fourth signal potential that is the third signal potential to which a positive voltage has been added and which is no greater than the second signal potential, and outputs the converted logic signals. The transistors in the circuit block are of the form of replacing the respective transistors of the circuit block with elements of opposite polarity, so that when the third signal potential is changed and operation of one of the circuit blocks and becomes difficult, the other operates normally. Consequently, stable level conversion can be accomplished.

Abstract: The invention discloses a power mesh arrangement method utilized in an integrated circuit having multiple power domains. The arrangement method includes: forming a first partial local power mesh according to a position of a first power domain; forming a second partial local power mesh according to a position of a second power domain; forming a global power mesh, utilized for providing powers needed by the first and the second power domains; coupling the first partial local power mesh to the global power mesh and the first power domain; and coupling the second partial local power mesh to the global power mesh and the second power domain.

Abstract: An input/output circuit includes an I/O node connected to a pull up and pull down circuit having a pull up and pull down transistors. Data is sent and received at through the I/O node. A level shifter provides voltages including a supply voltage and a high voltage higher than the supply voltage. A signal control circuit controls the voltage level applied to the pull up and pull down circuit. During a data input mode, data is received at the I/O node and the pull up transistor is biased at the high voltage to cut off the pull up transistor. During a data output mode, data is output at the I/O node and the pull down transistor pulls down the I/O node to ground when the output data is low, and the pull up transistor is activated when the output data is high.

Abstract: A voltage scale down circuit includes an input node configured to receive a voltage input within an input voltage range. At least two voltage followers are coupled to the input node. The voltage scale down circuit also includes at least two scalers. Each scaler is coupled to a respective voltage follower. An output node is coupled to the at least two scalers. Each voltage follower is configured to receive the voltage input. Each voltage follower is configured to supply a respective voltage for the voltage input within a narrower portion of the input voltage range. The output node is configured to supply a voltage output linearly related to the voltage input. An output voltage range of the voltage output is narrower than the input voltage range.