Abstract: According to various embodiments, a method of operating a two-wire digital bus includes applying a bias voltage to the two-wire digital bus at a first interface node, measuring a common mode voltage of the two-wire digital bus at the first interface node, and adjusting the bias voltage at the first interface node based on the measured common mode voltage.

Abstract: A thermal-type flow meter for representing a flow rate of air by the frequency of a periodic signal, wherein abnormalities in the waveform of an output signal due to frequency variation is prevented while high-frequency noise is suppressed. The thermal-type flow meter pertaining to the present invention is provided with a plurality of switching elements connected in parallel, and varies a delay width between the switching elements in accordance with variation of the frequency of a periodic signal for representing a flow rate.

Abstract: A circuit comprises an input terminal configured to receive an input signal. A high-side driver is configured to provide a high-side control signal to a high-side power transistor via a high-side terminal based on the input signal. A low-side driver is configured to provide a low-side control signal to a low-side power transistor based on the input signal. An interface is configured to couple the high-side terminal and the low-side terminal via a capacitor.

Abstract: A serial low-power inter-chip media bus communications link is deployed in apparatus having multiple Integrated Circuit devices. Communications capabilities of a device coupled to the communications link may be determined and configuration or framing message may be sent to the first device based on the capabilities. The messages may be transmitted on a primary data line of the communications link with a clock used to control timing of transmission on at least the primary data line. The communications capabilities can include information identifying a number of data wires supported by or coupled to the device. A first device may be configured to communicate with a second device over a secondary data line, which may be reserved for such direct communication. Communications on the secondary data line may be synchronized using the clock signal and may be controlled by a different protocol than the protocol used for the primary data line.

Abstract: In one embodiment, a node includes at least one core to independently execute instructions; a first host device to receive information from the at least one core and to include the information in a first packet of a first communication protocol; a selection logic coupled to the first host device to receive the first packet and to provide the first packet to a conversion logic or a first interface to communicate with a first device via a first interconnect of the first communication protocol; the conversion logic to receive the first packet under selection of the selection logic and to encapsulate the first packet into a second packet of a second communication protocol; and a second interface coupled to the conversion logic to receive the second packet and to communicate the second packet to a second device via a second interconnect of the second communication protocol. Other embodiments are described and claimed.

Abstract: Methods and systems for optoelectronics transceivers integrated on a CMOS chip are disclosed and may include receiving optical signals from optical fibers via grating couplers on a top surface of a CMOS chip, which may include a guard ring. Photodetectors may be integrated in the CMOS chip. A CW optical signal may be received from a laser source via grating couplers, and may be modulated using optical modulators, which may be Mach-Zehnder and/or ring modulators. Circuitry in the CMOS chip may drive the optical modulators. The modulated optical signal may be communicated out of the top surface of the CMOS chip into optical fibers via grating couplers. The received optical signals may be communicated between devices via waveguides. The photodetectors may include germanium waveguide photodiodes, avalanche photodiodes, and/or heterojunction diodes. The CW optical signal may be generated using an edge-emitting and/or a vertical-cavity surface emitting semiconductor laser.

Abstract: A cascode voltage generating circuit and method are provided. The circuit includes four switching elements. In a high voltage operation mode, the first and second switching elements, respectively, couple a first intermediate voltage input node to a first intermediate voltage output node, and a second intermediate voltage input node to a second intermediate voltage output node. In a low voltage operation mode, the third switching element couples the first and second intermediate voltage input nodes to a ground reference voltage level, and the fourth switching element couples the first and second intermediate voltage output nodes to a supply voltage level.

Abstract: A transceiver and an operation method thereof are provided. The transceiver includes a transmitter and a receiver. The transmitter is configured to receive an output reference signal to provide an output signal to a signal channel. The receiver is coupled to the signal channel to receive a receiving reference signal to provide a receiving signal. The receiver includes a comparator unit and a signal adjusting unit. The comparator unit is configured to compare a first signal and a second signal to obtain the receiving signal. The signal adjusting unit is coupled between the output reference signal, the receiving reference signal and the comparator unit to adjust a voltage level of at least one of the output reference signal and the receiving reference signal to obtain the first signal and the second signal.

Abstract: A differential driving circuit includes a source current source, a sink current source, an H-bridge circuit, an error detector unit and a circuit network. The H-bridge circuit is connected to the source current source and the sink current source, that has a first output terminal and a second output terminal, and that generates differential output from the first output terminal and the second output terminal. The error detector unit adjusts a common mode voltage at the first output terminal and the second output terminal of the H-bridge circuit by controlling at least one of the source current source and the sink current source. The circuit network is configured by resistors and capacitors connected to the first output terminal and the second output terminal of the H-bridge circuit.

Abstract: A memory module such as a DIMM includes two separate memories with corresponding data, address and control interfaces. Each separate memory core includes plural memory banks for corresponding portions of the data interface. The separate interfaces include separate byte strobes and control signals. The two memories may be separately powered or share power connection. The two memories may be disposed on a single semiconductor integrated circuit or separate semiconductor integrated circuit. The two memories may be connected to two external memory interfaces of a single data processor or to separate data processors.

Abstract: Systems and techniques for single-wire communications are described. A described system includes a host device, and a slave device coupled with the host device via a single-wire bus. The host device can be configured to transmit synchronization information based on transitions over the single-wire bus. The slave device can be configured to detect the transitions on the single-wire bus, determine timing information of the host device based on a first transition of the transitions and a second transition of the transitions, determine a predicted start time of a host sampling window based on the timing information, and determine, based on a predicted charging duration, whether to perform a charge operation before the predicted start time or after a predicted end time of the host sampling window. The charge operation can include drawing power from the single-wire bus to charge the device.

Abstract: A selected gate (SG) driver circuit, including a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, and a second PMOS transistor. A gate electrode of the first NMOS transistor is connected to a gate electrode of the first PMOS transistor, a source electrode of the first NMOS transistor being connected to a drain electrode of the third NMOS transistor, and a drain electrode of the first NMOS transistor being connected to a drain electrode of the first PMOS transistor and a gate electrode of the second NMOS transistor. A source electrode of the second NMOS transistor is connected to a source electrode of the third NMOS transistor, and a drain electrode of the second NMOS transistor being connected to a drain electrode of the second PMOS transistor and a gate electrode of the third NMOS transistor.

Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with dynamic gain control. More specifically, some embodiments of the present disclosure are directed to a buffer having a gain boost configuration and a current shunt circuit to control the gain of a respective gain boosting transistor of the gain boost configuration. The current shunt circuit and resulting gain are dynamically controlled by a gain control signal such that the buffer gain can be adjusted to within an acceptable range of the target gain for the current operating and device mismatch conditions. In one or more embodiments, the gain boost configuration with dynamic gain control can be deployed in a full differential implementation. Both analog and digital dynamic calibration and control techniques can be used to provide the gain control signals to multiple current shunt circuits and multiple buffers.

Abstract: The differential output buffer comprises the differential output circuit, and the bias voltage generation circuit that is the replica circuit of the differential output circuit. The bias voltage generation circuit generates, by the operational amplifier, the bias voltage for controlling currents respectively flowing in the first current source of the differential output buffer and the second current source of the bias voltage generation circuit such that the voltage of the third internal node between the third internal and external resistors and the third switch of the bias voltage generation circuit becomes equal to the reference voltage equal to the voltage of the first internal node when the first switch of the differential output buffer is in an ON state or equal to the voltage of the second internal node when the second switch of the differential output buffer is in an ON state.

Abstract: A tristate gate includes an output port and at least two transistors. Each of the transistors has at least a first and a second gate configured such that a high-impedance value (Z) on the output port is set by controlling the threshold voltage of at least one of the transistors.

Abstract: A multi-modal memory interface that supports each of current-mode and voltage-mode signaling by a memory controller with a memory which includes one or more memory devices. In a first type of system, the memory interface is configured to provide differential current-mode signaling from the memory controller to a first type of memory, and differential voltage-mode signaling from the memory to the memory controller. In contrast, in a second type of system, the memory interface is configured to provide single-ended voltage-mode signaling from the memory controller to the memory, and single-ended voltage-mode signaling from a second type of memory to the memory controller. To support these different types of systems, the memory controller couples different types of drivers to each I/O pad. The resulting capacitance is reduced by sharing components between these drivers. Moreover, in some embodiments, the memory interface is implemented using “near-ground” current-mode and voltage-mode signaling techniques.

Abstract: A semiconductor device is provided. The semiconductor device includes a driver circuit, a dummy circuit, and a control unit. The driver circuit is configured to provide a termination resistor at a signal transmission path. The driver circuit includes a plurality of resistors having at least two different types of resistor. The dummy circuit is electrically connected to the driver circuit and is configured to compensate for a mismatch between the at least two different types of resistors. The control unit is configured to control the dummy circuit, based on a result obtained by detecting the mismatch.

Abstract: A circuit includes a switching circuit, a node, and a tracking circuit. The switching circuit has a first terminal, a second terminal, and a third terminal. The node has a node voltage. The tracking circuit is electrically coupled to the third terminal and the node, and configured to receive the node voltage and generate a control voltage at the third terminal based on the node voltage.

Abstract: A memory controller includes logic to determine corresponding reference voltage values and delay values for one or more memory devices. The memory controller includes a command-address (CA) interface to send a command to a memory device to set a reference voltage value of the memory device to a test value, a data interface to write a data pattern to the memory device and read the data pattern from the memory device, and test reference voltage logic to perform a density check on at least a portion of the data pattern read from the memory device and determine whether the test value is a potential reference voltage value based on the density check. An operational reference voltage value selected from one or more potential reference voltage values may be used to determine a delay value.

Abstract: Described examples include sensing circuits and reference voltage generators for providing a reference voltage to a sensing circuit. The sensing circuits may sense a state of a memory cell, which may be a PCM memory cell. The sensing circuits may include a cascode transistor. Examples of reference voltage generators may include a global reference voltage generator coupled to multiple bank reference voltage generators which may reduce an output resistance of the voltage generator routing.

Abstract: An object is to prevent malfunction of a power device. In a semiconductor device for driving a power device for power supply, a buffer circuit and a level-shift circuit are configured by transistors having the same conductivity type. Furthermore, a capacitor is provided in the level-shift circuit, and a signal to be boosted is supplied to the capacitor and is boosted using capacitive coupling of the capacitor. Furthermore, a structure can be employed in which the signal is boosted in such a manner that, in the level-shift circuit, a capacitor is provided between a wiring for supplying a low power source potential and a wiring for supplying a potential to boost the signal so that a power transistor can be driven.

Abstract: According to one aspect of the present invention, the provided is a gate driving circuit, comprising: a first switch control circuit, being configured to be respectively coupled to each of the multiple stages of shift register units; a second switch control circuit, being configured to be respectively coupled to each of the multiple stages of shift register units. The first switch control circuit controls the multiple stages of shift register units to turn on in a forward sequence; the second switch control circuit controls the multiple stages of shift register units to turn on in a backward sequence.

Abstract: A drive circuit includes a duty cycle adjusting circuit that changes the duty cycle of a first signal; and a calculating circuit that with respect to signals that include the first signal for which the duty cycle has been adjusted and a second signal having a phase and amplitude that differ from that of the first signal, performs any one of subtracting one of the signals from the other signal and adding the signals.

Abstract: Disclosed is a high-swing voltage-mode transmitter or line driver. The transmitter can operate over a wide range of supply voltages. Increasing the available output swing merely involves increasing the supply voltage; the circuit adapts to maintain the desired output impedance. This allows for a tradeoff between output amplitude and power consumption. Another advantage of the proposed architecture is that it compensates for process, voltage, and temperature (PVT) and mismatch variations so as to keep rise and fall times matched. This feature reduces common-mode noise and hence EMI in systems in which the transmitter is used.

Abstract: A method of operating an input/output interface includes selecting one of a plurality of output driver circuits according to a mode selection signal, and outputting a data signal using the selected one of the plurality of output driver circuits. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an on-die termination (ODT) circuit included in the input/output interface according to the mode selection signal. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an ODT circuit included in the input/output interface according to the mode selection signal.

Abstract: The present disclosure provides embodiments of an improved current steering switching element for use in a digital to analog (DAC) converter. Typically, each current steering switching element in the DAC converter provides a varying set of currents for converting a digital input signal. Generally, the switches and drivers in the current steering switching elements are scaled down proportionally to the current being provided by the current steering switching element according to a ratio as less and less current is being driven by the switching element in order to overcome timing errors. However, device sizes are limited by the production process. When a switch is not scaled proportionally to the current, settling timing errors are present and affects the performance of the DAC. The improved current steering switching element alleviates this issue of timing errors by replacing the single switch with two complementary current steering switches.

Abstract: A contactless card includes an inductive circuit configured to send and receive signals, a rectifier circuit coupled to the inductive circuit and configured to generate a DC voltage from an AC voltage generated by the inductive circuit, a clamp circuit configured to limit the DC voltage, a regulator circuit configured to regulate the DC voltage and a control circuit configured to selectively enable and disable the clamp circuit and the regulator circuit.

Abstract: Continuous-time linear equalization of received signals on multiple wire channels while maintaining accurate common mode signal values. Multiwire group signaling using vector signaling codes simultaneously transmits encoded values on multiple wires, requiring multiple receive signals to be sampled simultaneously to retrieve the full transmitted code word. By misaligning transitions on multiple wires, skew introduces a transient common mode signal component that is preserved by using frequency-selective common mode feedback at the receiver to obtain accurate sampling results.

Abstract: A pre-emphasis circuit is disclosed. In one embodiment, a pre-emphasis circuit includes a first signal path configured to receive a first signal and a second signal path configured to receive the first signal. The second signal path includes a re-timing circuit configured to delay the first signal by a pre-determined amount to produce a second signal. The pre-emphasis circuit also includes a summing circuit coupled to receive the first signal from the first signal path and the second signal from the second signal path. The summing circuit is configured to add the second signal to the first signal to produce a third signal, wherein the third signal is logically equivalent to the first signal. The third signal has a first magnitude for a first portion of a bit-time of the first signal, and a second magnitude for a second portion of the bit-time of the first signal.

Abstract: A single-ended comparator is disclosed herein. The comparator may be implemented with low-voltage semiconductor devices that are capable of operating with high-voltage signals at an input. The single-ended comparator may be integrated in a larger circuit to receive and detect information provided on the input at voltage levels higher than the levels supported by the rest of the circuit, and transfer the information in the received signal for use by the rest of the circuit.

Abstract: A display and an operating method thereof are provided. The display includes a display panel, a timing controller, and a plurality of source drivers. The timing controller has a plurality of signal output terminals. The source drivers are coupled to the timing controller and the display panel. The timing controller outputs a plurality of training packets to the source drivers. When the source drivers lock a clock of the timing controller according to the training packets, the timing controller outputs a plurality of control packets and a plurality of color data packets to the source drivers. The source drivers respectively output a plurality of pixel voltages corresponding to the color data packets to the display panel according to the corresponding control packets. The training packets, the control packets, and the color data packets are serially transmitted to the source drivers via the signal output terminals.

Abstract: An intelligent current drive is disclosed that couples an active current source to a bus line to increase the rate of pull-up and decouples the active current source from the bus line prior to reaching the desired pull-up voltage.

Abstract: An active termination circuit for a differential receiver includes a first receiver element configured to receive a first component of a differential signal, a second receiver element configured to receive a second component of a differential signal, a common mode measurement element configured to receive the differential signal and generate a transmit common mode signal (Vcm) representing an average value of the differential signal, and a receiver (RX) common mode signal node. The termination circuit also comprises an active element configured to receive the transmit common mode signal (Vcm) and provide an output to the receiver common mode signal node, the output configured to drive the value of the signal at the receiver common mode signal node to the value of the transmit common mode signal (Vcm), and a capacitive element coupled to the receiver common mode signal node in parallel with the active element.

Abstract: A apparatus, having a processing system and an input buffer coupled with both the processing system and one of two IO pads, and a reference buffer coupled to both the input buffer and the second of the IO pads such that the reference generator controls the input threshold of the input buffer in response to an analog voltage received from an external circuit on the second of the IO pads.

Abstract: A voltage mode driver circuit able to achieve a larger voltage output swing than its supply voltage. The voltage mode driver circuit is supplemented by a current source or “current booster.” The circuit includes a first inverter, a second inverter, and a current source. The first inverter receives a first input and outputs a signal at a node. The second inverter receives a second input signal and outputs an inverted second input signal at the same node. The current source provides current to the node via a first switch, the first switch receiving an input at a first input where the voltage output swing at the node is larger than a power supply voltage applied to the current source. The voltage mode driver circuit uses a stable power supply voltage using a power amplifier with feedback.

Abstract: Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.

Abstract: The present invention relates to the use of cyanocinnamic acid derivatives as a matrix in the MALDI mass spectrometry of an analyte.

Abstract: A driver circuit for a digital signal transmitting bus includes a main switch. The main switch is connected to the bus, is controllable by the digital signal to be transmitted, and has one on-switching state in which it has maximum electrical conductivity, one off-switching state in which it has minimum electrical conductivity and at least one intermediate switching state with an electrical conductivity between the minimum and maximum conductivity. The digital signal has a first logic state and a second logic state, the first logic state controls the main switch to be in the on-switching state and the second logic state controls the main switch to be in the off-switching state. The main switch is in the intermediate switching state during switching from the on-switching state to the off-switching state and/or vice versa.

Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including first and second transmitter-receivers that execute transmission and reception of data through a signal line. The first transmitter-receiver includes a first termination circuit that includes a first resistor and a first switch, the first resistor being provided between a first power supply terminal and the signal line, the first switch controlling a current flowing through the first resistor to be turned on and off, and a control circuit that outputs a first control signal to the first termination circuit so that the first switch is turned on when the first transmitter-receiver receives data, the first switch is turned off when the first transmitter-receiver transmits the data, and the first switch is continuously on during a first predetermined period after receiving the data when the first transmitter-receiver further receives another data after receiving the data.

Abstract: A termination circuit for a plurality of memories controlled by a controller is provided. The termination circuit includes a plurality of drivers, a plurality of resistors and a plurality of capacitors. Each of the drivers is coupled to the memories via a transmission line. Each of the resistors is coupled to the corresponding driver via the corresponding transmission line. Each of the capacitors is coupled between the corresponding resistor and a reference voltage. The controller is coupled to the memories via the drivers, and the controller provides a specific code to one of the drivers when a quantity of logic “0” and a quantity of logic “1” transmitted to the memories via the transmission line corresponding to the one of the drivers are unbalanced, so as to adjust a termination voltage of the capacitor corresponding to the one of the drivers.

Abstract: A low voltage differential signal driving circuit including positive and negative differential output terminals, an automatic level selector, an output level detector and a transition accelerator. The positive and negative differential output terminals provide a transmission interface with a differential output signal for transmission of a data signal. The automatic level selector outputs a reference voltage corresponding to the transmission interface. The output level detector generates a low-high (or high-low) transition acceleration control signal based on the data signal, the reference voltage, and VTXP signal at the positive differential output terminal (or VTXN signal at the negative differential output terminal).

Abstract: Disclosed are a terminating resistance generation device for differential input mode communication and a differential input mode communication device. The terminating resistance generation device for differential input mode communication according to the present invention includes: a first circuit unit including a first ground terminal and operating only when the first ground terminal is connected to a ground; a second circuit unit including a second ground terminal and operating only when the second ground terminal is connected to the ground; and a terminating resistance generating unit generating terminating resistance when one of the first ground terminal and the second ground terminal is not connected, and as a result, only one of the first circuit unit and the second circuit unit operates.

Abstract: An integrated circuit comprising a first circuit and a second circuit. The first circuit may be configured to generate a plurality of complementary outputs based upon a plurality of inputs, a first control signal, and a second control signal. The plurality of inputs may be received in parallel in a first mode and as a serial bit stream in a second mode. The second circuit may be configured to generate a plurality of outputs in response to a third control signal and a fourth control signal.

Abstract: A system and process overcomes the influence of induced current and/or capacitance in wires and, more particularly, reduces and overcomes induced current and/or capacitance cross-talk between neighboring wire-bonds. A change or toggle in each of a plurality of outputs from a circuit is determined. The change determined for one selected output is compared with the change determined for neighboring outputs. When the change for the neighboring outputs is both the same as that of the selected output, the power of the output or the slew rate of an amplifier that receives the selected output is altered so that the output is increased. When the change for the neighboring outputs is both the opposite of that of the selected output, the power of the output or the slew rate of an amplifier that receives the selected output is altered so that the output is decreased.

Abstract: The invention provides a bidirectional level shifter which includes: a first signal terminal; a second signal terminal; a first switch, coupled between the first signal terminal and ground; an inverter receiving a signal from the first signal terminal; a Schottky diode including an anode and a cathode, the anode receiving a signal from the second signal terminal; a second switch, coupled between the cathode of the Schottky diode and the ground; a comparing circuit, comparing a reference voltage and a voltage at the second signal terminal to control the first switch, wherein the reference voltage is lower than a forward bias voltage of the Schottky diode; a first voltage source coupled to the first common node; and a second voltage source coupled to the second common node.

Abstract: A power supply switch circuit according to an aspect of the present invention includes a first switch element that is connected between a first power supply line and a second power supply line and switches connection and disconnection between the first power supply line and the second power supply line according to a first enable signal; a second switch element that is connected between the first power supply line and the second power supply line and switches connection and disconnection between the first power supply line and the second power supply line; and a switch control circuit that includes at least one logic gate supplied with power from the second power supply line and controls the second switch element. The switch control circuit controls the second switch element based on a second enable signal supplied to the switch control circuit and on a voltage of the second power supply line.

Abstract: A calibration circuit includes an amplifier, a current steering digital-to-analog converter (DAC), a comparator, a slew calibration network, and an on-die termination (ODT) network. The amplifier generally has a first input, a second input, and an output. The first input generally receives a reference signal. The current steering digital-to-analog converter (DAC) generally has a first input coupled to the output of the amplifier, a first output coupled to the second input of the amplifier, and a second output coupled to a circuit node. The comparator generally has a first input receiving the reference signal, a second input coupled to the circuit node, and an output at which an output of the calibration circuit may be presented. The slew calibration network is generally coupled to the circuit node and configured to adjust a slew rate of the calibration circuit. The on-die termination (ODT) network is generally coupled to the circuit node.

Abstract: Method and system for configuring a serial interface. The system includes one or more input nodes each coupled to a corresponding serial bus. One or more output nodes are coupled to a respective serial bus, each output node having a respective driver. A voltage detection circuit determines the voltage at a configuration node. Mode of serial bus operation is based on the voltage level detected at the configuration node. In at least one mode of serial bus operation, the configuration node is used as a mode select input and power source for at least one output driver.

Abstract: A circuit includes an input stage configured to receive a regulated input signal and generate an input stage output signal in response to the regulated input signal. An isolation stage can be configured to pass the input stage output signal to a buffered output node. The isolation stage receives feedback from the buffered output node to deactivate the buffer input stage if transient voltages are generated at the buffered output node. An output stage can be configured to provide current to the buffered output node in response to the regulated input signal.

Abstract: An adjustable impedance circuit includes a calibration module, an impedance module, a first switch module and a second switch module. The calibration module is arranged to generate a calibration signal. The impedance module has a plurality of impedance elements. The first switch module is coupled to the calibration module, and is arranged to receive the calibration signal and make a first portion of the impedance elements be selectively coupled between a differential input port and at least one reference voltage according to the calibration signal. The second switch module is coupled to a common-mode voltage output node, and is arranged to receive a control signal and make a second portion of the impedance elements be selectively coupled between the common-mode voltage output node and the differential input port according to the control signal.