Abstract: Because there are different voltages at two current output terminals of a current divider, the voltages at the current input terminals of two current switch circuits are not affected mutually even with a large amplitude of local signals. Accordingly, the performance of a quadrature mixer can be enhanced by increasing the amplitude of the local signals. Bias currents are supplied to the two current switch circuits through the current divider from a common DC current source which essentially supplies a bias current to a V/I converter and, therefore, power consumption is reduced.

Abstract: A wavelength tunable mode-locked laser system including a complex laser cavity comprising a broadband reflective mirror at one end and a wavelength chirped selective mirror at the other end. The system further includes a gain element and a low finesse Fabry-Perot etalon element inside the laser cavity. The gain element may be a semiconductor laser chip, with a broadband high reflection coating at one end and a partially reflecting coating at its other end. The gain element has a well-defined length, such that its longitudinal modes match a required optical frequency grid. The system also includes an active modulation element applied externally on said complex laser cavity to provide mode-locking of a specific cavity length among said defined predetermined cavity lengths, such that all possible optical frequencies emitted by the laser system are stabilized to the linear grid dictated by the Fabry-Perot longitudinal modes, that could be in accordance with the International Telecommunications Union Standards.

Abstract: A body diode comparator circuit for a synchronous rectified FET driver including a sample circuit and a comparator. The FET driver has a phase node coupled between a pair of upper and lower switching FETs and is responsive to a PWM signal having first and second phases for each cycle. The sample circuit samples an initial voltage of the phase node during the first phase of the PWM signal and provides a sum voltage indicative of the initial phase voltage added to the voltage level of the phase node during the second phase of the PWM signal. The comparator compares the sum voltage with a predetermined reference voltage and provides an output indicative of an activation state of the lower FET during the second phase of the PWM signal. The FET driver turns on the upper FET when the comparator indicates that the lower FET is off.

Abstract: A low-cost approach to voltage scaling is realized by latching the output of a propagation delay detector, and inputting the latched output to a string digital-to-analog (DAC) converter. The string DAC generates a DC voltage in response to the latched values, which is fed back to the propagation delay detector.

Abstract: A DLL (delay locked loop) circuit for outputting a phase lock signal having a predetermined phase relationship with an input signal. The DLL circuit has: a functional block having a constant-current source; and bias generator for generating a constant current source bias signal for controlling the constant current source of the functional block, the bias generator comprising a bias control which changes the bias signal according to the frequency of the input signal.

Abstract: A receiver comprising an input for receiving a first signal, said receiver further comprising a local oscillator for generating a periodical signal. The receiver further comprises a mixer for generating a third signal representative for a combination of a second signal and the periodical signal. The receiver is characterized in that it further comprises a voltage to current converter for receiving the first signal and generating the second signal as a current indicative for the first signal. The mixer comprises a plurality of controllable switches. The receiver further comprises a variable gain current to voltage converter (VGIV) coupled to the passive mixer, the VGIV receiving the third signal and generating a first voltage signal, said first voltage signal being in a linear relationship with the third signal.

Abstract: A Pulse Interval to Voltage Converter (PIVC) and conversion method thereof is revealed. The PIVC comprises a clock generator, a counter, a latch, a digital-to-analog converter (DAC), a delay unit, a frequency regulator and an underflow protection unit. New components, such as the delay unit, the frequency regulator and the underflow protection unit, are incorporated into the present invention, unlike the conventional art. The delay unit is intended for the programming of the default duration of delay, so as to delay the time for the counter to reset to zero, and in consequence regulate the baseline of the output voltage. The frequency regulator can regulate the clock generation frequency of the clock generator, so as to regulate the resolution of the output voltage. The underflow protection unit turns back external signals while the delay unit is operating, so as to minimize interference from noise.

Abstract: A write compensation circuit of a recording device includes a first delay portion driven by a first driving voltage, for receiving a clock signal, delaying the clock signal by a first delay time, and outputting the delayed clock signal, and a voltage supplying portion for supplying the first driving voltage to the first delay portion in such a manner that the first delay time is substantially equal to a clock period of the clock signal.

Abstract: A clock signal duty cycle control circuit is provided that receives an incoming signal from a clock signal input source and generates an improved output clock signal having an accurately controlled duty cycle. The circuit controls the duty cycle of the output clock signal by comparing the incoming signal to a reference value in a comparator. The reference value is derived from a reference charge stored on a capacitor. The reference charge is built up in the capacitor using the currents from a current source and a current sink, which are controlled using translated output signals from the comparator.

Abstract: A logic system with adaptive supply voltage control comprising a logic circuit clocked by a clock signal from a clock generating circuit and a voltage conversion circuit for generating a dynamically regulated supply voltage for powering the logic circuit. A critical path delay of the logic circuit is designed to be equal to or shorter than a period of the clock signal. The voltage conversion circuit dynamically regulates the supply voltage of the logic circuit based on a bias voltage of the clock generating circuit. According to the invention, the power consumption is effectively minimized while ensuring the logic circuit to function correctly throughout all conditions.

Abstract: A frequency to frequency de-randomizer circuit having means for smoothing a current which comprises a diode filter configured so as to have a time constant which changes in response to changes in the current thus providing a rapidly responding, real time, fluctuation free signal which is optimised for measurement and display from a very low power circuit.

Abstract: A clock signal duty cycle control circuit is provided that receives an incoming signal from a clock signal input source and generates an improved output clock signal having an accurately controlled duty cycle. The circuit controls the duty cycle of the output clock signal by comparing the incoming signal to a reference value in a comparator. The reference value is derived from a reference charge stored on a capacitor. The reference charge is built up in the capacitor using the currents from a current source and a current sink, which are controlled using translated output signals from the comparator.

Abstract: A circuit arrangement for generating specific waveforms includes a controllable voltage transformer circuit for generating an output signal (VOUT) with a specific waveform, which increases the voltage of its output signal depending on a first control signal (VH) or reduces it depending on a second control signal (VL). The arrangement also includes a control unit that generates the first and second control signal (VH, VL) for the voltage transformer circuit depending on a reference signal (VREF) in the form of an open-loop control or in the form of a closed-loop control.

Abstract: A pipelined data converter current biasing system employs a frequency-to-voltage converter (FVC) operational to convert a plurality of desired sampling frequencies to a plurality of output voltages and a voltage-to-current (V to I) converter operational to convert the plurality of output voltages to a plurality of bias currents. The plurality of bias currents function to bias the data converter operational amplifiers such that the data converter power consumption is dependent on the plurality of sampling frequencies in a way that optimizes power consumed by the data converter with respect to the sampling frequency.

Abstract: A dual output capacitance interface circuit (100) based on switched capacitor circuits and charge subtraction technique provides both voltage output (104) and frequency output (106). The circuit is programmable independently with sensitivity and offset adjustment, and is insensitive to fixed stray capacitance. Temperature compensation methods are described.

Abstract: In the process for converting a frequency signal to a DC voltage according to the invention a first and a second output voltage signal (UA1, UA2) are generated from the frequency signal. Each of the output voltage signals is a sequence of rectangular pulses the pulse sequence frequency of which is equal to a frequency f of the frequency signal. These are converted with a first and a second lowpass filter to a first DC voltage signal and a second DC voltage signal, respectively, with the second DC voltage signal being used to influence the pulse width T0 of the rectangular pulses of at least the first output voltage signal. This makes it possible to build a simple frequency-to-voltage converter using cost-effective standard monoflops in which a largely linear correlation between frequency f of the frequency signal and the magnitude of the first DC voltage signal is realized in a simple manner.

Abstract: An integrated circuit card receives power in the form of a radio frequency signal and includes a voltage generator that produces a first power supply voltage. The card also includes a voltage booster circuit for producing a high voltage that receives the first power supply voltage at a first supply input terminal. The voltage booster circuit also receives a second power supply voltage higher than the first power supply voltage at a second supply input terminal.

Abstract: In a frequency-voltage conversion circuit, integrating means gives a predetermined slope for rising or falling of a rectangular pulse signal. First comparing means compares an output value of the integrating means with a threshold value, and produces a pulse signal line having a pulse width corresponding to frequency of the rectangular pulse signal. Storing means stores and retains the threshold value. Smoothing means smooths the pulse signal line, and produces a voltage value corresponding to the frequency of the rectangular pulse signal. Second comparing means compares the voltage value with a reference voltage, and charges and discharges electric charge for the storing means on the basis of the comparison result.

Abstract: A frequency-voltage conversion circuit 21 receives a clock CLK as an input and provides a voltage IVdd in accordance with the frequency of the clock as an output. The input and output characteristic of the frequency-voltage conversion circuit 21 is adjusted to substantially match a given input and output characteristic.

Abstract: An electronic circuit generates a bias current that is proportional to a frequency of a reference clock signal in a switched capacitor circuit. The electronic circuit includes a capacitive circuit selectively coupled to a transistor supplied by a voltage reference circuit. During a first phase the capacitive circuit is charged by a current from the transistor, and during the second phase the capacitive circuit is discharged to ground. The duration of each phase is related to the reference clock signal. The average current corresponds to a bias signal and is filtered to reduce ripple in the bias signal before the bias signal is received by the switched capacitor circuit. The capacitive circuit is configured with a first and second capacitor arranged in a complimentary out-of-phase configuration. During a first phase, the first capacitor is charged and the second capacitor is discharged. During the second phase, the second capacitor is charged and the first capacitor is discharged.

Abstract: To control the transconductance of a transconductor, its voltage input terminal (Vin2) is connected to the base of a first and a second transistor (Q21, Q22) via respective capacitors (C21, C22). The interconnection points between the capacitors (C21, C22) and the respective base are connected to the respective control voltage terminal (Vreg2+, Vreg2−) of the transconductor via a first and a second resistor (R21, R22), respectively. The emitters of said first and second transistors (Q21, Q22) are inter-connected, and the interconnection point is connected to a ground terminal via a third resistor (R23). The collector of the first transistor (Q21) is connected to the current output terminal (Iout2) of the transconductor, and the collector of the second transistor (Q22) is connected to the supply voltage terminal (Vcc2) of the transconductor.

Abstract: A impedance-to-voltage converter for converting an impedance of a target to a voltage is described which comprises an operational amplifier (OP), a coaxial cable consisting a signal line and shielding element(s), and an AC signal generator. A feedback impedance circuit is connected between output and inverting terminals of the OP, and whereby a non-inverting terminal and the inverting terminal are an imaginal-short condition. One end of the signal line is connected to the inverting input terminal of the OP and the other end is connected to one electrode of the target and the AC signal generator is connected to the non-inverting input terminal of the OP. The shielding element comprises at least one shielding layer surrounding the signal line and is connected to the non-inverting input terminal of the OP, and thus the signal line and the shielding layer are the same voltage due to the imaginal-short of the input terminals of the OP, resulting in reduction of noise on the signal line.

Abstract: The voltage converting circuit 10 includes a standby VDC, an active VDC which operates when the semiconductor integrated circuit device is activated and has current drivability larger than that of standby VDC, and a drivability control circuit. Drivability control circuit generates a control signal in accordance with operational frequency of the semiconductor integrated circuit device. Current drivability of the active the VDC is controlled in accordance with the operational frequency by the control signal.

Abstract: A decoding apparatus for transmitting a high voltage signal includes a final decoder for switchably transmitting a transmission signal. The final decoder has a switching device that has at least one depletion-mode-type field effect transistor and/or field effect transistor having a low threshold voltage (i.e., 0.1 to 0.4 V), in particular, a low VT field effect transistor. A transmission signal line supplies the transmission signal to the decoder, a driver signal line supplies a driver signal to the decoder, and an output signal line outputs an output signal from the decoder. The driver signal line applies the driver signal to the gate line, the transmission signal line applies the transmission signal to the source line. The field effect transistor is configured to selectively connect the output signal to the output signal line device through the output in response to a reset of the driver signal. The configuration reduces the likelihood of channel degradation and of failure in the field effect transistor.

Abstract: The present invention relates to a charge pump circuit which can vary an oscillation frequency for charge pumping in proportion to a charge consumption amount. The charge pump circuit includes: a voltage divider dividing a boosting voltage to a predetermined level; a voltage level sensing unit sensing a voltage difference between a divided voltage outputted from the voltage divider and a reference voltage, and outputting a control voltage corresponding to the sensed voltage difference; an oscillator circuit varying an oscillation frequency in accordance with the control voltage outputted from the voltage level sensing unit; and a charge pump performing a pumping operation in accordance with the output from the oscillator circuit, and outputting a boosting voltage.

Abstract: A synchronous rectifier circuit (10) includes a polarity comparator (14) that generates a signal to a driver circuit (16) for controlling the voltage at the gate of a power MOSFET (60). The power MOSFET (60) is switched to operate in the conduction mode and short out a parasitic diode (62) when the diode is forward biased. The power MOSFET (60) is switched to operate in the nonconduction mode when the parasitic diode (62) is reverse biased. A bias supply circuit (12) uses a capacitor (70) to generate a regulated internal bias that provides power to the polarity comparator (14) and to the driver circuit (16). The internal bias allows the power MOSFET (60) to provide a current conduction that is substantially isolated from the changes in voltage levels at the terminals (64, 66) of the synchronous rectifier circuit (10).

Abstract: In a frequency-voltage conversion circuit, integrating circuitry gives a predetermined slope for rising or falling of a rectangular pulse signal. First comparing circuitry compares an output value of the integrating circuitry with a threshold value, and produces a pulse signal line having a pulse width corresponding to frequency of the rectangular pulse signal. Storing circuitry stores and retains the threshold value. Smoothing circuitry smoothes the pulse signal line, and produces a voltage value corresponding to the frequency of the rectangular pulse signal. Second comparing circuitry compares the voltage value with a reference voltage, and charges and discharges electric charge for the storing circuitry on the basis of the comparison result.

Abstract: A frequency detection circuit detects the frequency of a horizontal sync signal, and generates a mode switching signal corresponding to the detected frequency. A voltage-controlled oscillator constituting a PLL circuit has a plurality of oscillation modes obtained by dividing a frequency equal to an integer multiple of the frequency of the horizontal sync signal into a plurality of frequency ranges, and oscillates signals in the respective frequency ranges in accordance with control voltages output from a filter. The oscillation modes of the voltage-controlled oscillator are switched in accordance with the mode switching signal output from the frequency detection circuit. In the voltage-controlled oscillator, since the frequency range in each oscillation mode is narrow, the oscillation gain can be suppressed low, and a deterioration in jitter characteristics can be prevented.

Abstract: A reference voltage generator includes a voltage controlled oscillator which has fixed and accurate relationship between a frequency of an oscillation signal and a voltage supplied thereto, a reference frequency oscillator for generating a reference frequency signal of high accuracy and stability, a phase comparator for detecting a phase difference between the oscillation signal of the voltage controlled oscillator and the reference frequency signal, a low pass filter for smoothing a detection signal from the phase comparator, a gain adjust circuit for amplifying a signal from the low pass filter, a voltage adder for providing a sum of voltages from the gain adjust circuit and an offset voltage to the voltage controlled oscillator, and a phase clock loop formed by the phase comparator, low pass filter, gain adjust circuit and voltage adder to null the phase difference by regulating a control voltage applied to the voltage controlled oscillator.

Abstract: A frequency difference detector includes a pulse generator that receives an NRZ signal and a reference signal and provides data pulses having first edges based on edges of the NRZ signal and second edges based on edges of the reference signal, a pulse router that routes consecutive ones of the data pulses to different signal paths, a voltage generator that receives the data pulses from the signal paths and provides voltage signals with amplitudes based on pulse widths of the data pulses, and a comparison circuit that receives the voltage signals and provides error pulses with amplitudes based on voltage differences between the voltage signals. The amplitudes of the error pulses represent a frequency difference between the NRZ signal and the reference signal. Preferably, the data pulses have leading edges based on edges of the NRZ signal and the lagging edges based on leading edges of the reference signal immediately following the edges of the NRZ signal.

Abstract: A clock frequency detector is provided having a precise trip frequency which is insensitive to power supply variations. In one embodiment, the clock frequency detector employs a current source to discharge a capacitor at a constant rate and a gated current source to charge the capacitor at a frequency-dependent rate. If the charge rate exceeds the discharge rate, the capacitor will charge and an output signal is asserted. The gated current source is controlled by an edge-triggered pulse generator which generates pulses of a precise width in response to edges in the input clock signal. To create these pulses, the pulse generator produces an inverted clock signal with delayed transitions and combined this signal with the clock signal. The delayed transitions are created using a capacitor which is charged by a current source. The capacitor is provided with a shunt transistor which drains the charge from the capacitor whenever the clock signal is asserted.

Abstract: A semiconductor integrated circuit which converts power-supply voltage applied from outside into optimum voltage for operating an internal circuit at the frequency of an internal clock in response to a multiplication control signal supplied to a PLL circuit from outside to generate the internal clock for operating the internal circuit by dividing a clock supplied from outside or by judging the cycle of an internal clock generated by dividing an external clock so as to supply the optimum voltage to the internal circuit.

Abstract: An interface for a blower in an automotive vehicle. The interface allows a blower requiring a DC control voltage to be controlled by either (1) a DC control voltage or (2) a Pulse Width Modulated (PWM) signal. The interface converts the PWM signal to a DC voltage.

Abstract: A frequency-to-current converter includes several capacitances with capacitive values that are effectively multiplied. After each of a series of periodic pulses, the voltage on a "ramp" capacitance is charged to a starting voltage. Then, during the period preceding the subsequent pulse, the ramp capacitance is allowed to discharge at a discharge rate that is a function of a voltage on a discharge-current bias capacitance. At the end of the period, the voltage on the ramp capacitance is sampled and compared to a reference. If the voltage on the ramp capacitance is too low or too high, indicating a discharge current that is too high or too low, respectively, the bias voltage on the bias capacitance is adjusted to compensate for the error. In another embodiment, a small ramp capacitance is repetitively charged and discharged between two reference voltage levels using alternating charge and discharge current levels.

Abstract: In a frequency-to-voltage converting circuit, a clamping frequency is maintained constant without being adversely influenced by circuit constants, and temperature characteristics. The frequency-to-voltage converting apparatus has voltage converting means for converting a frequency of an input pulse signal into a voltage, arranged by frequency judging means for judging whether or not the frequency of the input pulse signal reaches a predetermined clamping frequency. Setting pulse signal generating means outputs a setting pulse signal having the clamping frequency, and means for causing the voltage converting means to convert the frequency of the input pulse signal into the voltage when the frequency of the input pulse signal does not reach the clamping frequency based on a judgement result of the frequency judging means.

Abstract: A wave-shaping circuit comprises a dynamic hysteresis generating circuit for generating a dynamic hysteresis voltage having a certain crest value and whose signal level attenuates at a speed proportional to a number of engine revolutions to mask an ignition noise superimposed on an input signal, and a threshold generating circuit for generating a threshold voltage whose signal level increases/decreases in proportion to the number of engine revolutions to mask an interference noise superimposed on the input signal and to reliably detect a minimum level of the input signal. Either the dynamic hysteresis voltage or the threshold voltage, whichever is higher, is selectively output as a comparison reference signal through a high-level selecting circuit.

Abstract: A Frequency-to-Voltage Convertor (FVC) circuit is based on a precision one-shot that is compensated in a way such that matching of transistors in the circuit is unimportant. Therefore, temperature spacial gradients are rejected. The necessary saturation voltages for the FVC's npn devices are compensated by modulating the drive level of these devices with temperature.

Abstract: A receiver having, arranged in this order, an input section, an FM demodulator, to which a frequency-modulated input signal is applied, and an LF section, which FM demodulator includes a pulse shaper and a low-pass filter, the pulse shaper comprising a series arrangement of at least a load and a capacitance, the base-emitter junction of a transistor being arranged across the capacitance, and further including a switching device for charging and discharging the capacitance. The pulse shaper generates a low-noise pulse in that charging of a capacitance is started upon an edge of the input signal. The capacitance voltage is measured by a single transistor and when the transistor is turned on, the charging current of the capacitance is diverted via the transistor, so that the capacitance voltage is limited. The capacitance is discharged upon a second edge, after which the cycle is repeated. The output signal of the pulse shaper is a signal which varies with the current through the capacitance.

Abstract: A Frequency-to-Voltage Converter (FVC) circuit is based on a precision one-shot that is compensated in a way such that matching of transistors in the circuit is unimportant. Therefore, temperature spacial gradients are rejected. The necessary saturation voltages for the FVC's npn devices are compensated by modulating the drive level of these devices with temperature.

Abstract: A pulse light-receiving circuit includes a pair of preamplifiers made up of the same circuit components, a difference amplifier for amplifying the outputs from the preamplifiers, and a pair of peak value-detecting circuits made up of the same circuit component for obtaining the amplitude of an input pulse signal. The median of that amplitude is used as a reference voltage for comparison with an output from the difference amplifier.

Abstract: A magnetic field alternation detecting apparatus includes a magnetic member sensor enclosed in a case and having a core (i.e., a yoke) to which a magnet is attached and around which a coil is wound. The magnetic member sensor obtains as an electromotive voltage a change in magnetic flux linking the coil on the basis of a magnetic field distribution disturbed by an approaching magnetic member present near the case from a pair of output terminals of the coil. An analog-to-digital converter is connected to the output terminals of the coil using at least one control terminal of a transistor such as a bipolar transistor or an enhancement operation field effect transistor. A main current terminal of the transistor is connected to a pair of output terminals.

Abstract: The CMOS integrated circuit includes an oscillator including a capacitor having a polysilicon gate of one of several transistors as an electrode thereof and a diffused resistor located adjacent to the polysilicon gate, a counter circuit for calculating a frequency of the oscillator, a power-supply voltage control circuit for selecting an optimal power-supply voltage for transistors in accordance with the frequency, and a power-supply circuit for generating the optimal power-supply voltage.