Abstract: A pull-down circuit includes a control circuit generating an activation signal in response to a supply voltage, a first reference voltage, and a feedback signal, and a charge pump configured to generate a control signal in response to the activation signal and control a switching device using the control signal. The switching device is a field-effect transistor (FET) and is coupled to a power switch and pulls down a voltage level of a gate of the power switch to prevent a premature turn-on of the power switch.

Abstract: An accumulation layer has a function of reducing an ON voltage (Von), which is a voltage between the collector and the emitter when turning on the IGBT, by accumulating carrier. However, when turning off the IGBT, the carrier contributes to a turn-off loss (Eoff). A semiconductor device is provided, comprising: a semiconductor substrate, wherein the semiconductor substrate includes: trench portions, a mesa portion each provided between two adjacent trench portions, and a drift layer, wherein the trench portions include: a gate trench portion, and a dummy trench portion, wherein the mesa portion has: an emitter region, a contact region, and a accumulation layer, wherein the number of accumulation layers provided in a depth direction in the mesa portion adjacent to the gate trench portion is larger than that of the accumulation layers provided in the depth direction in the mesa portion between the two dummy trench portions.

Abstract: A drive circuit for a power semiconductor element according to the present disclosure includes: a control command unit that outputs a turn-on command for a power semiconductor element; a gate voltage detection unit that detects a gate voltage applied to a gate terminal after the control command unit outputs the turn-on command; a differentiator that subjects the gate voltage detected by the gate voltage detection unit to time differentiation; and a determination unit that determines, based on the gate voltage detected by the gate voltage detection unit and a differential value by the differentiator, whether the power semiconductor element is in a short-circuit state or not.

Abstract: A switching control circuit has a detector to detect a difference between a control object signal of a switching element to drive a load and a target signal of the control object signal, and gate adjustment circuitry to search for the timing at which the difference becomes the smallest by sweeping timing of adjustment of a gate signal of the switching element.

Abstract: The present disclosure discloses a gate drive output stage circuit, a gate driving unit, and a drive method. The gate drive output stage circuit includes: a first control sub-circuit configured to transmit a start signal of a compensation driving terminal to a first node; a second control sub-circuit configured to transmit a first clock signal of a first clock terminal to a control node when the first node is at an effective level; a first output sub-circuit configured to transmit a second clock signal of a second clock terminal to a first output terminal when the control node is at an effective level; and a second output sub-circuit configured to transmit a first power supply voltage signal of a first power supply voltage terminal to a second output terminal when the control node is at the effective level.

Abstract: A semiconductor integrated circuit includes a level shifter formed in a portion of a high-voltage junction termination structure and an isolation region formed surrounding the periphery of the level shifter. The level shifter includes a p-type base region formed in an upper portion of a p? substrate, an n? source region formed contacting the base region, an n+ drift region formed contacting the base region, a drain region formed in an upper portion of the drift region, and a control electrode that controls the voltage of the base region. In a planar pattern, an effective channel width defined by the width of the base region in a portion that overlaps with the control electrode is greater than the width of the drain region as measured along the same direction as the effective channel width.

Abstract: A current sense device includes a reference transistor for electrically coupling to a power transistor, a sense transistor for electrically coupling to the power transistor, and control circuitry. The control circuitry is configured to (a) control current through the sense transistor such that a voltage at the sense transistor has a predetermined relationship to a voltage at the power transistor, and (b) control current through the sense transistor according to one or more operating conditions at the reference transistor, to compensate for aging of the power transistor.

Abstract: Embodiments of the present disclosure relate to a computer-implemented method. According to the method, a series of valid control codes for a calibration stage in a channel corresponding to a plurality of calibration cycles are acquired from the calibration logic. The acquired valid control codes are analyzed to obtain changing characteristics for the calibration stage in the channel. The calibration logic for the calibration stage in the channel is adjusted in one or more subsequent calibration cycles based on the changing characteristics.

Abstract: In described examples, in response to a voltage at an external power terminal falling below a safe limit: a charge pump is operated at a first frequency to produce a voltage at a charge pump node; and a first controlled current is coupled from the charge pump node to a control terminal of a power switch transistor. The power switch transistor has a conduction path coupled between the external power terminal and an internal power terminal at which an internal power source is connected. In response to the voltage at the external power terminal reaching a selected level: the charge pump is operated at a second frequency, lower than the first frequency; and a second controlled current, lower than the first controlled current, is coupled from the charge pump node to the control terminal of the power switch transistor.

Abstract: A power circuit includes a power transistor and a driving circuit. The power transistor draws a power current from a loading node according to a voltage of a driving node and stops drawing the power current according to an over-current signal. The driving circuit includes a high-side transistor, a low-side transistor, a charge pump, a pre-driver, and a desaturation circuit. The high-side transistor provides a supply voltage to the driving node according to a high-side voltage of a high-side node. The low-side transistor couples the driving node to the ground according to a first internal signal. The charge pump generates a high-side voltage that exceeds the supply voltage according to the first internal signal. The pre-driver generates the first internal signal according to a control signal. The desaturation circuit determines that the power current exceeds a threshold to generate the over-current signal.

Abstract: A method and a device for controlling a commutation process of a load current between two switching modules are disclosed that each have a MOSFET that can be controlled by a gate-source voltage, and an intrinsic-body inverse diode. To reduce oscillations in the down-commutation of the inverse diodes caused by parasitic circuit parameters, after switching off one of the switching modules, the gate-source control voltage applied to this switching module is temporarily switched off until being increased again the vicinity of the threshold voltage for switching on the MOSFET, before and while the other switching module is switched on, in order to commutate the current from the inverse diode of the one switching module to the MOSFET of the other switching module.

Abstract: According to the present invention, a semiconductor device includes a first semiconductor device, a second semiconductor device, an AC output terminal, a first shunt resistor connected to the first semiconductor device at one end thereof and the AC output terminal at the other end thereof, a second shunt resistor connected to the second semiconductor device at one end thereof and the AC output terminal at the other end thereof, a first wiring connecting the one end of the first shunt resistor and the one end of the second shunt resistor, a second wiring connecting the other end of the first shunt resistor and the other end of the second shunt resistor and a first sense resistor circuit including a first sense resistor and a second sense resistor connected in series between the one end of the first shunt resistor and the one end of the second shunt resistor.

Abstract: A switch circuit includes a first switch connected to a first node such that the first switch is connected in series between the first node and a first electrode terminal of a DC power source. a second switch connected in series between the first node and a second node which is configured to be connected to a second electrode terminal of the DC power source, a soft switch circuit, a power switching element, and a controller. The soft switch circuit includes a capacitor connected in series between a third node and one of the first and second nodes, a charge-discharge switch connected in series between the third node and another of the first and second nodes, and a charge-discharge resistor connected in parallel to the charge-discharge switch. The power switching element has a drain terminal, a gate terminal connected to the first node, and a source terminal connected to the second node.

Abstract: A semiconductor device includes a power semiconductor switching element, a comparator circuit, a filter circuit and an erroneous-detection prevention circuit. The comparator circuit compares a value of an output voltage of the switching element with a threshold and outputs a comparison result as a determination signal. The filter circuit outputs the determination signal to the control circuit after a delay time required for the output voltage of the switching element to reach a predetermined voltage value for determining that the switching element is in a normal ON state after the switching element is turned on. The erroneous-detection prevention circuit changes a turn-on time of the switching element, the delay time, or a voltage value of the determination signal when a voltage of the power supply drops in a case where the switching element is normally turned on.

Abstract: An electrical circuit includes a ground-referenced transistor and a non-ground-referenced transistor configured in a half-bridge topology. The non-ground-referenced power transistor has a first conducting electrode coupled to a high voltage power supply, a control electrode coupled to a high-side pre-driver, and a second conducting electrode coupled to a switch node. The electrical circuit further includes a boot-strapped capacitor having a bottom plate coupled to the second conducting electrode and a top plate coupled to the high-side pre-driver, and an interface coupled to a first sense device for sensing a voltage at the top plate, a second sense device for sensing a voltage at the bottom plate, and a charging device for selectively increasing the voltage at the top plate. The interface controls the charging device based on the voltage at the top plate and the voltage at the bottom plate.

Abstract: In a drive apparatus, a transmission unit mounted to a first region stops transmission of a pulse signal from a physical-quantity transmission terminal. The transmission unit transmits, from the failure information transmission terminal, a first signal indicative of an occurrence of the failure associated with the target switch when it is determined that the failure associated with the target switch has occurred, and transmits, from the physical-quantity transmission terminal, a second signal indicative of a content of the failure associated with the target switch. A controller mounted to a second region electrically isolated from the first region detects, based on the pulse signal from the physical-quantity transmission terminal, the physical quantity upon no input of the first signal to the controller. The controller identifies, based on the second signal transmitted from the physical-quantity transmission terminal, the content of the failure upon the first signal being input to the controller.

Abstract: System and method for driving a bipolar junction transistor for a power converter. The system includes a current generator configured to output a drive current signal to a bipolar junction transistor to adjust a primary current flowing through a primary winding of a power converter. The current generator is further configured to output the drive current signal to turn on the bipolar junction transistor during a first time period, a second time period, and a third time period, the second time period separating the first time period from the third time period, drive the bipolar junction transistor to operate in a hard-saturation region during the first time period and the second time period, and drive the bipolar junction transistor to operate in a quasi-saturation region during the third time period.

Abstract: Disclosed are a pixel circuit and a method for driving the pixel circuit. The pixel circuit includes a light-emitting diode; a driving transistor; a first transistor connected between a data line and the driving transistor, a gate electrode of the first transistor being connected to a first scanning line; a second transistor connected between a first power line and the driving transistor, a gate electrode of the second transistor being connected to a second scanning line; a third transistor connected between a gate electrode of the driving transistor and the second transistor, a gate electrode of the third transistor being connected to a third scanning line; and a driving capacitor connected between the gate electrode of the driving transistor and the first power line, in which the driving transistor is further connected to a second power line via the light-emitting diode.

Abstract: A charge pump circuit is provided, in which a charge pump is supplied with a temperature-dependent bias current, in particular a bias current that decreases with temperature.

Abstract: An insulating gate semiconductor device includes an insulating gate semiconductor element, an insulating circuit board, and a main-current path member. A main-current of the insulating gate semiconductor element flows toward a first external terminal in the main-current path member; and a gate-current path member, being patterned so as to have a linearly extending portion arranged in parallel to a linearly extending portion of the main-current path member in a planar pattern on the insulating circuit board, being provided to connect between a second external terminal and a gate electrode of the insulating gate semiconductor element. A current which is induced in the gate-current path member by mutual induction caused by a change in magnetic field implemented by the main-current is used for increasing the gate-current in a turn-on period of the insulating gate semiconductor element.

Abstract: Power semiconductor devices according to embodiments of the present technology may be operated to protect components of the semiconductor device. Methods for operation of the devices may include measuring a temperature within a source region of the semiconductor device. The methods may include measuring at the semiconductor device an amount of current associated with a short circuit external to the semiconductor device. The methods may include predicting a temperature effect within two regions of the semiconductor device based on a range of distribution of the amount of current between the two regions of the semiconductor device. The methods may include determining a particular distribution of the amount of current between the two regions of the semiconductor device. The methods may also include shutting off the semiconductor device to cause the particular distribution of current between the two regions of the semiconductor device.

Abstract: A computing device is provided that includes a processor, a primary power supply, and a voltage regulation module. The voltage regulation module is configured to determine a load line for the processor and monitor a voltage and a current to the processor. While monitoring the voltage and current, the voltage regulation module is further configured to regulate the voltage to the processor to trend toward a voltage setpoint defined by the load line. While regulating the voltage, the voltage regulation module is further configured to clamp the load line at a clamping voltage to limit the regulated voltage output by the voltage regulation module from falling below a predetermined device minimum operation voltage when the monitored current exceeds a device maximum current value. The voltage regulation module is further configured to output electrical power at the regulated voltage to the processor.

Abstract: A power electronics circuit is disclosed that includes a switching circuit comprising a first solid-state device coupled in series with a second solid-state device, with at least the first solid-state device comprising a solid-state switch having a gate terminal. The power electronics circuit also includes a current sense transformer positioned between the first and second solid-state devices and configured to sense a current flowing on a conductive trace connecting the first and second solid-state devices, and a controller coupled to the switching circuit and the current sense transformer so as to be in operable communication therewith. The controller is programmed to receive a current sense signal from the current sense transformer indicative of the current flowing on the conductive trace and modulate a gate voltage to the gate terminal of the first solid-state device based on the received current sense signal, so as to control switching thereof.

Abstract: A method for protecting a power switch during turn-on includes sensing that a change in current through the power switch is in regulation, measuring a time that the change in current through the power switch is in regulation, and comparing the time that the change in current through the power switch is in regulation to a reference time. An over current signal, which can be used to disable the power switch, is generated if the time that the change in current through the power switch is in excess of the reference time.

Abstract: An input circuit includes an input line for providing input regarding state of a load. A first impedance is connected to the input line at a first node for connecting a voltage source to the input line. A second impedance is connected to the input line at a second node for connecting the input line to ground. A Zener diode is connected in the input line in series between the first and second nodes to impede current flowing through the Zener diode below the Zener voltage thereof in a direction from the first node to the second node, and to allow current above the Zener voltage thereof in the direction from the first node to the second node.

Abstract: The present disclosure relates to a power converter configured for limiting switching overvoltage. The power converter comprises a bottom commutation cell that includes a bottom power electronic switch and a bottom compensation circuit connected to a bottom parasitic inductance. The bottom compensation circuit applies a sample of the voltage induced across the bottom parasitic inductance at turn-off of the bottom power electronic switch to the reference node of the bottom gate driver. The power converter also comprises a top commutation cell that includes top power electronic switch and a top compensation circuit connected to the bottom parasitic inductance. The top compensation circuit applies a sample of the voltage induced across the bottom parasitic emitter upon turn-off of the top power electronic switch to the reference node of the top gate driver.

Abstract: There is provided a semiconductor device comprising a substrate, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a trench and an insulating film arranged to cover a surface of the trench. The first semiconductor layer has a carrier concentration that provides a peak in a thickness direction perpendicular to a plane direction. A high carrier concentration area having a peak of the carrier concentration in the first semiconductor layer is extended in the plane direction at a location away from the trench to be located on the substrate side of the trench. This configuration reduces the on resistance while suppressing reduction of the breakdown voltage in the semiconductor device.

Abstract: This electrical switching apparatus has at least two power components each including first and second power transistors. A driver control device of the transistors is configured to deliver a first control signal to each of the first transistors and a second control signal to each of the second transistors, and an electrical interconnect device connecting the driver control device to the power components. The interconnect device includes several electrically conductive plates extending parallel to one another, each being connected between a control electrode of one of the first or second power transistors and a corresponding output of the driver control device.

Abstract: The present invention relates to a control device (1) for at least one transistor, referred to as the controlled transistor (3), comprising:—said controlled transistor (3) which comprises a control electrode (Ec) and two other electrodes (E1 and E2),—a main control circuit (5) connected to the control electrode (Ec) of the controlled transistor (3) and configured, according to a main mode of operation, to control the state of the controlled transistor (3) and,—an auxiliary control circuit (11) configured, according to an auxiliary mode of operation, to inject an auxiliary current opposing the current circulating between the main control circuit (5) and the control electrode (Ec) of the controlled transistor (3), characterized in that the control device (1) also comprises a control circuit (15) of the auxiliary control circuit (11), said control circuit (15) being configured to block or authorize the auxiliary operation of the auxiliary control circuit (11) depending on the commands from the main control circu

Abstract: Disclosed is a method for driving a transistor device and an electronic circuit that includes a transistor device. The method includes driving the transistor device based on a drive signal such that the transistor device is driven in an on-state when the drive signal has an on-level and an off-state when the drive signal has an off-level. Driving the transistor device in the off-state includes: operating the transistor device in a first off-state after the drive signal changes from the on-level to the off-level; after the first off-state, operating the transistor device in a second off-state different from the first off-state; and after the second off-state, operating the transistor device in a third off-state different from the second off-state if the off-level of the drive signal prevails longer than a predefined maximum time period.

Abstract: With the disclosed device, a control method is set forth to control the flow of power between an electrical source and an electrical load.

Abstract: A control buffer circuit includes a voltage detection circuit configured to detect whether a received voltage is a negative voltage or a ground voltage and provide a voltage detection signal based on a result of the detecting, and a buffer circuit configured to provide a switching signal based on the voltage detection signal, wherein the switching signal comprises a positive voltage as a switching-on level voltage and includes one or more of the ground voltage and the negative voltage as a switching-off level voltage.

Abstract: An optical-controlled driving circuit adapts to a high utility power environment with high voltages, large currents and severe surges, and includes an optical-controlled switch circuit, an SCR with optical-controlled driver and a main circuit. The optical-controlled switch circuit includes an optical-controlled component and a first switching transistor that are connected in serial. The SCR with optical-controlled driver includes at least two switching transistors that are connected in serial and a plurality of diodes, and is coupled to the main circuit. The optical-controlled driving circuit generates a driving current according to the voltage of a utility power. When the optical-controlled driving circuit is used in a DC converter using an SCR as a switch element, the optical-controlled driving circuit helps to increase the operation efficiency when the DC converter works under a light load.

Abstract: A circuit and a system may drive switching modules. The driving circuit and system are capable of controlling a detection level of a protection voltage of a switching module, by controlling a voltage of a detection circuit for detecting the protection voltage. This may be done based on control of a variable resistance.

Abstract: A light-receiving circuit receives light emitted by a light-emitting part and generates an energization signal that is an electric current based on intensity of the light. A hold circuit is configured to supply an electric charge of an energization signal to a high electric potential terminal and not to decrease a voltage of the high electric potential terminal in a case where a control circuit is sending an OFF signal. Furthermore, the hold circuit is configured not to supply the electric charge of the energization signal to the high electric potential terminal and to keep the voltage of the high electric potential terminal in a case where the control circuit is sending an ON signal. A comparison circuit compares a comparison signal and a reference signal, generates a bias voltage based on a result of the comparison between the comparison signal and the reference signal, and feeds back the bias voltage as a reference signal.

Abstract: Embodiments of the present disclosure relate to a computer-implemented method. According to the method, a series of valid control codes for a calibration stage in a channel corresponding to a plurality of calibration cycles are acquired from the calibration logic. The acquired valid control codes are analyzed to obtain changing characteristics for the calibration stage in the channel. The calibration logic for the calibration stage in the channel is adjusted in one or more subsequent calibration cycles based on the changing characteristics.

Abstract: A P-channel type MOSFET and an N-channel type MOSFET formed by a CMOS process are connected in series. A high-voltage signal and a low-voltage signal are applied to the drain of one of transistors. Prescribed bias voltage is applied to both gates in order that only a low-voltage signal can pass through both conduction paths.

Abstract: Structures and circuits including multiple nanosheet field-effect transistors and methods of forming such structures and circuits. A complementary field-effect transistor includes a first nanosheet transistor with a source/drain region and a second nanosheet transistor with a source/drain region stacked over the source/drain region of the first nanosheet transistor. A contact extends vertically to connect the source/drain region of the first nanosheet transistor of the complementary field-effect transistor and the source/drain region of the second nanosheet transistor of the complementary field-effect transistor.

Abstract: A half bridge GaN circuit is disclosed. The circuit includes a low side power switch configured to be selectively conductive according to one or more input signals, a high side power switch configured to be selectively conductive according to the one or more input signals, and a high side power switch controller, configured to control the conductivity of the high sigh power switch based on the one or more input signals. The high side power switch controller includes a capacitor, and a logic circuit, wherein the capacitor is configured to capacitively couple a signal based on the input signals to the logic circuit, and the logic circuit is configured to control the conductivity of the high sigh power switch based on the capacitively coupled signal.

Abstract: A driver circuit which includes an output circuit and a control circuit coupled to the output circuit. The driver circuit includes a pull-up transistor with a silicon semiconductor layer. The control circuit includes a first transistor with an oxide semiconductor layer.

Abstract: A semiconductor device includes a first circuit operating with a first potential as a reference potential and a second circuit operating with a second potential different from the first potential as a reference potential, able to reliably detect that a negative voltage is applied to the first circuit. The first circuit includes a current source. The current source supplies a current to the low side circuit, and changes the current in response to whether or not the first potential becomes a negative voltage with respect to the second potential. Also, the second circuit includes a negative voltage detection circuit. The negative voltage detection circuit monitors a change in the current supplied from the current source and detects that a negative voltage is applied to the high side circuit.

Abstract: A waveform conversion circuit for turning a switch device on and off by applying a control signal from a controller to a gate terminal of the switch device is provided. The switch device has the gate terminal, a drain terminal, and a source terminal. The waveform conversion circuit includes a parallel circuit of a first capacitor and a first resistor and a voltage clamp unit. The parallel circuit is coupled between the controller and the gate terminal. The voltage clamp unit is coupled between the gate terminal and the source terminal and configured to clamp a voltage across the gate terminal to the source terminal at a first voltage in an OFF pulse of the control signal and at a second voltage in an ON pulse of the control signal.

Abstract: Provided is a technique for a stably operable complementary single ended push pull (SEPP) circuit. A buffer circuit includes the following: an NPN transistor and a PNP transistor that constitute a complementary SEPP circuit; a first resistor; a second resistor; a first load element having one end connected to a gate of a semiconductor switching element and another end connected to a base of the NPN transistor; and a second load element having one end connected to the gate of the semiconductor switching element and another end connected to a base of the PNP transistor.

Abstract: A half bridge circuit and a method for its operation are presented. The half bridge circuit contains a high-side switch, a latch for providing a drive signal for the high-side switch, a first transistor device acting as a level shifter for shifting a voltage level at an input of the latch. The first transistor device is coupled between a supply voltage level and ground, and the voltage level at the input of the latch is shifted in accordance with a current that flows through the first transistor device. A second transistor device is coupled between the supply voltage level and ground, in parallel to the first transistor device. There is a current mirror for mirroring a current that flows through the second transistor device. There is a circuit path for feeding the mirrored current to an intermediate node between the supply voltage level and the first transistor device.

Abstract: The present invention provides a drive device and a power supply system capable of driving a power transistor with low power while reflecting variations in manufacture process and external environments. A trigger detection circuit monitors a voltage between terminals or a current between terminals in a switching period of a power transistor and detects that the voltage between terminals or the current between terminals reaches a predetermined reference value. A current switching circuit selects a register outputting a current value to a variable current driver circuit from a plurality of registers and switches the register to be selected using a detection result of the trigger detection circuit as a trigger in the switching period, thereby making the drive current of the variable current driver circuit shift.

Abstract: A body bias voltage generating circuit for supplying a body bias voltage to a body of a transistor of a functional circuit is provided, including: a first transistor and a second transistor connected in series between a supply voltage terminal and a ground terminal, wherein a control terminal of the first transistor is coupled with a control terminal of the second transistor; a third transistor, wherein a body of the third transistor is electrically coupled with any one of the body of the first transistor and the second transistor, and a terminal of the third transistor is coupled with the body of the third transistor; and a resistance element coupled between the terminal of the third transistor and a current input terminal of the first transistor or a current output terminal of the second transistor. The terminal of the third transistor is the body bias voltage.

Abstract: An electronic device can include a bidirectional HEMT. In an aspect, the electronic device can include a pair of switch gate and blocking gate electrodes, wherein the switch gate electrodes are not electrically connected to the blocking gate electrodes, and the first blocking, first switch, second blocking, and second switch gate electrodes are on the same die. In another aspect, the electronic device can include shielding structures having different numbers of laterally extending portions. In a further aspect, the electronic device can include a gate electrode and a shielding structure, wherein a portion of the shielding structure defines an opening overlying the gate electrode.

Abstract: This application relates to methods and apparatus for voltage regulation. Embodiments relate to signal processing circuit (300) having a first and second processing path with respective first and second inputs (INP and INN). The first and second processing paths have respective first and second virtual earth nodes (108P and 108N) at the input to a differential integrator (106). A differential feedback path is configured to apply a feedback signal to each of the first and second virtual earth nodes so as to minimize any voltage difference between them. A regulator (301) is operable to monitor a voltage at one of the virtual earth nodes (108P) against a reference voltage (VREF) and to generate a regulation signal to maintain the voltage at said monitored one of the first and second virtual earth nodes to be equal to the reference voltage. The regulation signal is applied to both of the first and second virtual earth nodes.

Abstract: A controller is configured to select a rate of change direction of an output voltage of a variable voltage converter (VVC) based on a direction of current flow associated with a capacitor of the VVC, and to adjust a magnitude of the rate of change direction based on directions of current flow associated with the capacitor and an electric machine coupled to the VVC.

Abstract: An automated test equipment for testing a device under test includes a control unit and a plurality of tester subunits. The control unit is configured to put the tester subunits in a state of lower activity in dependence on a current demand on the test resources.