Abstract: Circuitry comprises a high voltage rail providing a high voltage level corresponding to a higher voltage domain, an intermediate voltage source, a low voltage rail, and devices that operate in a lower voltage domain. First devices in an upper voltage region are powered between the high voltage rail and an intermediate voltage rail powered by the intermediate source. Second devices in a lower voltage region are powered between the intermediate and low rails. On power up, the intermediate source is powered before the high voltage rail. An isolating circuit connects the intermediate source to a node when the high voltage rail is powered and isolates the node from the intermediate source when the high voltage rail is not powered to impede current flow from the intermediate source to the high voltage rail.

Abstract: An integrated circuit includes an output driver circuit having a plurality of output driver devices connected in a parallel arrangement and an output driver controller that is capable of individually controlling the conducting states of the output driver devices. In at least one embodiment, the controller is capable of achieving any of a plurality of different fall times (and/or rise times) in an output signal by appropriately controlling the conducting states of the output devices if a change in the state of the output signal is desired, in some implementations, the controller is capable of achieving different waveshapes during rising and/or failing edges of an output signal.

Abstract: A voltage controlled switching element gate drive circuit makes it possible to suppress an occurrence of a malfunction, while suppressing surge voltage, surge current, and switching noise, when switching in a voltage controlled switching element. A gate drive circuit that supplies a gate voltage to the gate of a voltage controlled switching element, thus driving the voltage controlled switching element, includes a high potential side switching element and low potential side switching element connected in series, first variable resistors interposed between at least the high potential side switching element and a high potential power supply or the low potential side switching element and a low potential power supply, and a control circuit that adjusts the resistance values of the first variable resistors.

Abstract: A decoupling circuit includes an inverter. The inverter includes i (i is an integer of 1 or more) PMOS transistors each having a first gate electrode, and j (j is an integer of 0 or more) PMOS transistors each having a second gate electrode. The inverter includes m (m is an integer of 1 or more) NMOS transistors each having a third gate electrode, and n (n is an integer of 0 or more) NMOS transistors each having a fourth gate electrode. The first to fourth gate electrodes are coupled to an input end of the inverter. A total area of the first and second gate electrodes is different from a total area of the third and fourth gate electrodes.

Abstract: The preferred embodiments of the present invention use low voltage transistors to support high voltage switching circuits by connecting low voltage circuits in a stacking configuration. High voltage switching signals are divided into a plurality of small amplitude switching signals before sending into transformers, filters or other circuits. The resulting circuits can support high voltage applications while achieving cost and performance advantages of low voltage circuits.

Abstract: A voltage mode driver system includes a plurality of VMD cells, a plurality of auxiliary cells, a control logic and an output node. The plurality of VMD cells are configured to generate a first output. The plurality of VMD cells are configured to generate a calibrated effective resistance at different signal levels according to a calibration signal. The plurality of auxiliary cells are configured to generate a second output. The output node combines the first output and the second output into a driver output. The control logic is configured to control the plurality of auxiliary cells and the second output according to a selected level. The plurality of VMD cells may be configured to generate a calibrated effective resistance at different signal levels according to a calibration signal. A calibration component is configured to determine a voltage dependence effect and to generate a calibration signal according to the determined voltage dependence effect.

Abstract: An impedance calibration circuit includes a first calibration voltage driver configured to operate in response to a first enable signal, compare a first calibration voltage signal with a first reference voltage signal, and drive the first calibration voltage signal, a first control code generator configured to operate in response to a second enable signal, compare the first calibration voltage signal with a first target voltage signal, and generate a first control code signal, and a first reference voltage generator configured to generate the first reference voltage signal in response to the first control code signal.

Abstract: An output circuit includes: a first PMOS transistor and a second PMOS transistor connected in series between a high potential side power supply and an output node; a first NMOS transistor and a second NMOS transistor connected in series between a low potential side power supply and the output node; a bias voltage generation circuit outputting a first bias voltage to a first bias node connected to a gate terminal of the second PMOS transistor and a second bias voltage to a second bias node connected to a gate terminal of the second NMOS transistor; first and second bias voltage stabilization circuits suppressing fluctuations in the first and second bias voltages; and a control circuit detecting a change in a signal that fluctuates the first bias voltage and the second bias voltage and controlling the first and second bias voltage stabilization circuits.

Abstract: A semiconductor device includes a normal code generation unit capable of generating a normal code, a test code output unit capable of storing a plurality of preliminary test codes to output a test code in response to a test control signal, and a reference voltage generation unit capable of generating a normal reference voltage in a normal operation mode and generating a test reference voltage in a test operation mode in response to the normal code and the test code.

Abstract: Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.

Abstract: A driving circuit is provided. The driving circuit is capable of driving a load coupled to an output node of the driving circuit. The driving circuit includes an output-stage element, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a first P-type metal-oxide-semiconductor (PMOS) transistor. The output-stage element is coupled between an operation voltage source and the output node. The first NMOS transistor has a gate, a drain coupled to the output node, and a source coupled to a ground. The first PMOS transistor has a gate, a drain coupled to the ground, and a source coupled to the output node. When the first NMOS transistor begins to be turned off, the first PMOS transistor is turned on, and a voltage at the drain of the first NMOS transistor is clamped to be lower than a breakdown trigger voltage of the first NMOS transistor.

Abstract: A two-stage post driver circuit includes a controlling circuit, a pull-up unit and a pull-down unit. A first N-type transistor of the pull-down unit and a first P-type transistor of the pull-up unit are both connected to an output pad. The controlling circuit is used for controlling the first N-type transistor and the first P-type transistor. Consequently, when the pull-up unit or the pull-down unit is turned on, the voltage difference between the drain terminal and the source terminal of the first N-type transistor or the first P-type transistor is lower than a voltage stress.

Abstract: Differential receivers are “stacked” and independently calibrated to different common-mode voltages. The different common-mode voltages may correspond to the common-mode voltages of stacked transmission circuits. Multiple stacks of samplers are connected to the same channels. The clocking of each stack of sampler circuits is phased (timed) such that the samplers in a given stack are not resolving at the same time. Samplers in a different stack and receiving a different common-mode voltage resolve at the same time.

Abstract: A pre-charging circuit, such as can be used to pre-charge a data bus, is largely process independent. A push-pull type of arrangement is used, where the output of the pre-charge circuit is initially connected to a supply level through one transistor, then connected to ground by another transistor. These transistors can be controlled by one or more comparators that have as inputs a reference level and feedback from the output. The reference level is generated by a circuit that tracks the threshold voltage of the other devices in the circuit in order to reduce process dependency of the output level. The circuit can also include a device to provide an extra VDD assist to the output.

Abstract: An output driver for electrostatic discharge (ESD) protection includes a first pair of stacked metal oxide semiconductor field-effect transistor (MOS) devices coupled between a power terminal and a first differential output terminal. The output driver also includes a second pair of stacked MOS devices coupled between a second differential output terminal and a ground terminal.

Abstract: The transistor suffers the variation caused in threshold voltage or mobility due to gathering of the factors of the variation in gate insulator film resulting from a difference in manufacture process or substrate used and of the variation in channel-region crystal state. The present invention provides an electric circuit having an arrangement such that both electrodes of a capacitance element can hold a gate-to-source voltage of a particular transistor. The invention provides an electric circuit having a function capable of setting a potential difference at between the both electrodes of the capacitance element by the use of a constant-current source.

Abstract: Techniques for reducing crowbar current are disclosed. In one embodiment, a circuit for reducing crowbar current comprises an inverter having an input and an output, a first switch coupled between the inverter and a first power supply rail, and a second switch coupled between the inverter and a second power supply rail. The circuit also comprises a feedback circuit coupled to the output of the inverter, wherein the feedback circuit is configured to turn off the first switch when the output of the inverter is in a low output state, and to turn off the second switch when the output of the inverter is in a high output state.

Abstract: There is provided an output stage comprising: a phase splitter for receiving an input signal and for generating first and second drive signals of opposite phase in dependence thereon; a DC offset signal generator for generating a DC offset signal; an adder for adding the DC offset signal to the first drive signal to provide a first modified drive signal; a subtractor for subtracting the DC offset signal from the second drive signal to provide a second modified drive signal; a first drive transistor associated with a first power supply voltage, for generating a first output signal in dependence on the first modified drive signal; a second drive transistor associated with a second power supply voltage, for generating a second output signal in dependence on the second modified drive signal; and a combiner for combining the first and second output signals to generate a phase combined output signal.

Abstract: A driving circuit includes a common well. The driving circuit further includes a first output buffer having a bulk connected to the common well, the first output buffer having a first terminal configured to receive a first signal, and having a second terminal connected to the common well. The driving circuit further includes a second output buffer having a bulk connected to the common well, the second output buffer having a first terminal configured to receive the first signal, wherein a second terminal of the second output buffer disconnected from the common well. The driving circuit further includes a first driver connected to the second terminal of the first output buffer and a second driver connected to the second terminal of the second output buffer.

Abstract: A gate driving circuit for driving an insulated gate switching element, including a gate charging circuit configured to charge gate capacitance of the insulated gate switching element, and a gate discharging circuit that is connected in series with the gate charging circuit and configured to discharge a charge of the gate capacitance. The gate charging circuit includes a first p-channel metal oxide semiconductor field effect transistor (MOSFET), and a first hybrid normally-on enhancement MOSFET insertion (NOEMI) circuit connected in series with a drain of the first p-channel MOSFET. The gate discharging circuit includes a first n-channel MOSFET, and a second hybrid NOEMI circuit connected in series with a drain of the first n-channel MOSFET.

Abstract: A semiconductor device and a power voltage supply circuit for a test operation of a semiconductor system including the semiconductor device. The semiconductor device receives first and second power supply voltages in a normal operation mode from an external device and receives the first power supply voltage in a test operation mode. The semiconductor device includes a voltage level setting unit configured to set a power connection node at a voltage between a voltage level of a first power supply voltage terminal and a voltage level of a ground voltage terminal according to an operation mode signal, and a voltage driving unit configured to drive a second power supply voltage terminal with the first power supply voltage in the test operation mode, wherein the driving power is controlled according to the voltage level of the power connection node.

Abstract: A buffer control circuit includes a current supply unit configured to supply current and adjust the current in response to codes, an amplifying buffer configured to operate using the current and output a value obtained by comparing a reference potential and the reference potential, a second buffer configured to buffer an output of the first buffer, and a code generation unit configured to generate the codes in response to an output of the second buffer.

Abstract: A semiconductor device includes an information generation circuit configured to generate first information, an information multiplexing circuit configured to multiplex the first information and second information, and an information driving circuit configured to drive an output pad in response to an output signal of the information multiplexing circuit.

Abstract: A PWM modulator as might be used in a power converter, a drive signal will be generated on an output pin of an integrated circuit PWM controller device which is used to drive the output when the modulator is required to be on.

Abstract: Current drivers and biasing circuitry at least partly compensate for manufacturing variations and environmental variations such as supply voltage, temperature, and fabrication process.

Abstract: Described is an apparatus which comprises: a first node to provide an un-gated power supply; a second node to provide a threshold dependent supply; an inverter with an input and an output, the inverter coupled to the first and second nodes, the inverter to receive the un-gated power supply at its power supply node, and to receive the threshold dependent supply for supplying ground supply at its ground node; and a transistor with its gate terminal coupled to the output of the inverter, the transistor to provide gated power supply to one or more logic units.

Abstract: An output stage circuit includes: a first transistor, including a first terminal coupled to a first node, a second terminal coupled to an output terminal, a third terminal coupled to an input terminal for receiving an input voltage, and a fourth terminal coupled to a first power terminal for receiving a first voltage; a second transistor, including a first terminal coupled to a second node, a second terminal coupled to the output terminal, a third terminal coupled to the input terminal for receiving the input voltage, and a fourth terminal coupled to ground; and a current source, coupled to the output terminal for providing a constant current.

Abstract: The present document relates to a reduction of heat generated in driver circuits comprising voltage regulators. A circuit arrangement comprises a driver circuit configured to generate a control signal for driving a power switch. The driver circuit comprises a voltage regulator configured to generate a second voltage from a supply voltage, a drive unit configured to generate the control signal based on the supply voltage and configured to provide the control signal to a control interface of the driver circuit, and a logic component operating at the second voltage and drawing a second current, and configured to control the drive unit. Furthermore, the circuit arrangement comprises bypass circuitry coupled at an input to the control interface and configured to provide at an output at least part of the second current to the logic component.

Abstract: A semiconductor device arrangement and a method. One embodiment includes at least one power transistor and at least one gate resistor located between a gate of the power transistor and a connecting point in the drive circuit of the power transistor. The semiconductor device arrangement includes a switchable element between the connecting point and a source of the power transistor.

Abstract: A driving circuit of flat display including a charging circuit path, a discharging circuit path, and a detecting circuit is provided. The charging circuit path has first and second impedance states, wherein an impedance value of the first impedance state is smaller than that of the second impedance state. The discharging circuit path has third and fourth impedance states, wherein an impedance value of the third impedance state is smaller than that of the fourth impedance state. The detecting circuit detects whether the charging circuit path or the discharging circuit path is in an unstable first state or stable second state, controls the charging circuit path to the first impedance state or the discharging circuit path to the third impedance state in the first state, and controls the charging circuit path to the second impedance state or the discharging circuit path to the fourth impedance state in the second state.

Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit that transmits data in parallel through a plurality of signal lines and a data receiving circuit that receives the data. The data transmitting circuit includes a plurality of data output circuits that output the data in a data transmission mode or set an output to a high impedance state in a HiZ mode, a plurality of data selection circuits that select one of the data and fixed data and output the selected data to the data output circuits, and a control circuit that controls the data output circuits to output the fixed data during a period between a time when a mode is switched from the HiZ mode to the data transmission mode and a time when the data output circuits start to output the data.

Abstract: A circuit may include a controller, at least one bridge circuit, and a plurality of switches. The plurality of switches may be connected parallel to each other, each may have a switch output connected to the bridge circuit. The bridge circuit, upon receiving a current from the plurality of switches, may generate an output based on a reference voltage. The controller may generate a plurality of control signals, based on a voltage transition range, to selectively turn on the plurality of the switches in more than one combination, to supply a current to the output.

Abstract: An inverter circuit includes an input stage and an output stage, each including pairs of complementary transistors having low-voltage oxides. The transistors within the input stage are configured to receive the input signal and to provide control voltages in response to input signal voltage variations. The voltage level of one control voltage is clamped between an intermediate voltage and a high voltage, and the voltage level of the other control voltage is clamped between the intermediate voltage and a low voltage. The switching states of each complementary transistor in the output stage are controlled by the control voltages, which results in an output signal voltage varying between the high and the low voltage. The voltage clamping advantageously allows the inverter circuit to switch between the high and the low voltage level without exceeding a maximum gate-source or a gate-drain voltage rating for any transistor, and without requiring additional passive components.

Abstract: According to one embodiment, a line driver circuit comprises a plurality of output stages each operable to produce an output signal and one or more pre-output stages operable to perform one or more common functions. The line driver circuit also comprises circuitry operable to selectively couple one or more of the output stages to the one or more pre-output stages based on a wireline communication technology implemented by the line driver circuit.

Abstract: Data transmission circuits are provided. The data transmission circuit includes a control signal generator and an output driver. The control signal generator generates a pull-up control signal and a pull-down control signal by using a count signal that changes in response to a clock signal during a drive control period. The output driver receives an internal data signal and drives a transmission data signal in response to the pull-up control signal and the pull-down control signal.

Abstract: A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly.

Abstract: The present disclosure discloses methods and circuits to reduce power consumption of switching circuits comprising two or more units by applying charge sharing/reuse of capacitive loads between the units. The units are stacked in a way that, if an output potential of a unit is to be lowered and an output potential of a neighboring unit is to be lifted, a charge of the unit to be lowered is reused by transferring it to the unit to be lifted depending on input signals of the units. In case of input signals having an arbitrary relationship a storage unit is placed at a junction of two neighboring units to store the charge temporarily until a neighboring unit is to be lifted.

Abstract: A power drive apparatus is provided. The apparatus includes a first switch having a first plurality of power devices arranged in a back to back configuration within adjacent stacked rows of the first switch. The apparatus includes a second switch having a second plurality of power devices arranged in a back to back configuration within adjacent stacked rows of the second switch. A bus is shared with the first switch and the second switch. The apparatus includes a control drive device coupled to a gate of each power device of the first plurality of power devices and each power device of the second plurality of power devices.

Abstract: A load driving device includes a pulse driving circuit which has a capacitor between an output terminal and a ground potential, a level detection circuit which detects whether an output terminal voltage on the output terminal of the pulse driving circuit is at high level or at low level, a switching discharge unit for forming a discharge path through which electric charges charged in a capacitor are discharged by switching of a switch from a non-discharge side to a discharge side, and switching the switch to the discharge side over a discharge maintenance time in a state where the application of a pulse voltage by the pulse driving circuit stops and the output terminal voltage is maintained at high level, a post-discharge detection unit, and a determination unit.

Abstract: A switch-driving circuit suitable for driving a full-controlled power switch combination is disclosed. The switch-driving circuit includes a first pulse-width modulator, a high-voltage isolation pulse transformer module and a plurality of output modules. The high-voltage isolation pulse transformer module includes a magnetic core connected to multiple output modules in a one-to-many way, or includes multiple magnetic cores connected to multiple output modules in a one-to-one way. Each output module includes a second pulse-width modulator and a driving-power amplifier. The full-controlled power switch combination includes a plurality of full-controlled power switches. The driving-power amplifier is coupled between the second pulse-width modulator and one of the full-controlled power switches.

Abstract: A driver circuit has a detector circuit including a high side detection transistor, a resistor, and a low side detection transistor connected to a high side output transistor and a low side output transistor. A clamping circuit converts a high voltage amplitude change signal generated at a connection point of the high side detection transistor and resistor to a signal clamped to a voltage range applied on the low side. An OR circuit outputs a signal taking the logical sum of an inverted control signal and an output of a low side first stage drive circuit. A level shifter circuit outputs a level-shifted signal of the OR circuit to a high side first stage drive circuit. A second OR circuit outputs a signal wherein the logical sum of an output signal of the clamping circuit and the control signal is inverted to the low side first stage drive circuit.

Abstract: A drive control apparatus for a semiconductor device having a diode and a transistor includes: a current detection device of a current flowing through the diode; and a control device, which applies a gate drive voltage to the semiconductor device when an on-instruction signal is input. The control device compares the current detection signal with a current threshold value during a first period, in which the on-instruction signal is input, after a second period has elapsed from gate drive voltage application time, or gate drive voltage shut-off time. A transient variation is generated on the current detection signal in the second period. The control device shuts off the gate drive voltage when the current detection signal is equal to or larger than the current threshold value. The control device applies the gate drive voltage when the current detection signal is smaller than the current threshold value.

Abstract: A driver circuit includes an output terminal connected to a gate of a Schottky transistor, a reference transistor formed in the same manner as the Schottky transistor, a resistor connected between a first power source line and a gate of the reference transistor, a voltage generator configured to supply a second node with a voltage equal to or lower than a voltage at a first node between the resistor and the reference transistor, and a switching element configured to transmit the voltage at the second node to the output terminal in response to a signal inputted to an input terminal.

Abstract: A voltage controlled switching element gate drive circuit makes it possible to suppress an occurrence of a malfunction, while suppressing surge voltage, surge current, and switching noise, when switching in a voltage controlled switching element. A gate drive circuit that supplies a gate voltage to the gate of a voltage controlled switching element, thus driving the voltage controlled switching element, includes a high potential side switching element and low potential side switching element connected in series, first variable resistors interposed between at least the high potential side switching element and a high potential power supply or the low potential side switching element and a low potential power supply, and a control circuit that adjusts the resistance values of the first variable resistors.

Abstract: A method of sharing in use an impedance matching circuit of a memory circuit to perform an initial calibration and a full time refresh mode calibration includes supplying power to the memory circuit, utilizing the impedance matching circuit to perform the initial calibration on the memory circuit, the memory circuit exiting the initial calibration, the memory circuit entering a driving mode, the memory circuit exiting the driving mode every a predetermined interval, utilizing the impedance matching circuit to perform the full time refresh mode calibration on the memory circuit according to a refresh command, an output voltage detection circuit determining a level of an output voltage of the memory circuit, and performing a corresponding operation according to a determination result generated by the output voltage detection circuit.

Abstract: A high-side semiconductor-switch driving method includes generating power for controlling a high side semiconductor switch. The high side semiconductor switch has a control terminal and the power allows a current to flow into the control terminal of the high side semiconductor switch to switch the high side semiconductor switch. The voltage at the control terminal of the high side semiconductor switch is quantified. The power dependent on the voltage at the control terminal of the high side semiconductor switch is controlled so that the current provided is increased when the voltage at the control terminal indicates that the current is not sufficient to switch the high side semiconductor switch.

Abstract: Disclosed is a circuit arrangement for generating a drive signal for a transistor. In one embodiment, the circuit arrangement includes a control circuit that receives a switching signal, a driver circuit that outputs a drive signal, and at least one transmission channel. The control circuit transmits, depending on the switching signal for each switching operation of the transistor, switching information and switching parameter information via the transmission channel to the driver circuit. The driver circuit generates the drive signal depending on the switching information and depending on the switching parameter information.

Abstract: Input/output (I/O) line driving circuits are provided. The circuit includes a first I/O line driver and a second I/O line driver. The first I/O line driver receives a first input signal in response to an enable signal to generate a first control signal and drives a first I/O line in response to a second control signal. The second I/O line driver receives a second input signal in response to the enable signal to generate the second control signal and drives a second I/O line in response to the first control signal.

Abstract: A reduced oxide stress cascode stack circuit includes a cascade transistor stack and dynamic bias circuits that supply an output voltage having a magnitude greater than an oxide reliability voltage of their component transistors. The reduced oxide stress cascode stack circuit also includes an offset voltage generator that provides an offset voltage based on a transient extreme of the output voltage, wherein the offset voltage is applied to the cascade transistor stack and the dynamic bias circuits to reduce component transistor voltages commensurate with the oxide reliability voltage. The reduced oxide stress cascode stack circuit further includes a bias voltage supply that modifies a bias voltage value of the cascade transistor stack and dynamic bias circuits by an amount proportional to the offset voltage. A method of reducing oxide stress in a cascode stack circuit is also provided.

Abstract: A ringing suppression circuit for a communication circuit that performs communication through a transmission line includes a high side switch connected between a high potential reference point and a high side line of the transmission line, a low side switch connected between a low potential reference point and a low side line of the transmission line, and a ringing suppression section. The ringing suppression section turns on the high side switch based on a difference between a potential of the high side line and a potential applied to a control terminal of the high side switch. The ringing suppression section turns on the low side switch based on a difference between a potential of the low side line and a potential applied to a control terminal of the low side switch.