Abstract: An oscillator circuit includes an integrator, a comparator, an edge triggered flip-flop, and first and second capacitors. The edge triggered flip-flop has an input terminal coupled to an output terminal of the comparator and is configured to output first and second signals which are mutually exclusive, and to flip the signals when detecting a rising or falling edge output by the comparator such that: when the first signal is at a designated level, the first capacitor is charged and the second capacitor is discharged, and a terminal of the first capacitor is coupled to an input terminal of the integrator; and when the second signal is at a designated level, the second capacitor is charged and the first capacitor is discharged and a terminal of the second capacitor is coupled to the input terminal of the integrator.

Abstract: The present disclosure is generally directed to an ultrasonic transducer interface system for use within portable 2-D ultrasonic imagers and includes an on-chip adaptive beamformer and Charge-Redistribution TX (CR-TX) to provide a drive strength of up to 500 pF/channel at 5 MHz (or 10 nF at 250 kHz) while reducing the TX drive power by at least 30% compared to other ultrasonic transducer TX drivers. The ultrasonic transducer interface system can be implemented in a single chip via, for example, a complementary metal oxide semiconductor (CMOS) process.

Abstract: An electronic circuit according to an embodiment includes a clock generator, a delay element, a first electromagnetic coupler, a first frequency converter, a second electromagnetic coupler, a second frequency converter, a controller and an output device. The clock generator is configured to generate a first clock signal. The delay element is configured to output a second clock signal which has a phase delayed with respect to the first clock signal. The first electromagnetic coupler is configured to transmit one of the first and second clock signals by electromagnetic coupling. The first frequency converter is driven by the one of the first and second clock signals transmitted from the first electromagnetic coupler and is configured to convert a first input signal to a first signal with a first frequency corresponding to the one of the first and second clock signals.

Abstract: A method for receiving a broadcast signal by an access network to a plurality of terminals of a two-way wireless communication system. An information signal is formed from the broadcast information destined for the terminals. A pilot signal is formed and a broadcast signal including the information signal SI1 and the pilot signal is transmitted. The information signal and the pilot signal are transmitted on different respective central frequencies having a predefined frequency gap.

Abstract: A method for transmitting and receiving a broadcast signal by an access network to a plurality of terminals of a two-way wireless communication system. An information signal is formed from the broadcast information destined for the terminals. A pilot signal is formed and a broadcast signal including the information signal SI1 and the pilot signal is transmitted. The information signal and the pilot signal are transmitted on different respective central frequencies having a predefined frequency gap.

Abstract: Systems and methods for amplifying signals. In some embodiments, the signals may be amplified using a diode steering network with an amplifier operated in class AB mode. In some embodiments, distortion in the amplified signal may be corrected using a feed forward cancellation circuit operated in class A mode.

Abstract: A system is provided for generating a ramping signal. The system includes a plurality of storage circuits each including an input and an output. The output of a previous storage circuit is connected to the input of a next storage circuit. The storage circuits are configured to propagate a first enable signal based on a first control signal. The system also includes a plurality of first current generating circuits. Each first current generating circuit is coupled to the output of a corresponding storage circuit to receive the propagated first enable signal. The first current generating circuits are configured to generate a first current signal based on the propagated first enable signal.

Abstract: Described herein is an apparatus and system for generating a signal with phase angle configuration. The apparatus comprises an array of switch-resistors, each switch resistor to receive a control signal, wherein the array of switch-resistors to generate an output signal; and a circuit to configure phase angle of the output signal. The apparatus can be used for different package and inductor configurations. The apparatus provides flexibility to mitigate switching noise by adjusting phase angles, and provides the ability to enable and disable switch-resistors on the fly without ripples. The apparatus also saves power consumption by selectively turning off switch-resistors when phases are disabled. The output signal of the apparatus has smooth triangular waveforms for improving the quality of power supply generated using the output signal. Overall, the apparatus exhibits reduced sensitivity to process variations compared to traditional signal generators.

Abstract: In one embodiment, a method comprises generating a first current at a current source having a magnitude based on the magnitude of a second current flowing from a capacitive node of a touch sensor in the absence of a touch with respect to the capacitive node. The method further includes generating a third current from the capacitive node of the touch sensor in the presence of a touch with respect to the capacitive node. The first current and the third current are summed to cancel out at least a portion of the third current. The method further includes integrating, by an integrator, the sum of the first current and the third current to generate an output voltage.

Abstract: A circuit includes a control circuit coupled to detect whether an electrical energy source is coupled to an input of a power converter. A switch is coupled to the control circuit to transfer energy from the input of the power converter to an output of the power converter during a first operating mode. The control circuit is coupled to drive the switch in the first operating mode when the electrical energy source is coupled to the input of the power converter. The control circuit is coupled to drive the switch in a second operating mode when the electrical energy source is uncoupled from the input of the power converter. The control circuit is coupled to discharge a capacitance coupled between input terminals of the power converter through the switch to a threshold voltage in less than a maximum period of time in the second operating mode.

Abstract: A stepped ramp signal generator includes a ramp signal generation unit configured to provide final values of previous stepped ramp signals as initial values of the next stepped ramp signals. The ramp signal generation unit includes a plurality of matching resistors, and a plurality of holders installed between the matching resistors, each holder storing a final value across a previous matching resistor and providing the final value to a next matching resistor.

Abstract: A ramp signal generator includes a rising-edge current unit, a falling-edge current unit and a current-voltage converter. The rising-edge current unit provides a rising-edge output current that sequentially increases or decreases in synchronization with rising edges of a clock signal. The falling-edge current unit provides a falling-edge output current that sequentially increases or decreases in synchronization with falling edges of the clock signal. The current-voltage converter outputs a ramp voltage by converting a summed current of the rising-edge output current and the falling-edge output current.

Abstract: A fully integrated ramp generator circuit includes a first current generator that sources current to first capacitor through a first transistor that is gate controlled by the complement of a periodic signal. The ramping voltage stored on the first capacitor is buffered to an output node as a ramp output signal. A second transistor couples the output node to the first current generator and is gate controlled by the periodic signal. The periodic signal is generated at the output of a flip-flop that receives an input clock signal and reset signal. The reset signal is generated by a comparator circuit operable to compare the voltage on a second capacitor to a reference. The second capacitor is charged by a second current source and discharged by a third transistor that is gate controlled by the periodic signal.

Abstract: A method for generating a ramp comprises providing a voltage reference source, providing a summing amplifier, providing n switched capacitor elements coupled in parallel between the voltage reference source and the summing amplifier, and selectively activating a predetermined number of the switched capacitor elements to first store charge on each activated switched capacitor element and then to measure the sum of the charges on the activated capacitor switch elements in each of a fixed-integer number of time slots in a cyclical manner, the predetermined number being between 0 and n.

Abstract: A ramp signal generator includes: a row decoder which receives a row control signal from a timing controller and generates one or more row select signals, a first column decoder which receives a first column control signal from the timing controller and generates one or more first column select signals, a second column decoder which receives a second column control signal from the timing controller and generates one or more second column select signals, and a current cell array which is activated by the one or more first column select signals, the one or more second column select signals, and the one or more row select signals, and includes at least one current cell which generates at least one unit current, and generates an output current by summing the generated at least one unit current.

Abstract: A stepped ramp signal generator includes a ramp signal generation unit configured to provide final values of previous stepped ramp signals as initial values of the next stepped ramp signals. The ramp signal generation unit includes a plurality of matching resistors, and a plurality of holders installed between the matching resistors, each holder storing a final value across a previous matching resistor and providing the final value to a next matching resistor.

Abstract: A fully integrated ramp generator circuit includes a first current generator that sources current to first capacitor through a first transistor that is gate controlled by the complement of a periodic signal. The ramping voltage stored on the first capacitor is buffered to an output node as a ramp output signal. A second transistor couples the output node to the first current generator and is gate controlled by the periodic signal. The periodic signal is generated at the output of a flip-flop that receives an input clock signal and reset signal. The reset signal is generated by a comparator circuit operable to compare the voltage on a second capacitor to a reference. The second capacitor is charged by a second current source and discharged by a third transistor that is gate controlled by the periodic signal.

Abstract: A local oscillator circuit for a signal transmitter or receiver, the circuit comprising: an input for receiving a master oscillating signal from a master oscillator; and signal processing circuitry configured to be clocked by the master oscillating signal to generate a local oscillator signal, the signal processing circuitry being such that the local oscillator signal has substantially no harmonic content at any integer multiple of the frequency of the master oscillator signal, which oscillates at (2n+1)/2 times the frequency of the generated local oscillator signal, with n being a positive integer.

Abstract: A signal processing circuit includes: a reference signal generating circuit that generates a reference signal of a ramp waveform of which a voltage value varies with the lapse of time by changing a current; and a signal processing unit including a plurality of processing sections that process the reference signal as a ramp wave and a potential of a supplied analog signal, wherein the reference signal processing circuit has a function of adjusting an offset of the reference signal by adjusting the current from the time of starting the generation of the reference signal or adjusting the level of the reference signal at least at the time of starting the generation of the reference signal.

Abstract: According to a first aspect of the present invention there is provided a signal generation system for generating a predetermined analog signal. The system comprises a clock generator (1) adapted for generating on the basis of an external clock signal a predetermined clock signal, a signal generator including a first gain stage (21) and a second gain stage (22) adapted for providing an overall gain of the signal generator and outputting a stepped analog signal, an analog filter (23) adapted for filtering the stepped analog signal output by the second gain stage and for outputting the predetermined analog signal, and a first and a second clock mapping units (3,4) adapted for receiving the predetermined clock signal, and respectively supplying to the first and second gain stages non-overlapped clock signal, wherein the amount of gain provided by the first and second gain stages is controlled by the non-overlapped clock signals.

Abstract: A local oscillator circuit for a signal transmitter or receiver, the circuit comprising: an input for receiving a master oscillating signal from a master oscillator; and signal processing circuitry configured to be clocked by the master oscillating signal to generate a local oscillator signal, the signal processing circuitry being such that the local oscillator signal has substantially no harmonic content at any integer multiple of the frequency of the master oscillator signal, which oscillates at (2n+1)/2 times the frequency of the generated local oscillator signal, with n being a positive integer.

Abstract: A clock frequency modulator for an oscillator having a digital circuit for the generation of a signal modulating the clock frequency, the digital circuit adapted to obtain, from the signal generated by the oscillator, a first pulse signal having a lower frequency than the clock frequency of the oscillator, a digital counter adapted to count the pulses of the first signal and to produce a digital signal and a digital-to-analog converter adapted to convert the digital signal in the signal for modulating the clock frequency of the oscillator.

Abstract: A stepwise voltage ramp generator includes a tank capacitor, a terminal of which is coupled to a reference potential to be charged with a voltage ramp. A transistor couples the tank capacitor to a supply line. A diode-connected transistor, biased with a bias current is coupled to the transistor to form a current mirror. A by-pass switch is electrically coupled in parallel to the diode-connected transistor, and is controlled by a PWM timing signal, the duty-cycle of which determines a mean slope of the generated voltage ramp.

Abstract: A control circuit for controlling a motor. The control circuit includes a control module, a current transformation module and a comparison module. The control module generates a control current and a comparison voltage according to a first current, a first voltage and an input voltage. The current transformation module, coupled to the control module, generates a first output voltage from a first output terminal and a second output voltage from a second output terminal. The comparison module, coupled to the control module and the current transformation module, compares a threshold voltage, the first output voltage, the second output voltage, and the comparison voltage and generates a plurality of control signals to control the motor.

Abstract: Systems and methods are disclosed for providing a temporarily modified output. A waveform control provides a control output that temporarily adjusts to an intermediate level between normal high and low levels during a first operating mode. The waveform control provides the control output to transition periodically between the high and low levels during a second operating mode. A delay network controls the waveform control to provide the output at the intermediate level for a duration during the first operating mode.

Abstract: A control terminal driver circuit for a switching amplifier including a driver for each of a pair of output power transistors responsive to a PWM information signal. The circuit operates in response to an operating state signal indicating a start up condition for the amplifier to vary the amplitude of the drive pulses for the output transistors between a zero value and a maximum value for normal operation of the amplifier over a start up interval, and to reverse the process during a shut down interval. A DC offset detector is provided to detect a DC offset at amplifier output, and an error circuit responsive to an output of the DC offset detector controls the relative amplitude of the driver outputs during at least a portion of the start up interval to substantially eliminate the DC offset. Also disclosed is a switching amplifier including a control terminal driver circuit as described above.

Abstract: AC to DC inverters that are formed from electronic switches, such as MOSFETs, that are controlled by gating pulses obtained from comparators. The comparators compare a varying signal against two closely spaced reference voltages so as to provide gating pulses with delays needed to prevent shoot-through in the electronic switches.

Abstract: In a method for prescribing an essentially linear ramp with a prescribable slope by a quantity, and which is clock-pulse-controlled and which describes the ramp by an increment per clock interval, the ramp is described by a number of regular increments and by at least one first and one second irregular increment. The regular increments exhibit a value corresponding to the prescribable slope. The irregular increments exhibit a value deviating from the prescribable slope. The first irregular increment is a first increment describing the ramp and the second irregular increment is a last increment describing the ramp.

Abstract: Switching apparatus for switching on and off one or more microwave tubes. A preferred embodiment of the switching apparatus comprises a solid state magnetron switcher that switches a plurality of magnetrons on and off using a plurality of high voltage (IGBT) switches. The microwave tubes or magnetrons are driven from a single power supply. The technical approach employed in the present invention places all microwave tubes or magnetrons into low level oscillation prior to switching them into full conduction. This maintains minimal voltage across the high voltage switches while allowing only a small percentage (1-2%) of full load current to be drawn.

Abstract: A pulse shaper for integrated service digital network (ISDN) U-interface. The pulse shaper of the present invention includes a couple of control clock generators, a clock-controlled fully differential switched-capacitor integrator, a fully differential sample and hold circuit, and a fully differential line driver/Rauch lowpass filter. The pulse shaper converts four-level 2B1Q digital input code (D0 and D1) to five staircase-type analog waveform by using fully differential switched-capacitor integrator. The sample and hold circuit then eliminates the spikes in the five-stair waveform and improve the signal linearity. The lowpass filter and telephone line driver is utilized to perform the output signal to comply with the waveform specification of ANSI T1 5.3.2.1 and 5.3.2.2.

Abstract: The period of an input signal is subdivided into N parts by carrying out a count, during this period, of the pulses delivered by a clock. This number is divided by N and then the remainder of this division is distributed among all the N parts of the period of the input signal. This technique may be applied to the generation of scanning signals in television.

Abstract: A step generator 800 including at least one gate 805 and a voltage divider 806 coupled to an output of gate 805. The selected node of voltage divider 806 provides an output V.sub.OUT of generator 800. Circuitry 801 presents a signal to an input of gate 805 to initiate current flow through voltage divider 806.

Abstract: An apparatus for controlling an electrical appliance coupled with an output terminus and configured to operate in response to an alternating input signal, such as input AC power. The apparatus comprises a reference signal generator for receiving the input signal and generating a reference signal (either V.sub.RAMP or V.sub.CONTROL) in response to the input signal, and a control circuit for controlling connection of the input signal to the output terminus in response to the reference signal and to a user-defined set-point signal. The control circuit is coupled with the reference signal generator and with a set-point terminal. The set-point terminal receives the set-point signal and the control circuit controls connection of the input signal with the output terminus in response to a predetermined relationship between the reference signal and the set-point signal; the apparatus is capable of generating a modified periodically interrupted AC power output based on an AC power input.

Abstract: An integrated circuit driver for providing data to a communications channel comprises first and second output buffers coupled to first and second output conductors (e.g. bondpads) respectively. Each output buffer comprises a multiplicity of pull-up transistors and a multiplicity of pull-down transistors coupled to the associated output conductor through pull-up resistors and pull-down resistors, respectively. A multiplicity of delay circuits coupled to a data input node supply delayed data signals to the control terminals of the pull-up and pull-down transistors. Control circuitry is included for selectively activating the delay circuits. In a typical case, the control circuitry comprises multiplexers each having an output that is coupled to the input of a corresponding delay circuit. Advantages of the technique include a constant output impedance and waveshaping of the data output for reduction of harmonics.

Abstract: The present invention relates to a circuit for controlling output voltage from a charge pump, and more particularly to a charge pump which can reduce the chip area in a way that allows the output from the charge pump to be outputted at multi levels making use of a P-N junction breakdown voltage in the NMOS transistor.

Abstract: In a signal transmission circuit having a plurality of signal lines for supplying potentials to load capacitances, in which each load capacitance is driven by each signal line, each signal line can be connected to another signal line via a switch. By connecting two signal lines at different potentials to each other by means of said switch, the potentials of the signal lines are changed through the process of charge redistribution, thereby eliminating charging and discharging through a power-source line and a ground line. Therefore, if n load capacitances are equal to each other, the switches are controlled so that the potential variation of each of the signal lines is phase shifted from those of its adjacent signal lines by 1/n. Thus, the load capacitances can be driven with 1/n of the total amount of charge consumed in the case of driving the n load capacitances independently, thereby reducing the consumed current.

Abstract: An improved output driver circuit for a semiconductor integrated circuit device, wherein a stepped control voltage generation circuit is connected to the gate of a driving transistor for driving an output terminal DQ. The stepped control voltage generation circuit responds to an applied input data signal to provide a stepped control voltage changing in a stepped form including a plurality of steps to the gate of the driving transistor. The driving transistor therefore changes its state on a step by step basis from a cut off state to a conduction state. Thus, sharp change in output current flowing through the output terminal can be prevented, and noise caused by a parasitic inductance can be avoided, thus preventing an erroneous operation in the device.

Abstract: A counter circuit converts a full count to a zero count and a zero count to a full count. An incrementing counter circuit according to the present invention has a plurality of threshold circuits with stepwise thresholds. An output of the highest threshold circuit is used as a cut off signal for other threshold circuits. A decrementing counter circuit according to the present invention has a plurality of threshold circuits from the lowest threshold to the highest thresholds. An output of the lowest threshold circuit is used as a closing signal for other threshold circuits.

Abstract: A transceiver for transmitting and receiving digital data represented as stair-stepped sinusoidal waveforms over twisted pair lines interconnecting nodes of a network. The transmitter of the transceiver converts square waves into the stair stepped sinusoidal waveforms by utilizing a number of current sources for supplying differing amounts of current to a resistor coupled across the twisted pair lines. Shift registers control a set of switches which control the direction and the amount of current flowing through the resistor. Thereby, the output voltage across the resistor can be controlled to produce the stair-stepped sinusoidal waveform by clocking the digital signal to the shift registers. The receiver of the transceiver re-converts received stair-stepped sinusoidal waveforms back to their respective digital signals.

Abstract: A current source is provided according to the present invention. The current source includes N current sources configured in a parallel arrangement, wherein N is at least two. Each of the N current sources includes a respective control input. The current source also includes M delay elements. An mth one of the M delay elements includes an input in communication with an m?1th one of the M delay elements. M is equal to N?1, and an output of the mth one of the M delay elements is arranged in communication with the control input of an m+1th one of the N current sources.