Abstract: A load control device may control power delivered to an electrical load from an AC power source. The load control device may include a controllably conductive device adapted to be coupled in series electrical connection between the AC power source and the electrical load, a zero-cross detect circuit configured to generate a zero-cross signal representative of the zero-crossings of an AC voltage. The zero-cross signal may be characterized by pulses occurring in time with the zero-crossings of the AC voltage. The load control device may include a control circuit operatively coupled to the controllably conductive device and the zero cross detect circuit. The control circuit may be configured to identify a rising-edge time and a falling-edge time of one of the pulses of the zero-cross signal, and may control a conductive state of the controllably conductive device based on the rising-edge time and the falling-edge time of the pulse.

Abstract: Disclosed embodiments select a proper hum frequency reference by utilizing one or more functional logic circuits within a cluster. The slowest logic circuit is determined, and an instance of that logic circuit is used in timing circuitry for the cluster. Multiple logic circuits with similar characteristics are incorporated into the timing circuit. Each cluster is interconnected to a second level timing circuit. Each cluster inputs timing information into the second level timing circuit. The second level timing circuit then determines when the next cycle, or tic, of the self-generated clock starts, and the process repeats, providing a self-generated clock signal.

Abstract: In an approach for generating a file, a computer generates a modified layout for an integrated circuit. The computer receives a draft layout for an integrated circuit. The computer identifies a resonator, wherein the resonator comprises a capacitor connected to ground and an inductor connected to a clock grid. The computer creates alternative resonator wiring of the received draft layout associated with the identified resonator. The computer generates a modified draft layout based on the created alternative resonator wiring for the integrated circuit.

Abstract: An automated test equipment (ATE) system includes a plurality of test blades each coupled to a test blade connector and mounted on a circular track; a central reference clock (CRC) having an origin point at a center of the circle; and a clock/sync connector coupled to the CRC through a zero skew clock connection to one or more sync buses, wherein each instrument utilizes the CRC to coordinate its testing process with another instrument.

Abstract: Embodiments described herein include a quadrature phase corrector (QPC) which includes multiple differential amplifies for correcting the phase of one or more clock signals. In one embodiment, the differential amplifiers are arranged in an input stage, cross-coupled stage, and ring stage. The input stage receives and buffers the input clock signal (or signals). The cross-coupled stage includes one or more latches that force one clock signal high and another low which causes the QPC to oscillate. The ring stage outputs four clock signals with adjusted phases relative to the input clock signals. In one example, the ring stage outputs a quadrature clock signal that includes four clock signals phase shifted by 90 degrees.

Abstract: A spread-spectrum clock generator has a phase-locked loop locked to a reference signal that gives a stable-frequency output to a variable phase shifter. The variable phase shifter provides a spread-spectrum clock output because its phase-shift is determined by a pseudorandom sequence generator and the pseudorandom sequence generator changes its output regularly or irregularly within limits. The clock generator performs a method of generating a spread-spectrum clock including locking the phase-locked loop to the reference signal, and phase shifting the stable frequency signal by a phase-shift determined by the pseudorandom sequence generator; and changing the phase-shift determined by the pseudorandom sequence generator. Since phase shifting is performed open-loop, total phase shift is defined by design.

Abstract: A data processing circuit includes a delay circuit configured to delay a data signal and generate delayed data signals each having a different delay; and an output control circuit configured to output a first data signal among the delayed data signals as a data signal sampled at a first edge of a sampling clock signal, and output a second data signal among the delayed data signals as a data signal sampled at a second edge of the sampling clock signal.

Abstract: A source driving device includes a locking module, a controlling module and a decoding module. The locking module executes a locking process selectively in a first band or a second band according to a band setting signal in order to lock a first clock signal synchronized with a first display signal. The controlling module is coupled to the locking module for comparing a control voltage with a reference voltage in the locking process and generates the band setting signal accordingly. The decoding module is coupled to the locking module for generating a decoded signal according to the first display signal and the first clock signal.

Abstract: Apparatus for use in one of a plurality of sensors each having a respective transmitter which transmits pulses for sensing, a respective clock which controls timing of the pulses transmitted from the respective transmitter, and a respective receiver which receives echoed instances of the pulses. The apparatus comprises: sensing logic configured to sense a being or object in dependence on the echoed pulses received back by the respective receiver from the respective transmitter, and timing logic configured to compensate for a clock discrepancy between the respective clock and that of one or more others of the sensors. The timing logic does this by using the respective receiver to listen for instances of the pulses from the one or more other sensors, and adjusting the timing of the pulses from the respective transmitter based thereon.

Abstract: An interference processing method comprises: receiving a multi-carrier modulated signal, wherein the multi-carrier modulated signal comprises multi-carrier modulation symbols; discomposing the multi-carrier modulation symbols into a set of subcarriers, wherein the set of subcarriers at least comprises a target subcarrier; equalizing the target subcarrier to obtain an equalized target subcarrier; obtaining an error power of the equalized target subcarrier; and comparing the error power of the equalized target subcarrier with a predefined threshold to determine the existence of interference in the target subcarrier, wherein the predefined threshold is associated with a minimum distance between two constellation points of a modulation constellation of the target subcarrier.

Abstract: The present invention is directed to communication systems. According to embodiments of the present invention, a communication system includes at least two communication lanes and a skew management module. The skew management module generates a control current based on output test patterns of the two communication lanes. The control current is integrated and compared to a reference voltage by a comparator, which generates an analog offset signal. A PLL of one of the communication lanes generates a corrected clock signal that is adjusted using the analog offset signal to remove or adjust the skew between the communication lanes. The corrected clock signal is used for output data. There are other embodiments as well.

Abstract: A transmission apparatus includes: a generator configured to generate position information indicating a position of header information of each of a plurality of first signals from a second signal nesting the plurality of first signals; a storage configured to store the position information generated by the generator and the plurality of first signals; a monitor configured to read the position information and the plurality of first signals stored in the storage, and to monitor the header information of each of the plurality of first signals based on the position information; and an output unit configured to output the plurality of first signals after monitoring the contents of the header information.

Abstract: Embodiments include systems and methods for applying a controllable early/late offset to an at-rate clock data recovery (CDR) system. Some embodiments operate in context of a CDR circuit of a serializer/deserializer (SERDES). For example, slope asymmetry around the first precursor of the channel pulse response for the SERDES can tend to skew at-rate CDR determinations of whether to advance or retard clocking. Accordingly, embodiments use asymmetric voting thresholds for generating each of the advance and retard signals in an attempt to de-skew the voting results and effectively tune the CDR to a position either earlier or later than the first precursor zero crossing (i.e., h(?1)=0) position. This can improve link margin and data recovery, particularly for long data channels and/or at higher data rates.

Abstract: A semiconductor apparatus may include a burst operation sensing unit and the interface circuit. The burst operation sensing unit may be configured to generate operation mode conversion signals based on current operation state information and a level variation of at least one signal transmission line. The interface circuit may include one or more analog circuits enabled according to the operation mode conversion signals.

Abstract: Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes an input pad, an input buffer including a first input node and a second input node, a switch that couples the first input node and the second input node in an active state and further decouples the first input node and the second input node in an inactive state, a control circuit that provides a signal causing the switch to be in the active state or an inactive state. The first input node of the input buffer is coupled to the input pad by a conductive wiring.

Abstract: A source synchronous data transmission system includes a data transmitting device and a data receiving device. A dedicated data line carries a data signal from the data transmission device to the data receiving device. A dedicated clock line carries a modulated clock signal from the data transmission device to the data receiving device. The data transmission device includes a clock data driver configured to encode data into the modulated clock signal by modulating an amplitude of the modulated clock signal. Thus, the clock line of the source synchronous data transmission system carries the clock signal and additional data.

Abstract: Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain, output the event to another timing domain, and further configured to mark the event as transferred. An example method includes receiving an Event In based in a first timing domain at a first latch and receiving an intermediate event from the first latch by a second latch. The event is transferred to a second timing domain by the second latch and the first latch is reset based on feedback.

Abstract: A sensor such as a presence sensor for use in a lighting system or other system that adapts to information from a plurality of active presence sensors. If transmissions from the active sensors are uncoordinated, the overall detection performance may be adversely impacted (e.g. due to potential cross-interference), which may make sensing over the detection coverage area defined by a single presence sensor (or the like) become unreliable. The disclosure presents protocols for coordinating transmissions in active sensing systems. The invention may be applied to various active modalities (e.g. ultrasound, RF), for example that find applications in indoor and outdoor lighting controls.

Abstract: A hybrid numeric-analog clock synchronizer, for establishing a clock or carrier locked to a timing reference. The clock may include a framing component. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip. It may comprise a numeric time-locked loop (TLL) with an analog phase-locked loop (PLL). Moreover a high-performance number-controlled oscillator (NCO), for creating an event clock from a master clock according to a period control signal. It processes edge times rather than period values, allowing direct control of the spectrum and peak amplitude of the justification jitter. Moreover a combined clock-and-frame asynchrony detector, for measuring the phase or time offset between composite signals. It responds e.g. to event clocks and frame syncs, enabling frame locking with loop bandwidths greater than the frame rate.

Abstract: Techniques relating to providing clock signals to a storage element. Generally, different portions of a given storage element may be clocked according to different schemes. This technique may be pertinent to a storage element that has a portion for which the associated bit values do not change frequently relative to another portion of the storage element. For such a storage element, a high-frequency portion may be clocked upon an access to the storage element, while a low-frequency portion may be clocked only if there is a change in the associated bit values. This technique can be applied to various storage elements, including registers and FIFO buffer entries. An apparatus may be designed such that the low-frequency and high-frequency portions of a storage element do not change during operation. Alternatively, the low-frequency and high-frequency portions of the storage element may be changeable based on a current operating mode of the apparatus.

Abstract: Disclosed are a data transmission method and a data restoration method. The data transmission method forming a plurality of transmission preparatory packets by dividing data to be transmitted by a predetermined number (n) of bits, forming a plurality of transition inducing packets having the predetermined number (n) of bits, different from the transmission preparatory packets, and not complementary to the transmission preparatory packets, and forming transition included data packets by performing a logical operation on the transition inducing packets and the respective transmission preparatory packets, transmitting the transition included data packets and the different transition inducing packets, wherein the forming of the transition included data packets comprises: forming the transition included data packets by performing the logical operation on periodically repeated packet bundles and different transition inducing packets.

Abstract: A clock driver control scheme for a resonant clock distribution network provides robust operation by controlling a pulse width of the output of clock driver circuits that drive the resonant clock distribution network so that changes are sequenced. The clock driver control circuit controls the clock driver circuits in the corresponding sector according to a selected operating mode via a plurality of control signals provided to corresponding clock driver circuits. The pulse widths differ for at least some of the sectors during operation of digital circuits within the integrated circuit having clock inputs coupled to the resonant clock distribution network. The different pulse widths may be a transient difference that is imposed in response to a mode or frequency change of the global clock that provides an input to the clock driver circuits.

Abstract: A clock generation circuit generates clock signals of a requested frequency and relative phase by dividing a reference clock signal by counting reference clock signal pulses in a counter circuit. The clock generation circuit changes the frequency, and optionally also the phase, of an output clock signal upon request, without generating glitches or missing pulses. The clock generation circuit does not alter the frequency of the output clock signal until a phase pulse associated with the requested phase is asserted, and the counter circuit is in a predetermined state, such as a reset state.

Abstract: A driving circuit and a shift register circuit are disclosed. The driving circuit includes a plurality of cascaded multi-stages shift register circuits. Each of the shift register circuit includes a transmission door latch circuit and a signal transmission circuit. The transmission door latch circuit includes a transmission door, first clock signals triggering the transmission door such that transmission signals of two stages ahead are transmitted to the signal transmission circuit via the transmission door to generate transmission signals for the current stage. Second clock signals control the transmission signals of the current stage to pass through the signal transmission circuit to generate gate driving signals for the current stage. In this way, the driving circuit is feasible for CMOS manufacturing process, and owns the advantages such as low power consumption and high noise tolerance.

Abstract: Systems, apparatuses, and methods for performing common mode extraction for data communication are disclosed. A circuit is configured to receive a single-ended data signal on a first input port and couple the data signal to a positive input terminal of a receiver component. The circuit is also configured to receive a differential clock signal on second and third input ports and generate a reference signal from the differential clock signal. In one embodiment, the reference signal is generated from an average of the differential clock signal. The circuit is configured to couple the reference signal to a negative input terminal of the receiver component. In one embodiment, the receiver component is an amplifier.

Abstract: Under control of a first transmission code controlling section, a first radar transmitting section periodically transmits a first radar transmission signal with a first transmission period based on a first transmission trigger signal produced after elapse of a first delay time period from reception of a predetermined synchronization establishment signal by a first transmission trigger signal producing section. Under control of a second transmission code controlling section, a second radar transmitting section periodically transmits a second radar transmission signal with a second transmission period similarly. In accordance with the first delay time period and the second delay time period, arrival times of interference signals from the first radar transmitting section and the second radar transmitting section are within transmission zones of the second radar transmission signal and the first radar transmission signal.

Abstract: A device with an I/O interface includes a replica clock distribution path matched to a clock distribution path of an unmatched receiver circuit. The device can monitor changes in delay in the replica path, and adjust delay in the real clock distribution path in response to the delay changes detected in the replica path. The receiver circuit includes a data path and a clock distribution network in an unmatched configuration. A ring oscillator circuit includes a replica clock distribution network matched to the real clock distribution network. Thus, delay changes detected for the replica clock distribution network indicates a change in delay in the real clock distribution network, which can be compensated accordingly.

Abstract: A clock driver control scheme for a resonant clock distribution network provides robust operation by controlling a pulse width of the output of clock driver circuits that drive the resonant clock distribution network so that changes are sequenced. The clock driver control circuit controls the clock driver circuits in the corresponding sector according to a selected operating mode via a plurality of control signals provided to corresponding clock driver circuits. The pulse widths differ for at least some of the sectors during operation of digital circuits within the integrated circuit having clock inputs coupled to the resonant clock distribution network. The different pulse widths may be a transient difference that is imposed in response to a mode or frequency change of the global clock that provides an input to the clock driver circuits.

Abstract: A routing network is associated with a logic island in a logic block of a programmable logic device and includes switches for each of feedback, street, and highway networks. Some of the switches include multiple stages. The street network switch receives the signals from the feedback network switch, signals from neighboring highway network switches, and direct feedback from selected logic island outputs and provides outputs to the logic island. The street network switch includes multiple stages, where outputs to the logic island are provided directly by each stage in the street network switch. The output terminals of a first stage of the street network switch that are connected to the logic island are also connected to the second stage of the street network switch. The second stage of the street network switch receives feedback output signals from the feedback network and directly from the associated logic island.

Abstract: A semiconductor device may include: a variable delay circuit configured to delay a data strobe signal according to a delay control signal and output a delayed data strobe signal; a data sampler configured to compare a level of a reference voltage and a value of a data signal in synchronization with the delayed data strobe signal, and determine a logic level of the value of the data signal, the data signal having a training pattern; and a control circuit configured to determine a delay amount of the data strobe signal and generate the delay control signal and the reference voltage according to an output signal of the data sampler.

Abstract: Filter circuits with emitter follower transistors and servo loops, and associated methods and apparatuses, are disclosed herein. In some embodiments, a filter circuit may include: a resistor-capacitor network having an input to receive an input signal; an emitter follower transistor, coupled to the resistor-capacitor network, wherein the filter circuit has an output to provide an output signal from the emitter of the emitter follower transistor; a current source to provide a constant reference current; and a current-buffering servo loop circuit, coupled to the emitter follower transistor and the current source, including a current buffer and a controlled current sink to maintain the collector current and the emitter current of the emitter follower transistor equal to the constant reference current.

Abstract: Disclosed is a method for detecting clock tampering. In the method a plurality of resettable delay line segments are provided. Resettable delay line segments between a resettable delay line segment associated with a minimum delay time and a resettable delay line segment associated with a maximum delay time are each associated with discretely increasing delay times. A monotone signal is provided during a clock evaluate time period associated with a clock. The monotone signal is delayed using each of the plurality of resettable delay line segments to generate a respective plurality of delayed monotone signals. The clock is used to trigger an evaluate circuit that uses the plurality of delayed monotone signals to detect a clock fault.

Abstract: A method for performing phase shift control for timing recovery in an electronic device and an associated apparatus are provided, where the method includes: generating an output signal of an oscillator, wherein a phase shift of the output signal of the oscillator is controlled by selectively combining a set of clock signals into the oscillator according to a set of digital control signals, and the set of clock signals is obtained from a clock generator, wherein the phase shift corresponds to the set of digital control signals, and the set of digital control signals carries a set of digital weightings for selectively mixing the set of clock signals; and performing timing recovery and sampling on a receiver input signal of a receiver in the electronic device according to the output signal of the oscillator to reproduce data from the receiver input signal.

Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a bit lag control element, and a synchronous lag receiver that is configured to receive one of a plurality of radially distributed strobes and a data bit, and that is configured to delay registering of the data bit by a propagation time. The replica radial distribution element is configured to receive a first signal, and is configured to generate a second signal, where the replica radial distribution element comprises replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The bit lag control element is configured to measure a propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a value on a lag bus that indicates the propagation time.

Abstract: A method that compensates for misalignment on a synchronous data bus. The method includes: replicating propagation path lengths, loads, and buffering of a radial distribution network for a strobe, receiving a lag pulse signal, and generating a replicated strobe signal by employing the replicated propagation path loads lengths, and buffering; measuring the time between assertion of the lag pulse signal and assertion of the replicated strobe signal; on a lag bus, generating a value that indicates the time; within a synchronous lag receiver, receiving a first one of a plurality of radially distributed strobes and a data bit, and delaying registering of the data bit by the time.

Abstract: A method for aligning signals on a bus, including: replicating propagation path lengths, loads, and buffering of a radial distribution network for a strobe; receiving a first signal, and generating a second signal by employing the replicated propagation path lengths, loads, and buffering; receiving control information over a standard JTAG bus, wherein the control information indicates an amount to adjust a propagation time; and measuring the propagation time beginning with assertion of the first signal and ending with assertion of the second signal, said measuring comprising: selecting one of a plurality of successively delayed versions of the first signal that coincides with assertion of the second signal; adjusting the propagation time by the amount prescribed by the control information to yield an adjusted propagation time; and gray encoding the adjusted propagation time to generate a value on a lag bus.

Abstract: The present invention is directed to communication systems. According to embodiments of the present invention, a communication system includes at least two communication lanes and a skew management module. The skew management module generates a control current based on output test patterns of the two communication lanes. The control current is integrated and compared to a reference voltage by a comparator, which generates an analog offset signal. A PLL of one of the communication lanes generates a corrected clock signal that is adjusted using the analog offset signal to remove or adjust the skew between the communication lanes. The corrected clock signal is used for output data. There are other embodiments as well.

Abstract: In one aspect, a transistor comprises a metal emitter, a first semiconductor barrier, a metal base, a second semiconductor barrier, and a metal collector. The first semiconductor barrier separates the metal emitter and the metal base and has an average thickness based on a first mean free path of a charge carrier in the first semiconductor barrier emitted from the metal emitter. The second semiconductor barrier separates the metal base from the metal collector and has an average thickness based on a second mean free path of the charge carrier in the second semiconductor barrier injected from the metal base. The metal base comprises two or more metal layers and has an average thickness based on a multi-layer mean free path of the charge carrier.

Abstract: A data control circuit includes an output stage circuit, a switch circuit, and an impedance module. The output stage circuit outputs a data signal. An input terminal of the switch circuit is coupled to an output terminal of the output stage circuit, and an output terminal of the switch circuit is coupled to a post-stage circuit. According to a control of a control signal, the switch circuit determines whether to transmit the data signal of the output stage circuit to the post-stage circuit. The impedance module is configured in the output stage circuit, configured between the output stage circuit and the switch circuit, or configured in the switch circuit. Here, the impedance module reduces noise flowing from the switch circuit to the output stage circuit.

Abstract: A rotational synchronizer for metastability resolution is disclosed. A synchronizer includes a plurality of M+1 latches each coupled to receive data through a common data input. The synchronizer further includes a multiplexer having a N inputs each coupled to receive data from an output of a corresponding one of the M+1 latches, and an output, wherein the multiplexer is configured to select one of its inputs to be coupled to the output. A control circuit is configured to cause the multiplexer to sequentially select outputs of the M+1 latches responsive to N successive clock pulses, and further configured to cause the M+1 latches to sequentially latch data received through the common data input.

Abstract: An integrated circuit may have two signal paths: an open-loop modulator (which may comprise a digital-input Class-D amplifier) and a closed-loop modulator (which may comprise an analog-input Class-D amplifier). A control subsystem may be capable of selecting either of the open-loop modulator or the closed-loop modulator as a selected path based on one or more characteristics (e.g., signal magnitude) of an input audio signal. For example, for higher-magnitude signals, the closed-loop modulator may be selected while the open-loop modulator may be selected for lower-magnitude signals. In some instances, when the open-loop modulator is selected as the selected path, the closed-loop modulator may power off, which may reduce power consumption. In addition, one or more techniques may be applied to reduce or eliminate user-perceptible audio artifacts caused by switching between the open-loop modulator and the closed-loop modulator, and vice versa.

Abstract: An embodiment integrated circuit (IC) clock distributor system includes a first IC. The first IC includes a clock synchronizer circuit and a clock generator circuit. The clock synchronizer circuit includes a first input coupled to a first clock transfer path including a replica delay of a portion of a first signal path included in an external IC. The clock synchronizer circuit also includes a second input coupled to a second clock transfer path. The clock generator circuit also includes an input coupled to an output of at least one of a reference oscillator and the clock synchronizer circuit. Delay of the second clock transfer path includes delay of the first signal path.

Abstract: A configurable clock circuit on an integrated circuit, such as an integrated circuit memory, can be configured to utilize external multiple phase clocks and external single phase clocks to produce an internal clock signal in a form compatible with the integrated circuit.

Abstract: Circuits and methods for detecting write operation and limiting cell current in resistive random access memory (RRAM or ReRAM) cells are provided. RRAM cells can include a select transistor and a programmable resistor. Current can flow through the programmable resistor responsive to word line voltage VWL applied to the gate of the select transistor and a bit line voltage VBL applied to the source of the select transistor. Responsive to the current, the programmable resistor can change between relatively high and low resistances (“SET”), or between relatively low and high resistances (“RESET”). It can be desirable to accurately characterize the resistance of the programmable resistor, that is, to accurately detect write operations such as SET or RESET. Additionally, it can be undesirable for the current to exceed a certain value (“over-SET”). The present circuits and methods can facilitate detecting write operations or limiting current, or both, in an RRAM cell.

Abstract: A radio transceiver is disclosed. It comprises a first transceiver circuit and a second transceiver circuit, the latter requiring an LO signal having higher LO frequency than the former. It further comprises a frequency synthesizer comprising a first clock-signal generator adapted to generate the LO signal for the first transceiver circuit based on a first reference oscillation signal and a second clock-signal generator adapted to generate the LO signal for the second transceiver circuit based on a second reference oscillation signal, which is or is derived from the LO signal for the first transceiver circuit. A radio communication apparatus comprising the radio transceiver is also disclosed.

Abstract: Embodiments include apparatuses, methods, and systems for crosstalk compensation. In embodiments, a transmitter may include a crosstalk compensation circuit that may receive a victim data signal and one or more attacker data signals. The crosstalk compensation circuit may adjust the timing of transitions in the victim data signal based on detected transitions in the one or more attacker data signals. Other embodiments may be described and claimed.

Abstract: A PLC network system and method operative with OFDM for generating MIMO frames with suitable preamble portions configured to provide backward compatibility with legacy PLC devices and facilitate different receiver tasks such as frame detection and symbol timing, channel estimation and automatic gain control (AGC), including robust preamble detection in the presence of impulsive noise and frequency-selective channels of the PLC network. A PLC device may include a delayed correlation detector and a cross-correlation detector operating in concert to facilitate preamble detection in one implementation.

Abstract: A delay-locked loop (DLL) has a fractional phase frequency (PF) detector that reduces false locking and harmonic locking. The PF detector has a trunk, an upper branch, a lower branch, and a logic module. A delay line provides the PF detector a set of fractional phase-delayed clock signals that are used to prime and/or activate corresponding flip-flops of the trunk, upper branch, and lower branch in a sequence. The use of flip-flops in the lower branch activated by different fractional phase-delayed clock signals avoids false locking and harmonic locking over a wider range of initial delay magnitudes than conventional DLLs.

Abstract: A clock generating apparatus and a fractional frequency divider thereof are provided. The fractional frequency divider includes a frequency divider (FD), a plurality of samplers, a selector and a control circuit. An input terminal of the FD is coupled to an output terminal of a multi-phase-frequency generating circuit. Input terminals of the samplers are coupled to an output terminal of the FD. Trigger terminals of the samplers receive the sampling clock signals. The input terminals of the selector are coupled to output terminals of the samplers. An output terminal of the selector is coupled to a feedback terminal of the multi-phase-frequency generating circuit. The control circuit provides a fraction code to a control terminal of the selector, so as to control the selector for selectively coupling the output terminal of one of the samplers to the feedback terminal of the multi-phase-frequency generating circuit.

Abstract: Systems and methods are directed to a three-phase non-volatile flip-flop (NVFF), which includes a master stage formed from a dual giant spin Hall effect (GSHE)-magnetic tunnel junction (MTJ) structure, with a first GSHE-MTJ and a second GSHE-MTJ coupled between a first combined terminal and a second combined terminal, and a slave stage formed from a first inverter cross-coupled with a second inverter. A first data value is read out from the slave stage during a read phase of the same clock cycle that a second data value is written into the master stage during a write phase. The three-phase NVFF includes three control signals, for controlling an initialization phase of the slave stage, the read phase, and the write phase.