Abstract: A multi-valued logic (MVL) circuit includes a MVL clock generator that generates a MVL clock signal having three or more ith MVL levels, a single MVL clock signal distribution network connected to the MVL clock generator, and three or more ith MVL selection circuits connected to the single MVL clock signal distribution network where i=0 to N and N>=3. Each ith MVL selection circuit corresponds to a specified ith MVL level. The ith MVL selection circuit outputs an ith binary clock signal having: (a) a first logic level whenever the MVL clock signal is equal to the ith MVL level and the ith data input receives the first logic level, (b) a second logic level whenever the MVL clock signal is equal to the ith MVL level and the ith data input receives the second logic level, and (c) a previous logic level of the ith binary clock signal whenever the MVL clock signal is not equal to the ith MVL level.

Abstract: A trigger signal detection apparatus includes: a clock gating circuit which is supplied with a trigger signal and a clock signal and outputs the clock signal; a trigger signal processing circuit which outputs a first signal only for a predetermined time when the clock signal is supplied from the clock gating circuit; a counter which operates in response to the trigger signal, thus outputting a count value of the clock signal; and a time set-up circuit which outputs a second signal to the trigger signal processing circuit when count value supplied from the counter reaches a preset value, and the trigger signal processing circuit stops outputting the first signal when the trigger signal processing circuit receives the second signal.

Abstract: A multi-channel isolation system has N+1 isolators for N channels of communication data. N of the isolators may transfer data signals across an isolation barrier, one for each of the N channels of data. An N+1st isolator transfers refresh signals representing state of the data signals on the N isolators. Receiver circuitry, therefore, may receive signals from the N isolation channels without risk for collision with refresh signals. If reception of the refresh signals becomes necessary, circuitry on a receive side of the isolator may switch over to the N+1st receive path to output state data contained in the refresh signals.

Abstract: A clock generation system for an integrated circuit (IC) chip (e.g., a microcontroller) is disclosed that allows digital blocks and other components in the IC chip to start and stop internal clocks dynamically on demand to reduce power consumption.

Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

Abstract: A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The clock/data recovery circuit may also include an oscillator coupled to the edge detector circuit. The oscillator locks onto a target data rate prior to receipt of the serial data burst and locks onto a phase of the serial data burst in response to the reset signal. The clock/data recovery circuit may also include a phase detector circuit that receives the serial data burst. The phase detector circuit is coupled to the oscillator. The phase detector circuit adjusts the oscillator to maintain the lock onto the phase of the serial data burst during the serial data burst.

Abstract: The described embodiments include a computing device with one or more asynchronous circuits and control circuits that control the operation of the asynchronous circuits. In some embodiments, the control circuits are arranged in a hierarchy with a top-level control circuit atop the hierarchy and one or more local control circuits lower in the hierarchy. In these embodiments, the top-level control circuit processes operating information for the one or more asynchronous circuits and/or other functional blocks in the computing device to determine an operating state for the computing device. Based on the operating state, the top-level control circuit communicates commands to the local control circuits to cause the local control circuits to operate in corresponding operating modes. Based on a corresponding operating mode command, each local control circuit sets one or more operating parameters for corresponding asynchronous circuits (and/or one or more other functional blocks).

Abstract: A multi-channel isolation system has N+1 isolators for N channels of communication data. N of the isolators may transfer data signals across an isolation barrier, one for each of the N channels of data. An N+1st isolator transfers refresh signals representing state of the data signals on the N isolators. Receiver circuitry, therefore, may receive signals from the N isolation channels without risk for collision with refresh signals. If reception of the refresh signals becomes necessary, circuitry on a receive side of the isolator may switch over to the N+1st receive path to output state data contained in the refresh signals.

Abstract: A signal generating circuit for generating a fan driving signal includes a phase adjusting circuit, a direct digital frequency synthesizer, a first operating circuit, a driving signal generator and a second operating circuit. The phase adjusting circuit receives a hall signal and adjusts a phase of the hall signal to generate a synchronization signal. The direct digital frequency synthesizer generates a modulating signal according to the synchronization signal. The first operating circuit receives a load current and generates a modulated signal according to the load current. The driving signal generator generates an original driving signal according to the synchronization signal. The second operating circuit generates a control signal according to the modulating signal and the modulated signal. The original driving signal is selectively outputted as the fan driving signal in response to the control signal.

Abstract: Apparatuses, circuits, and methods are disclosed for reducing or eliminating unintended operation resulting from metastability in data synchronization. In one such example apparatus, a sampling circuit is configured to provide four samples of a data input signal. A first and a second of the four samples are associated with a first edge of a latching signal, and a third and a fourth of the four samples are associated with a second edge of the latching signal. A masking circuit is configured to selectively mask a signal corresponding to one of the four samples responsive to the four samples not sharing a common logic level. The masking circuit is also configured to provide a decision signal responsive to selectively masking or not masking the signal.

Abstract: An apparatus comprises a clock and data recovery system, and a loss of lock detector at least partially incorporated within or otherwise associated with the clock and data recovery system. The loss of lock detector is configured to generate a loss of lock signal responsive to phase adjustment requests generated for a clock signal in the clock and data recovery system. By way of example, the loss of lock signal may have a first logic level indicative of the phase adjustment requests occurring at a first rate associated with a lock condition and a second logic level indicative of the phase adjustment requests occurring at a second rate lower than the first rate. Absolute values of respective phase increments each associated with multiple up and down phase requests may be accumulated, and the loss of lock signal generated as a function of the accumulated phase increment absolute values.

Abstract: Apparatuses, circuits, methods, and other embodiments associated with digital power on reset are described. In one embodiment, an apparatus includes a digital electronic component configured to produce a clock signal. A first counter is configured to output a first count signal based on the clock signal and a second counter is configured to output a second count signal based on the clock signal. A power on reset logic is configured to provide a power on reset signal based on the first count signal and the second count signal, where the power on reset logic is configured to disable the digital electronic component after providing the power on reset signal to prevent the digital electronic component from drawing power.

Abstract: Techniques for clock gating a synchronizer are described herein. In one embodiment a circuit for clock gating a synchronizer comprises a clock-gating circuit configured to receive an input clock signal, and to selectively provide either the input clock signal or a fixed clock signal to the synchronizer. The circuit also comprises a comparator configured to compare a data value of a data signal input to the synchronizer, a first value of the synchronizer, and a second value of the synchronizer with one another, to instruct the clock-gating circuit to provide the input clock signal to the synchronizer if the data value, the first value, and the second value are not all the same, and to instruct the clock-gating circuit to provide the fixed clock signal to the synchronizer if the data value, the first value, and the second value are all the same.

Abstract: A clock and data recovery device receives a serial data stream and produces recovered clock and data signals. The clock and data recovery device operates over a range of frequencies and without use an external reference clock. A first loop supplies a first clock signal to a second loop. The second loop modifies the first clock signal to produce the recovered clock signal and uses the recover clock signal to produce the recovered data signal. The first loop changes the frequency of the first clock signal based on frequency comparison and data transition density metrics.

Abstract: Some of the embodiments of the present disclosure provide a integrated circuit comprising a plurality of components, wherein each of the plurality of components is configured to receive a clock signal and a reset signal; a clock module configured to selectively suppress the clock signal; and a reset module configured to assert the reset signal while the clock signal is suppressed. Other embodiments are also described and claimed.

Abstract: In a multiphase electrical power assignment, a processor: receives instructions to connect a bi-directional power device to a multiphase premise power source; determines that the power device is to be coupled to a target phase's phase connection; confirms that the power device is not coupled to any phase connections; and couples the power device to the phase connection, where the power device's power signal is synchronized with the phase connection's power signal. When the power device is in a connected state, the processor: issues a command to place each phase connection switch in an open state; in response to confirming that the phase connection switches are in the open state, issues commands to the power device so that a power signal of the power device will be synchronized with the target phase; and closes the phase connection switch corresponding to the target phase.

Abstract: A radio frequency (RF) system is disclosed. The RF system includes an RF sensor, an analog to digital converter (ADC) module, a processing module, and a synchronization module. The RF sensor measures a parameter of an RF output and generates an RF signal based on the parameter. The ADC module converts samples of the RF signal into digital values. The processing module generates processed values based on the digital values. The synchronization module outputs one of the processed values in response to a transition in the RF output.

Abstract: Methods and apparatus are provided for digital linearization of an analog phase interpolator. Up to 2N desired phase values are mapped to a corresponding M bit value, where M is greater than N. A corresponding M bit value is applied to the phase interpolator to obtain a desired one of the 2N desired phase values. A linearized phase interpolator is also provided that accounts for process, voltage, temperature or aging (PVTA) variations.

Abstract: An integrated circuit package including an induction-coupled clock distribution system is disclosed. An exemplary embodiment of the disclosure includes a transmission module coupled to a main clock line, a clock reception module coupled to the transmission module, the clock reception module including a clock output line, and an electronic circuit coupled to the clock output line of the clock reception module, the electronic circuit including at least one clocked element and configured to operate synchronously with a clocking signal received through the clock output line of the clock reception module. The transmission module may be disposed on the supporting case of the IC package, and the electronic circuit and the clock reception module may be disposed on the semiconductor die of the IC package.

Abstract: Certain aspects of the present disclosure provide techniques for reducing the amount of storage needed for detecting a primary synchronization signal (PSS). According to certain aspects, a user equipment may store a limited number of samples corresponding to the strongest peaks per PSS index and perform PSS detection based on an analysis of the limited number of stored samples.

Abstract: A synchronization method for current differential protection comprises: selecting a point on the transmission line protected by the current differential protection; measuring the current and the voltage of each of the terminals of said transmission line; calculating the compensating voltage at the selected point respectively according to the measured current and the voltage of the each terminal; detecting and calculating the synchronization error by comparing all the compensating voltages.

Abstract: A jitter monitor includes: a voltage generating circuit configured to generate a first voltage that is varied with time at a predetermined inclination; a voltage reducing circuit configured to reduce the first voltage by a predetermined voltage in synchronization with a first clock signal so as to generate a second voltage that is varied with time at the predetermined inclination in synchronization with the first clock signal; and a sampling circuit configured to sample a portion having the predetermined inclination of the second voltage.

Abstract: A system including a power supply and a clock circuitry to generate a plurality of clock signals. Each clock signal is synchronous with a primary clock signal. First, second, and third clock signals of the plurality of clock signals are asynchronous to each other. The system further includes a plurality of switches. Each switch of the plurality of switches is communicatively coupled to the power supply and the clock circuitry. A first switch of the plurality of switches receives the first clock signal, a second switch of the plurality of switches receives the second clock signal, and a third switch of the plurality of switches receives the third clock signal.

Abstract: A clock and data recovery (CDR) circuit having a phase locked module and a frequency locked module is provided. A phase detector of the phase locked module compares a phase of an input data stream with a phase of a data-recovery clock to output an adjusting signal. The frequency locked module performs a first-order integration process and a second-order integration process on the adjusting signal to generate a first integration error and a frequency control signal. The phase locked module generates a phase control signal according to the first integration error and the adjusting signal. An oscillation circuit of the frequency locked module generates at least one reference clock according to the frequency control signal. A phase converter of the phase locked module outputs the data-recovery clock to the phase detector according to the phase control signal and the reference clock.

Abstract: An apparatus and method of generating a pseudo noise (PN) code is provided. The apparatus for generating the PN code includes: a memory device unit including a plurality of memory devices; an exclusive-OR (XOR) operation unit receiving output values of at least two memory devices among output values of the plurality of memory devices to output an XOR operation value with respect to the received output values; and a PN code generation unit generating the PN code based on an output value of the XOR operation unit.

Abstract: A system including an input module, a first gain module, a second gain module, and a preamble estimation module. The input module is configured to receive an input signal from a station. The input signal includes (i) a first preamble sequence, and (ii) subcarriers. The first gain module is configured to, based on the input signal, generate first channel gain values. Each of the first channel gain values is for a respective one of the subcarriers. A second gain module is configured to, based on the first channel gain values, generate second channel gain values. A preamble estimation module is configured to estimate the first preamble sequence based on (i) the first channel gain values, and (ii) the second channel gain values.

Abstract: Disclosed herein is a device comprising a first terminal for a first clock signal, a second terminal for a second clock signal substantially complementary to the first clock signal, a third terminal for a third clock signal, a fourth terminal for a fourth clock signal substantially complementary to the third clock signal, a first logic gate to produce a first intermediate signal, a second logic gate to produce a second intermediate signal, a first delay circuit to produce a third intermediate signal, and a second delay circuit to produce a fourth intermediate signal, and a first output circuit coupled to the first and second delay circuits to produce the third and fourth clock signals respectively at the third and fourth terminals.

Abstract: A method for reducing signal edge jitter in an output signal from a numerically controlled oscillator includes processing an input signal with a first accumulator to provide a first accumulator output signal and continuing to use a carry in the processing of the input signal with the first accumulator in the event of an overflow. The method further includes processing the input signal with a second accumulator to provide a second accumulator output signal and rejecting a carry in the processing of the input signal with the second accumulator in the event of an overflow. The method further includes outputting the second accumulator output signal at an output of the numerically controlled oscillator and synchronizing the second accumulator using the first accumulator output signal.

Abstract: A signal input circuit and method and chip are disclosed. The signal input circuit includes a control signal input terminal configured for receiving a control signal; at least one common signal input terminal each configured for receiving a corresponding common signal; at least one first signal output terminal each configured for outputting a corresponding first signal; at least one first signal unit each configured for receiving said corresponding common signal and outputting said corresponding common signal as said corresponding first signal under control of said control signal; at least one second signal output terminal each configured for outputting a corresponding second signal; and at least one second signal unit each configured for receiving said corresponding common signal and outputting said corresponding common signal as said corresponding second signal under control of said control signal.

Abstract: Methods and apparatuses are provided that allow for the synchronization of an operating point transition in an embedded system environment. Identification of an upcoming operating point transition, operating point transition constraints, and maximum parking latency parameters is provided. Then, an ordering of seizing bus activity as well as an ordering of resuming bus activity is determined. The operating point transition is then implemented using the determined ordering. Simulation and determination of change of successfully completing operating point transition prior to initiating and while the transition is pending are also provided.

Abstract: A source driver with an automatic de-skew capability is configured to receive a data signal and a clock signal from a timing controller, which are configured to drive a liquid crystal display panel. The source driver includes a signal delay unit, a setup time register, a hold time register, a first signal delay unit, a second delay unit and a logic circuit. In one embodiment of the present disclosure, the first data delay signal is configured to sample the second clock delay signal and the second data delay signal is configured to sample the first clock delay signal.

Abstract: A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly.

Abstract: A receiving apparatus includes a symbol timing detection unit, a Fourier transform unit, a first symbol timing correction unit, and an interpolation synthesis unit. The symbol timing detection unit is configured to detect a Fourier transform start position from a received transmitting signal of a symbol unit, the Fourier transform unit is configured to perform a Fourier transform using the detected Fourier transform start position. The first symbol timing correction unit is configured to calculate and correct an amount of change between the Fourier transform start position of a reference symbol and the detected Fourier transform start position, and the interpolation synthesis unit is configured to perform an interpolation synthesis of a plurality of delay profiles corresponding to a plurality of symbols including the reference symbol and a symbol in which the amount of change is corrected.

Abstract: A mobile communication device is provided that has a transceiver including a voltage controlled oscillator (VCO) and a calibration circuit for calibrating the VCO. The calibration circuit includes a logic block configured to estimate a calibration value for a tuning of the VCO to a desired frequency, and an asynchronous counter configured to execute a counting sequence to identify a frequency of the VCO after the tuning of the VCO using the calibration value, where the calibration circuit is configured to determine a tuned calibration value for producing the desired frequency from the counting sequence.

Abstract: In some embodiments, provided are calibration techniques for measuring mismatches between TDL delay stage elements, and in some cases, then compensating for the mismatches to minimize performance degradation.

Abstract: A system and method for data sending and receiving processing using a secondary data transmit channel is disclosed. The system comprises a device and a device base in which a secondary data transmit channel on the device is enabled when the device is coupled to the device base and receives a triggering signal from the device base. The system implements a 2T2R RF design in which the use of an additional data transmit channel increases the uplink transmit gain and coverage and reduces the deployment costs of base stations.

Abstract: A differential amplifier may be configured to have a duty cycle and/or gain that is adjustable, such as by adjusting the switch points of circuitry in the differential amplifier. The differential amplifier may alternatively or additionally have a hysteresis function by, for example, using a signal feedback from the output of the amplifier to adjust the switch points of circuitry in the differential amplifier. The differential amplifier may be used for a variety of purposes, such as in an input buffer or delay line, either of which may be used, for example, in a clock generator circuit.

Abstract: A signal receiving circuit includes a phase detection unit and a delay control unit. The phase detection unit detects a phase difference between a received signal and a clock signal. The delay control unit receives the phase difference, delays a phase of the received signal in a range not exceeding a delay amount determined by using a predetermined phase difference as a unit, and changes, when the phase difference exceeds the predetermined phase difference, a delay amount of the received signal by using the predetermined phase difference as a unit.

Abstract: Apparatuses and methods for compensating for differing power supply sensitivities of a circuit in a clock path. One such method includes altering signal timing of at least one of reference and feedback clock signals differently according to variations in power supply voltage to compensate for differences in delay power supply sensitivities of delays of a forward clock path and of a feedback clock path. Another example method includes providing an output clock signal in phase with an input clock signal and compensating for delay error between delays used in providing at least some of the delay of the output clock signal relative to the input clock signal by providing delays having power supply sensitivities resulting in a combined power supply sensitivity that is inverse to the delay error.

Abstract: A semiconductor device includes a comparison unit configured to compare the phases of a plurality of clocks having different frequencies and output a phase comparison signal, a phase inversion control unit configured to generate a phase inversion control signal, and a start control unit configured to generate a start control signal in response to a clock enable signal, wherein the comparison unit is configured to start an operation in response to the start control signal and invert, in response to the phase inversion control signal, a phase of an internal clock generated from one of the plurality of clocks when the plurality of clocks have different phases.

Abstract: A system including a demodulation module, a metric generation module, and a preamble detection module. The demodulation module is configured to generate demodulated signals based on demodulating, in accordance with a differential demodulation scheme, signals received from a base station. The signals received from the base station include a plurality of symbols. The demodulated signals comprise a plurality of real parts each having a corresponding magnitude. The metric generation module is configured to generate a plurality of metrics for the plurality of symbols based on the corresponding magnitudes of the plurality of real parts of the demodulated signals. The preamble detection module is configured to detect, based on the plurality of metrics, whether the plurality of symbols in the signals received from the base station includes a preamble symbol.

Abstract: A transmission interface includes a first pin, a second pin, a conversion unit, and a decoding unit. The conversion unit receives a serial input data stream via the first pin and receives a serial clock via the second pin. The conversion unit converts the serial input data stream to parallel input data and converts the serial clock to a parallel clock. The serial input data stream has a full swing form. The decoding unit receives and decodes the parallel input data and generates an input data signal according to the decoded parallel input data.

Abstract: A method and system for synchronizing the output signal phase of a plurality of frequency divider circuits in a local-oscillator (LO) or clock signal path is disclosed. The LO path includes a plurality of frequency divider circuits and a LO buffer for receiving a LO signal coupled to the plurality of frequency divider circuits. The method and system comprise adding offset voltage and setting predetermined state to each of the frequency divider circuits; and enabling the frequency divider circuits. The method and system includes enabling the LO buffer to provide the LO signal to the frequency divider circuits after they have been enabled. When the LO signal drives each of the frequency divider circuits, each of the frequency divider circuits starts an operation. Finally the method and system comprise removing the offset voltage from each of the frequency divider circuits to allow them to effectively drive other circuits.

Abstract: The present invention provides a synchronization signal processing method and apparatus, which solves problems of low accuracy and a slow speed of synchronization operation executed on the synchronization signal. The specific steps include: acquiring multiple to-be-processed signals of a power supply, where the to-be-processed signals are signals changing periodically; generating a synchronization signal that has the same period as the to-be-processed signals by generating pulses in each period of the to-be-processed signals, where each period of the synchronization signal includes at least two pulses; detecting whether the synchronization signal is normal by determining whether parameters of all the pulses in the synchronization signal are accurate; and if the synchronization signal is normal, synchronizing the to-be-processed signals by performing time alignment on the pulses in the synchronization signal.

Abstract: Source-synchronization between a source module and a responder module generally includes providing, at the source module, an initial determinism reconciliation signal, propagating the initial determinism reconciliation signal from the source module to the responder module and back to the source module to produce a received determinism reconciliation signal, and compensating for an intrinsic delay of the circuit based on the initial determinism reconciliation signal and the received determinism reconciliation signal.

Abstract: Control circuitry and adjustable clock signal generation circuitry is provided to control the signal transmission rate for electronic devices and systems of electronic devices. The control circuitry may receive status signals indicating current clock rates of a signal transmitting and receiving circuit as well as current processing capacity from the signal receiving circuit. The control circuitry may then generate control signals which control adjustable clock signal generation circuitry. The adjustable clock signal generation circuitry may be used to adjust the rate of generated clock signals for the signal transmitting and receiving circuits which can increase or decrease the signal transmission rate between those circuits.

Abstract: An interface board includes a synchronizer that synchronizes a first time that is a time of the interface board to a base time based on a master synchronization signal that is supplied by an external master time source and that defines the base time. The interface board also includes a comparator that compares a phase of a first synchronization signal that synchronizes to the first time with a phase of a shared synchronization signal sent by an interface controller that controls the interface board, and a notifier that notifies another interface board of a comparison result of the comparator.

Abstract: A clock data recovery circuit includes a phase detector circuit, a majority voter circuit, and a phase shift circuit. The phase detector circuit is operable to compare a phase of a periodic signal to a phase of a data signal to generate a phase error signal. The majority voter circuit includes a shift register circuit. The shift register circuit is operable to generate an output signal based on the phase error signal. The majority voter circuit is operable to generate a majority vote of the phase error signal based on the output signal of the shift register circuit. The phase shift circuit is operable to set the phase of the periodic signal based on the majority vote generated by the majority voter circuit.

Abstract: A data processing circuit that holds a state of a clock signal of each phase of an input multi-phase clock at a timing of an input latch clock, the multi-phase clock including clock signals of a plurality of phases sequentially shifted at certain intervals determined in advance, and generates a digital signal obtained by digitizing the states of the phases of the multi-phase clock at a timing at which the latch clock is input, the data processing circuit including: a latch portion including n latch unit groups (n is an integer of a power of 2) including the same number and a plurality of latch units, each latch unit holding the state of the clock signal of the corresponding phase of the multi-phase clock and outputting an output signal indicating the held state of the clock signal.

Abstract: For example, a semiconductor device includes a first latency counter, which selects whether to give an odd-cycle latency to an internal command signal; and a second latency counter, which gives a latency to an internal command signal at intervals of two cycles. The latency counters are connected in series. Since the number of bits in control information, which is used to set a latency, is smaller than the types of settable latency as a result, it is possible to reduce wiring density.