Abstract: A digital filter with a pipeline structure includes processing structures timed by respective clock signals. Each processing structure in turn is formed by a number of processing modules for processing input samples. A phase generator aligns the processing modules with the input samples so that each input sample is processed by a respective one of the processing modules. An up-sampling buffer and a down-sampling buffer are used when the processing structures operate at different clock frequencies (thus implementing different clock domains) so as to convert signal samples between the clock domains for processing in the processing structures.

Abstract: Differential clock phase imbalance can produce undesirable spurious content at a digital to analog converter output, or interleaving spurs on an analog-to-digital converter output spectrum, or more generally, in interleaving circuit architectures that depend on rising and falling edges of a differential input clock for triggering digital-to-analog conversion or analog-to-digital conversion. A differential phase adjustment approach measures for the phase imbalance and corrects the differential clock input signals used for generating clock signals which drive the digital-to-analog converter or the analog-to-digital converter. The approach can reduce or eliminate this phase imbalance, thereby reducing detrimental effects due to phase imbalance or differential clock skew.

Abstract: A method for providing network time synchronization using a redundant grandmaster includes sensing a loss of the grandmaster. A sync message is generated according to a sensed result. The generated sync message is transmitted through a clock master port.

Abstract: According to one embodiment, a phase estimating device includes a periodic signal obtaining unit that obtains a first periodic signal, and a wireless time synchronizing unit that synchronizes a reference time with that of a signal generating device by wirelessly communicating with the signal generating device that outputs a second periodic signal according to phase information. The phase estimating device includes a reference time storing unit that stores the reference time synchronized with that of the signal generating device by the wireless time synchronizing unit. The phase estimating device includes a phase determining unit that obtains sampled times from the reference time storing unit at timing at which the first periodic signal rises above or falls below a predetermined level, and determines phase information on a phase of the first periodic signal based on the obtained sampled time and period information on a period of the first periodic signal.

Abstract: A circuit includes first and second aligner circuits and a deskew circuit. The first aligner circuit is operable to align a first input serial data signal with a control signal to generate a first aligned serial data signal. The second aligner circuit is operable to align a second input serial data signal with the control signal to generate a second aligned serial data signal. The deskew circuit is operable to reduce skew between the first and the second aligned serial data signals to generate first and second output serial data signals.

Abstract: Receiver synchronization techniques (RST), contributing more accurate synchronization of receiver clock to OFDM composite frame combined with much faster acquisition time and better stability of the receiver clock, and phase and frequency recovery techniques, comprising a software controlled clock synthesizer (SCCS) for high accuracy phase & frequency synthesis producing synchronized low jitter clock from external time referencing signals or time referencing messages wherein SCCS includes a hybrid PLL (HPLL) enabling 1-50,000 frequency multiplication with very low output jitter independent of reference clock quality.

Abstract: A master device and slave devices are connected with each other through an SDA and an SCL, and at least one of a serial communication data signal communicated through the SDA and a serial communication clock signal communicated through the SCL is latched with use of a noise removal clock signal whose frequency is higher than that of the serial communication clock signal, and is taken in.

Abstract: The methods and apparatus disclosed herein provide an operative system for increasing the resolution of serial DRUs based on interleaved free running oversamplers. In particular, this system uses incoming data to measure and to compensate the skew between two or more free running oversamplers (e.g., SerDes), without the need for any hardware design requirement relating to the precision of the relative skew of the oversamplers.

Abstract: A pipeline analog-to-digital converter is disclosed which includes at least one periodic unit consisting of two adjacent stages that jointly use two capacitor networks of the same structure. Each of the capacitor networks includes two identical capacitors, two switches and four terminals. On/off states of the switches and interconnection configuration of the terminals are controlled by clock signals to switch the periodic unit between four possible connection configurations. During operation of the periodic unit, when the upstream stage is in a sampling phase that involves one of the capacitor networks as well as a reference capacitor, the downstream stage uses the other of the capacitor networks to conduct residue amplification; and on the other hand, when the upstream stage is using one of the capacitor networks for residue amplification, the downstream stage relies also on this capacitor network for sampling, leaving the other of the capacitor networks idle.

Abstract: A transmission apparatus for transmitting frames accommodating client data over a transmission network, comprising a clock generation unit that generates a clock for timing processing period of signal processing, a deviation detection unit that detects clock deviation between the clock generated by the clock generation unit and the clock used for timing processing period of signal processing by other transmission apparatus that receives the client data from outside the transmission network and adds them to frames, and a timing generation unit that generates timing signal of processing period of signal processing corrected with the clock deviation.

Abstract: A method and system for synchronizing the output signal phase of a plurality of frequency divider circuits in a local-oscillator (LO) or clock signal path is disclosed. The LO path includes a plurality of frequency divider circuits and a LO buffer for receiving a LO signal coupled to the plurality of frequency divider circuits. The method and system comprise adding offset voltage and setting predetermined state to each of the frequency divider circuits; and enabling the frequency divider circuits. The method and system includes enabling the LO buffer to provide the LO signal to the frequency divider circuits after they have been enabled. When the LO signal drives each of the frequency divider circuits, each of the frequency divider circuits starts an operation. Finally the method and system comprise removing the offset voltage from each of the frequency divider circuits to allow them to effectively drive other circuits.

Abstract: An apparatus for synchronizing an incoming signal with a clock signal comprises two or more synchronizer circuits, wherein each synchronizer circuit receives the incoming signal and the clock signal. Each synchronizer circuit generates a synchronized signal, wherein the state of each synchronized signal changes on a different phase of said clock signal in response to a change of the state of said incoming signal. A decision mechanism circuit receives the synchronized signals generated by each synchronizer circuit, wherein the decision mechanism circuit determines the output signal in response to the change of the state of the incoming signal. The decision mechanism circuit further comprises a memory element having a state which is set according to a previously detected state of said signal, wherein the output signal is determined according to the state of the memory element.

Abstract: A first phase alignment circuit generates an indication of a phase of a first clock signal. A second phase alignment circuit adjusts a phase of a second clock signal based on a data signal. The second phase alignment circuit adjusts the phase of the second clock signal based on the indication of the phase of the first clock signal. The second phase alignment circuit resets an indication of the phase of the second clock signal generated based on the data signal in response to the indication of the phase of the first clock signal. The second phase alignment circuit captures a value of the data signal in response to the second clock signal.

Abstract: A method and a system are provided for variation-tolerant synchronization. A phase value representing a phase of a second clock signal relative to a first clock signal and a period value representing a relative period between the second clock signal and the first clock signal are received. An extrapolated phase value of the second clock signal relative to the first clock signal corresponding to a next transition of the first clock signal is computed based on the phase value and the period value.

Abstract: A data receiver circuit for converting received serial data into parallel data in accordance with a data rate signal and for outputting the converted parallel data, the data receiver circuit includes a clock generator for generating a reference clock based on an input clock, a data latch for latching the received serial data and outputting first latched serial data in accordance with the reference clock, a first data output section for converting the first latched serial data into first parallel data with a first reference clock, in case that the data rate signal indicates a first data rate same as a data rate of the reference clock, and a second data output section for converting the first latched serial data into second parallel data with a second reference clock, in case that the data rate signal indicates a second data rate slower than the data rate of the reference clock.

Abstract: A receiving apparatus includes a symbol timing detection unit, a Fourier transform unit, a first symbol timing correction unit, and an interpolation synthesis unit. The symbol timing detection unit is configured to detect a Fourier transform start position from a received transmitting signal of a symbol unit, the Fourier transform unit is configured to perform a Fourier transform using the detected Fourier transform start position. The first symbol timing correction unit is configured to calculate and correct an amount of change between the Fourier transform start position of a reference symbol and the detected Fourier transform start position, and the interpolation synthesis unit is configured to perform an interpolation synthesis of a plurality of delay profiles corresponding to a plurality of symbols including the reference symbol and a symbol in which the amount of change is corrected.

Abstract: This invention includes a clock tree to which clock signals are distributed, and a phase comparison circuit configured to detect the phase difference between a plurality of feedback clock signals upon receiving the plurality of feedback clock signals output from different branching points of the clock tree. The invention includes a feedback clock signal generation circuit configured to generate a variation-corrected feedback clock signal for correcting a manufacture variation in the semiconductor integrated circuit based on the phase difference detected by the phase comparison circuit. The invention includes a phase regulation circuit configured to delay the clock signal so as to reduce the phase difference between a reference clock signal and the variation-corrected feedback clock signal generated by the feedback clock signal generation circuit.

Abstract: A semiconductor device includes a data input/output circuit that has an ODT function and a DLL circuit that generates an internal clock for determining an operation timing of the data input/output circuit. The DLL circuit has a first mode for controlling a phase of the internal clock in a precise manner and a second mode for operating with low power consumption. When the data input/output circuit does not perform an ODT operation, the DLL circuit operates in the first mode, and when the data input/output circuit performs the ODT operation, the DLL circuit operates in the second mode. In this manner, the operation mode of the DLL circuit is switched over depending on the ODT operation, so that the power consumption in the CDT operation in which strict phase control is not required can be reduced.

Abstract: A clock data recovery circuit includes a phase detector circuit, a majority voter circuit, and a phase shift circuit. The phase detector circuit is operable to compare a phase of a periodic signal to a phase of a data signal to generate a phase error signal. The majority voter circuit includes a shift register circuit. The shift register circuit is operable to generate an output signal based on the phase error signal. The majority voter circuit is operable to generate a majority vote of the phase error signal based on the output signal of the shift register circuit. The phase shift circuit is operable to set the phase of the periodic signal based on the majority vote generated by the majority voter circuit.

Abstract: A semiconductor memory device includes a system clock input block configured to be inputted with a system clock, a data clock input block configured to be inputted with a data clock, a first phase detection block configured to compare a phase of the system clock, generate a first phase detection signal, and determine a logic level of a reverse control signal in response to the first phase detection signal, a second phase detection block configured to compare a phase of a clock acquired by delaying the system clock by a correction time, generate a second phase detection signal, and determine a logic level of a clock select signal in response to the first and second phase detection signals, and a clock select block configured to select and output the data clock or a clock acquired by delaying the data clock.

Abstract: Systems and methods for measuring transmitter and/or receiver I/Q impairments are disclosed, including iterative methods for measuring transmitter I/Q impairments using shared local oscillators, iterative methods for measuring transmitter I/Q impairments using intentionally-offset local oscillators, and methods for measuring receiver I/Q impairments. Also disclosed are methods for computing I/Q impairments from a sampled complex signal, methods for computing DC properties of a signal path between the transmitter and receiver, and methods for transforming I/Q impairments through a linear system.

Abstract: A method of synchronizing clock signals may include generating a replicated delay associated with a delay of a clock signal path. The clock signal path may be associated with communication of a slave clock signal by a master block of a circuit to a slave block of the circuit. The method may further include selecting the slave clock signal from one of multiple clock signals based on the replicated delay. Each of the multiple clock signals may have a same frequency and a different phase.

Abstract: A phase adjusting apparatus includes a comparison code generating section, a calculating section, and a delay section. The comparison code generating section individually generates a first comparison code having a phase of a head code advanced and a second comparison code having the phase of the head code delayed, the head code being included in serial transfer data. The calculating section acquires a direction of adjustment of a phase of the serial transfer data using a comparison result of the head code and the first comparison code and a comparison result of the head code and the second comparison code. The delay section adjusts a delay amount of the serial transfer data based on the direction of adjustment of the phase.

Abstract: A multiphase clock divider includes: a reference clock generator for generating a plurality of reference clocks; and at least one output clock generator including a first multiplexer for selecting to output a selected reference clock, a second multiplexer for selecting to output a first selected input clock, a third multiplexer for selecting to output a second selected input clock, a first flip-flop for outputting a first sampling clock according to the selected reference clock and the first selected input clock, a second flip-flop for outputting a second sampling clock according to the first sampling clock and the second selected input clock, and a fourth multiplexer for selecting to output the first sampling clock or the second sampling clock to generate an output clock.

Abstract: In one embodiment, receiving an Ethernet signal over a channel, the Ethernet signal comprising a preamble frame, an idle frame, and a data frame, the preamble frame comprising one or more preamble codes; synchronizing to the Ethernet signal based on the preamble frame; replicating the one or more preamble codes; and training a decision feedback equalizer (DFE) based on the one or more replicated codes, the training enabling the DFE to use decision values at the DFE output to track channel variations.

Abstract: The data processing unit (15) for a receiver of signals carrying information (1) includes a clock and data recovery circuit (16) on the basis of a data signal (DOUT), and a processor circuit (17) connected to the clock and data recovery circuit. The clock and data recovery circuit is clocked by a local clock signal (CLK) and includes a numerical phase lock loop, in which a numerically controlled oscillator (25) is arranged. This numerically controlled oscillator generates an in-phase pulse signal (IP) and a quadrature pulse signal (QP) at output. The frequency and phase of the pulse signals IP and QP are adapted on the basis of the received data signal (DOUT). The processor circuit is arranged to calculate over time the mean and variance of the numerical input signal (NCOIN) of the numerically controlled oscillator (25), so as to determine the coherence of the data signal if the calculated mean and variance are below a predefined coherence threshold.

Abstract: A bang-bang frequency detector with no data pattern dependency is provided. In examples, the detector recovers a clock from received data, such as data having a non-return to zero (NRZ) format. A first bang-bang phase detector (BBPD) provides first phase information about a phase difference between a sample clock and the clock embedded in the received data. A second BBPD provides second phase information about a second phase difference between the clock embedded in the received data and a delayed version of the sample clock. A frequency difference between the sample clock and the clock embedded in the received data is determined based on the first and second phase differences. The frequency difference can be used to adjust the frequency of the sample clock. A lock detector can be coupled to a BBPD output to determine if the sample clock is locked to the clock embedded in the received data.

Abstract: Generate a series of digital data according to a pair of differential signals received from a low speed universal serial bus. Calibrate coarsely a frequency of an oscillator according to a width of an end-of-packet of the series of digital data. And calibrate finely the frequency of the oscillator according to a width of a SYNC pattern of the series of digital data.

Abstract: A method of operation in a receive circuit is disclosed. The method comprises entering an initialization mode followed by receiving training data from a lossy signaling path. The training data originates from a transmit circuit. The received training data is sampled and minimax transmit equalizer coefficients are generated based on the sampled data. The minimax transmit equalizer coefficients are then transmitted back to the transmit circuit. The initialization mode is exited and an operating mode initiated, where transmit data precoded by the minimax transmit equalizer coefficients is received.

Abstract: In described embodiments, a transceiver includes a clock and data recovery module (CDR) with an eye monitor and a cycle slip monitor. The cycle slip detector monitors a CDR lock condition, which might be through detection of slips in sampling and/or transition timing detection. The cycle slip detector provides a check point to sense system divergence, allowing for a mechanism to recover CDR lock. In addition, when the CDR is out-of-lock, the various parameters that are adaptively set (e.g., equalizer parameters) might be invalid during system divergence. Consequently, these parameters might be declared invalid by the system and not used.

Abstract: An apparatus includes a first oscillator configured to generate a reference signal and a second oscillator configured to generate an output signal having a controllable frequency. The apparatus also includes a frequency difference detector configured to generate a difference signal having a frequency based on a frequency difference between the reference signal and the output signal. The apparatus further includes a discriminator configured to modify the frequency of the output signal based on the difference signal. The frequency difference detector can be configured to generate the difference signal having multiple pulses. The discriminator can be configured to count a number of pulses in the difference signal during a specified time period and to modify the frequency of the output signal based on the counted number of pulses. The specified time period can be adjustable.

Abstract: As a digitized representation of an intermediate frequency television signal moves through a demodulator it undergoes a number of processes, including conversion from an analog signal to a digitized data, digital signal processing of the digitized data, and the like. The rate at which the digitized data moves through the digital signal processor of the demodulator for processing is referred to as the data rate of the DSP. The demodulator can vary the data rate based on a selected television channel, thereby reducing the level of interference at the demodulator resulting from noise.

Abstract: A method for performing delay locked looping upon a received signal which reduces the asymmetry of auto-correlation function resulting from sampling is provided. The received signal is a spread spectrum code signal, and the method includes: generating a plurality of replica spread spectrum code signals according to an estimated code phase delay and phase spacing, the replica spread spectrum code signals having phases respectively different from the phase of the received signal; calculating a spread spectrum code error statistics signal according to the replica spread spectrum code signals and the received signal; and adjusting the estimated code phase delay according to the spread spectrum code error statistics signal and a phase difference between a sampled point of at least one replica spread spectrum code signal and a corresponding signal transition point.

Abstract: The electronic circuit arrangement is used for generating poly-phase sequences as synchronization sequences and/or reference sequences in radio communications systems. It comprises a first adder, a first multiplier, a first register, a second register, a first counter and a trigonometry device. The first adder adds a value (km) formed from the value (k) of the counter to the value (B) of the first register. The first multiplier multiplies the value (A) of the second register by a value (y) formed from the value (B) of the first register and the value (k) of the counter. The trigonometry device forms the real part and the imaginary part of the present value of the poly-phase sequence (ak) from a value formed at least from the output value (wk) of the first multiplier.

Abstract: Apparatus and methods are disclosed, such as those involving deskewing serial data transmissions. One such apparatus includes a plurality of receivers, each of which is configured to receive a serial data stream. Each of the receivers includes a shift register including a plurality of stages arranged in sequence to propagate a stream of characters. Each of the stages is configured to store a character, and shift the character to a next stage in response to a clock signal. The receiver also includes a multiplexer having a plurality of inputs, each of the inputs being electrically coupled to a respective one of the stages of the shift register, and to select one of the stages to generate an output such that the outputs of the multiplexers in the receivers are deskewed.

Abstract: Apparatus and methods are disclosed, such as those involving deskewing serial data transmissions. One such apparatus includes a plurality of receivers, each of which is configured to receive a serial data stream. Each of the receivers includes a shift register including a plurality of stages arranged in sequence to propagate a stream of characters. Each of the stages is configured to store a character, and shift the character to a next stage in response to a clock signal. The receiver also includes a multiplexer having a plurality of inputs, each of the inputs being electrically coupled to a respective one of the stages of the shift register, and to select one of the stages to generate an output such that the outputs of the multiplexers in the receivers are deskewed.

Abstract: A circuit for generating multiphase clock signals and corresponding indication signals is provided. The circuit includes a multiphase clock generation circuit, a DLL circuit, a timing circuit, and a phase comparison circuit. The multiphase clock generation circuit receives an external clock to provide a plurality of first clock signals, phases of which differ from one another. The DLL circuit receives the external clock signal to provide a second clock signal. The timing circuit receives the second clock signal and a comparison signal to provide a plurality of indication signals. Each of the plurality of indication signals has rising edges which lead the rising edges of a corresponding one of the first clock signals. The phase comparison provides the comparison signal if a delayed phase of the corresponding one of the indication signals is within a phase of one of the first clock signals.

Abstract: A signal generation system maintains a phase relationship between output signals of first and second signal generators even when the sampling clock frequency is changed. The signal generators are coupled via a communication means including a dedicated cable where the delay amount of the communication means is known and fixed. The first signal generator provides sampling clock, sequence clock and trigger/event signals to the second signal generator and CPUs of the generators share information via the cable. When the frequency of the sampling clock is changed, the CPU of the first or second signal generator calculates the clock number of the frequency changed sampling clock equivalent to the delay amount of the communication means. A delay circuit of the first signal generator 100 delays the waveform data by one sampling clock based on the calculated value for adjusting phase relationship between the waveform data in the signal generators 1.

Abstract: An arrangement is described in which phase parity or phase opposition between two signals can be determined, and if necessary remedial action may be taken.

Abstract: A mixed-signal radio frequency receiver implements multiple spur avoidance modes to reduce or remove spurs or digital noise injection into the received channel to enhance the receiver performance. The multiple spur avoidance modes are reconfigurable to allow a single mode or multiple modes to be selected for use depending on the application. One or more spur avoidance modes can be selected to enhance the performance of the receiver or the modes can be selected to reduce power consumption. The same spur avoidance circuit is used to support all of the spur avoidance modes by reconfiguring the circuit for each mode or each combination of modes. In another embodiment, a clock masking scheme is applied to align analog and digital clock edges to separate digital activities from sensitive analog activities.

Abstract: A spread spectrum clock generator includes a phase comparator to detect a phase difference between a reference input clock signal and a feedback signal and output a control voltage, a voltage controlled oscillator to generate an output clock signal with a frequency in line with the control voltage, a phase selector to select any of equally divided phases of one cycle of the output clock signal, generate and transmit a phase shift clock signal to the phase comparator as the feedback signal, and a phase controller to decide a phase of the rising edge of the phase shift clock signal and control the phase selector to select the decided phase, and generate a second phase shift amount, decide the rising edge of the phase shift clock signal to and subject the output clock signal to spread spectrum modulation by the second phase shift amount.

Abstract: A clock and data recovery device recovers data from a sequential stream of data that includes bursts of data separated by gaps. Each burst of data arrives with its own phase and with its own deviation from a nominal frequency. The bursts of data begin with a preamble that is utilized to determine the timing of the burst. The clock and data recovery device determines the timing of a burst of data using signals from one or more demultiplexers or samplers. At the start of each burst of data, sampled input signals are analyzed by an edge detector to determine a sample phase for the burst. A selector utilizes the sample phase determined by the edge detector to choose which of the sampled input signals to use to produce output data signals from the clock and data recovery device.

Abstract: In one embodiment, a phase interpolator with a phase range of n degrees, where 0<n?360, and having m reference signals, where m?2, and a control signal as input, and producing an output signal with a phase within the phase range using one or more of the m reference signals based on a control code provided by the control signal. The phase interpolator comprises one or more circuits configured to: divide the phase range of n degrees into k sections, wherein k>m; and for each of the k sections, select a relative gain of one or more weights assigned to the one or more reference signals, respectively, with respect to the control code provided by the control signal.

Abstract: In a semiconductor circuit, a high frequency level detecting unit detects a level of a high frequency component adjusted with a first adjusting unit, and a first control unit controls a first gain of the adjusting unit according to the level of the high frequency component thus detected. Further, a low frequency level detecting unit detects a level of a low frequency component adjusted with a second adjusting unit. A second control unit controls a second gain according to the level of the high frequency component and the level of the low frequency component thus adjusted, so that a difference between the level of the high frequency component adjusted with the first adjusting unit and the level of the low frequency component adjusted with the second adjusting unit becomes smaller than a specific level determined in advance.

Abstract: Disclosed are apparatus and methodology subject matters for providing improved functionality of a meter in a 2-way communications arrangement, such as an Advanced Metering System (AMS) or Infrastructure (AMI). More particularly, the present technology relates to methodologies and apparatus for providing load sensing for utility meters which preferably are operable with remote disconnect features in an Advanced Metering Infrastructure (AMI) open operational framework. Meters per the present subject matter utilize a detection circuit, and separately utilize certain remote disconnect functionality. In particular, disconnect functionality is coupled with consideration of electric load information, such as load current as determined by the metering functionality.

Abstract: The domain crossing circuit of a semiconductor memory apparatus for improving a timing margin includes a sampler that provides a sampling internal signal generated by delaying an internal input signal by a predetermined time in response to a clock and an edge information signal that defines an output timing of the sampling internal signal and an output stage that allows the sampling internal signal to be synchronized with the clock in response to the edge information signal to be output as a final output signal.

Abstract: A source synchronous signal synchronization system includes a differential signal receiver; a tunable input delay element coupled to the receiver; an input serializer/deserializer (ISerDes) coupled to the tunable input delay; an alignment unit coupled to the ISerDes; and a delay control unit coupled to the tunable input delay, the ISerDes, and the alignment unit.

Abstract: The present invention relates to a PLL circuit and an associated method that allows the PLL circuit to operate at a higher operating frequency with a wider bandwidth and a better out-band noise suppression. The PLL circuit comprises a delay locked loop (DLL), a phase-frequency detector (PFD), a loop filter, a voltage controlled oscillator (VCO) and a frequency divider.

Abstract: A clock data recovery circuit that supplies stable reference clocks to the object respectively by shortening the time of bit synchronization with each received burst data signal regardless of jittering components included in the received burst data signal, includes an interpolator that generates a reference clock having the same frequency as that of a received burst data signal and two types of determination clocks having a phase that is different from that of the reference clock respectively; and a phase adjustment control circuit that can change the phase of the reference clock in units of M/2?. After beginning receiving of a burst data signal, the clock data recovery circuit sets a large phase change value at the first phase adjustment timing and reduces the change value in the second and subsequent phase adjustment timings, thereby realizing quick bit synchronization with the received burst data signal to generate a reference clock.

Abstract: A plurality of delay paths are connected in parallel between two synchronous operation circuits operating in synchronism with a clock signal CLK, and enable transmission of a signal. A delay detection unit detects the respective delay times of the plurality of delay paths, and a control unit selects one delay path from among the plurality of delay paths based on the detection results from the delay detection unit, and controls the blocking of signal transmission in the delay paths other than the selected one delay path.