Abstract: An apparatus and corresponding method for outputting a protocol pulse based on a speed signal representing speed of an object. The apparatus includes a zero-crossing circuit, and a delay circuit. The zero-crossing circuit is configured to output the protocol pulse at a zero-crossing of the speed signal. The delay circuit is coupled to the output of the zero-crossing circuit and configured to delay the protocol pulse. A first edge of the protocol pulse is asynchronous with a clock, and a second edge of the protocol pulse is synchronous with the clock.

Abstract: A voltage converter includes a power stage coupled to a power source, a passive circuit coupling the power stage to an output capacitor, a synchronous rectification (SR) switch operable to couple the passive circuit to ground when the SR switch is conducting, a linear controller and an adaptive voltage positioning (AVP) circuit. The linear controller is operable to control switching of the SR switch and switch devices included in the power stage, to regulate an output voltage of the voltage converter based on a reference voltage. The AVP circuit operable to generate an offset voltage applied to the reference voltage based on a first signal representing output current of the voltage converter, and to subtract a second signal from the first signal. The second signal approximates a surge current applied to the output capacitor via the passive circuit for charging the output capacitor during transitions in the reference voltage.

Abstract: An electronic device includes a power switch having a control terminal coupled to a first node, a first conduction terminal coupled to a second node, and a second conduction terminal coupled to a third node. A monitoring circuit has a first input coupled to the first node and a second input coupled to the second node, the monitoring circuit to generate a monitor signal indicating gate oxide stress on the power switch as a function of first and second voltages received at the first and second inputs thereof. A protection circuit actuates to protect the power switch from the gate oxide stress when the monitor signal indicates the gate oxide stress on the power switch. The monitoring signal is generated based upon a comparison of currents generated based upon the voltages at the first and second node, as well as a current generated based upon a programmable reference voltage.

Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

Abstract: A method of controlling and maintaining a constant slew rate at an output of a buffer is provided. The method includes the following steps: (a) receiving, (i) a first input signal and (ii) at least one of a control voltage using the buffer; (b) generating a threshold voltage using a first reference voltage generator; (c) comparing (i) the threshold voltage with an output of the buffer using at least one of a comparator; (d) determining a phase difference using a phase detector; (e) producing a DC voltage using a loop filter; (f) generating a reference voltage; (g) receiving the DC voltage and the reference voltage using an amplifier; (h) amplifying the difference between (a) said DC voltage, and (b) the reference voltage to obtain a control voltage using the amplifier; and (i) feeding the control voltage to the buffer.

Abstract: A charging circuit for charging a battery of an electronic device includes a first switch having one side connected to an interface into which external power is input, a second switch having one side connected to the other side of the first switch, a third switch having one side connected to the other side of the second switch, a fourth switch having one side connected to the other side of the third switch, a flying capacitor located between the other side of the first switch and the other side of the third switch, an inductor having one side connected to the other side of the second switch, and a control circuit for controlling a charging function of the battery by controlling on/off of the first switch, the second switch, the third switch and the fourth switch.

Abstract: The present disclosure relates to a method and system for calibrating transceivers by providing a stored index that was calculated of a race condition count. The race condition is based at least in part to a rat race between a clock signal and an input signal that has been sampled by a random or jitter signal. The stored index corresponds to a relative timing error between the clock signal and the sampled input signal. The stored index is used to scramble subsequent input signals that are thermo-coded signals, thereby eliminating timing errors.

Abstract: A duty correction circuit may be provided. The duty correction circuit may include a control circuit configured to generate a duty correction control signal by detecting edges of first and second differential clock signals. The duty a duty correction clock signal generation circuit may be configured to generate a duty correction clock signal according to edges of the duty correction control signal.

Abstract: A method of detecting clock duty cycle and adjusting clock duty cycle to achieve a clock with low jitters, low noise, high common mode rejection and high power supply rejection for sampling circuit. Adjusting the duty cycle of the sampling clock can enhance data converter's performance.

Abstract: The apparatus may include a first latch configured to store a first state or a second state. The first latch may have a first latch input, one of a set input or a reset input, a first pulse clock input, and a first latch output. The first latch input may be coupled to a fixed logic value. The one of the set input or the reset input may be coupled to a clock signal or an inverted clock signal, respectively. The apparatus may include an AND gate having a first AND gate input, a second AND gate input, and a first AND gate output. The clock signal may be coupled to the first AND gate input. The first latch output may be coupled to the second AND gate input. The AND gate output may be configured to output a pulsed clock. The pulsed clock may be coupled to the first pulse clock input.

Abstract: A duty correction device may be provided. The duty correction device may include a duty controller configured to output a control signal by controlling a duty of a duty corrected signal, and detect a level of a feedback signal to convert the duty based on a code signal which is applied at a section where the level of the feedback signal corresponds to a logic level. The duty correction device may include a power gating circuit configured to generate the feedback signal by driving the control signal.

Abstract: A pulse detection circuit according to an embodiment includes a conversion circuit, a delay circuit, first and second comparators, a latch, and a generation circuit. The conversion circuit converts an input signal into a thermometer code signal. The delay circuit outputs a delay signal being the thermometer code signal delayed by a predetermined delay time. The first comparator (The second comparator) compares the thermometer code signal with the delay signal and outputs an increase signal (a decrease signal) indicating whether the input signal is larger (smaller) than the input signal before the delay time. Based on the increase signal and the decrease signal, the latch outputs an increase-decrease signal indicating whether the input signal is increasing or decreasing. Based on the thermometer code signal and the increase-decrease signal, the generation circuit generates a pulse detection signal and a pileup detection signal.

Abstract: Described herein are apparatus, method, and system for re-synthesizing a clock signal. The apparatus comprises: a first logic unit to detect a rising edge of an input clock signal and for generating a rising edge of an output clock signal based on the detected rising edge of the input clock signal, the input clock signal having a non-50% duty cycle and a first period; and a second logic unit to compute a falling edge of the output clock signal according to the detected rising edge of the input clock signal, the falling edge of the output clock signal being near half of the first period.

Abstract: Battery management circuitry for an implantable medical device such as an implantable neurostimulator is described. The circuitry has a T-shape with respect to the battery terminal, with charging circuitry coupled between rectifier circuitry and the battery terminal on one side of the T, and load isolation circuitry coupled between the load and the battery terminal on the other side. The load isolation circuitry can comprise two switches wired in parallel. An undervoltage fault condition opens both switches to isolate the battery terminal from the load to prevent further dissipation of the battery. Other fault conditions will open only one the switches leaving the other closed to allow for reduced power to the load to continue implant operations albeit at safer low-power levels. The battery management circuitry can be fixed in a particular location on an integrated circuit which also includes for example the stimulation circuitry for the electrodes.

Abstract: An internal voltage generation circuit may be provided. The internal voltage generation circuit may include a pulse generation circuit configured to generate a first pulse and a second pulse in response to an external voltage. The internal voltage generation circuit may include a pulse synthesis circuit configured for synthesizing the first pulse and the second pulse to generate a synthesis pulse.

Abstract: A duty cycle calibration circuit includes a first signal-generating circuit, receiving a clock signal to generate a first signal and a second signal, wherein the second signal and the first signal are the inverse of each other and synchronous. The calibration circuit also includes a first transmission gate, supplying a supply voltage to an adjustment signal according to the first signal and the second signal, and a fourth transmission gate, coupling the inverse of the adjustment signal to a ground according to the first signal and the second signal.

Abstract: A field emission device is configured as a heat engine, wherein the configuration of the heat engine is variable.

Abstract: An intelligent equalization technique is provided for a three-transmitter system in which mid-level transitions are selectively emphasized and de-emphasized to conserve power and reduce data jitter.

Abstract: Examples may include techniques for dual-range clock duty cycle tuning of a clock signal used for an input/output data bus. A clock duty cycle of the clock signal is monitored to determine whether the clock duty cycle falls within a threshold of a 50 percent duty cycle. A dual-range tuning is then implemented until the clock duty cycle of the clock signal falls within the threshold.

Abstract: Circuits and methods control output voltage overshoot and undershoot of an SMPC in response to a load current transient. The SMPC control stage has at least one load variation detector that compares a feedback signal with at least one transient threshold level to determine that occurrence of the load current transient. When the load current transient has occurred, the at least one load variation detector causes a switch stage to be turned on to source or sink current to or from the load circuit to compensate the load current transient. A slope detector determines a change in polarity of the slope of the load current transient. When the slope changes polarity, the slope detector sends a signal for preventing an overshoot or an undershoot of the output voltage of the SMPC once the load current transient has been compensated.

Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.

Abstract: In one embodiment, an integrated circuit is disclosed. The integrated includes a general purpose processor, an interface circuit, and a calibration adapter circuit. The general purpose processor circuit generates calibration test inputs based on user instruction. The analog interface circuit may include a calibration bus circuit. The calibration bus circuit may receive the calibration test input from the general purpose processor circuit. The calibration adapter circuit is coupled to the calibration bus circuit and the general purpose processor circuit and transmits the calibration test inputs to the calibration bus circuit.

Abstract: Systems and methods for increasing Pulse Width Modulation (PWM) resolution for digitally controlled motor control applications are described. For example, in some embodiments, a method may include receiving a clock signal having a given period; identifying a target duty cycle; calculating a comparison point based upon the given period and the target duty cycle; generating a PWM signal based upon the clock signal using the comparison point; and varying the comparison point to increase a resolution of an effective duty cycle of the PWM signal.

Abstract: A memory controller according to an example embodiment of the present disclosure may include a duty ratio adjusting circuit which generates adjusted clock signals in response to a clock signal for strobing data, and a selection circuit which outputs one of the clock signal and the adjusted clock signals to a memory device as an output clock signal. Each of the adjusted clock signals may have a different duty ratio.

Abstract: A method is described for controlling switching edges for switched output stages, in which a voltage at a switching node of the output stage is detected; a reference time is started when the voltage reaches a predefined reference value; the steepness of the switching edge is reduced if the voltage has reached a second predefined reference value at an end of the reference time; and the steepness of the switching edge is increased if the voltage has not reached the second predefined reference value at the end of the reference time. Furthermore, a control device for adjusting switching edges for switched output stages is provided.

Abstract: A circuit, integrated circuit, system tor implementation in an integrated circuit, and method of operating such a circuit, integrated circuit, or system are disclosed herein. In one example embodiment, the such a circuit includes a multiplier circuit portion, a first duty cycle correction (DCC) circuit portion, and a clock gating circuit portion. The multiplier circuit portion, DCC circuit portion, and clock gating circuit portion are all coupled in series with one another between an input port and an output port of the circuit. Additionally, the circuit is capable of receiving at the input port a first clock signal having a first frequency and, based at least indirectly upon the first clock signal, outputting a second clock signal having a second frequency that is related by a factor to the first frequency.

Abstract: Apparatuses and methods for adjusting timing of signals are described herein. An example apparatus may include a first signal adjustment cell configured to receive a first clock signal and to adjust skew of rising or falling edges of the first clock signal based on a first control signal. The timing adjustment circuit may further include a second signal adjustment cell configured to adjust skew of rising or falling edges of a second clock signal based on a second control signal. The timing adjustment circuit may further include a differential adjustment cell configured to receive the first and second clock signals and to adjust skew of rising or falling edges of the first clock signal based on the first control signal and to adjust skew of rising or falling edges of the second clock signal based on the second control signal. The first and second clock signals may be complementary.

Abstract: A clock generator includes a duty cycle correction circuit. The duty cycle correction circuit includes a duty cycle detector. The duty cycle detector, includes a first programmable delay element and a controller. The first programmable delay element is configured to delay a clock signal. The controller is configured to vary an amount of delay applied to the clock signal by the first programmable delay element, and to apply a delayed version of the clock signal, provided by the first programmable delay element, to locate an edge of a different version of the clock signal and measure time during which the different version of the clock is high. The controller is also configured to generate a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock signal based on measured time during which the different version of the clock is high.

Abstract: Methods and digital circuits providing frequency correction to frequency synthesizers are disclosed. An FLL digital circuit is provided that is configured to handle a reference frequency that is dynamic and ranges over a multi-decade range of frequencies. The FLL circuit includes a digital frequency iteration engine that allows for detection of disappearance of a reference frequency. When the digital frequency iteration engine detects that the reference frequency signal is not available, the oscillator generated frequency is not corrected, and the last value of the oscillator generated frequency is held until the reference frequency signal becomes available again.

Abstract: Noise introduced in an output signal of a pulse-width modulator (PWM) may be reduced by changing the time duration that a switch is driving the output node. Because the power supplies coupled to the switches are the source of noise in the output signal of the PWM, the time duration that the power supplies are driving the output may be reduced to obtain a subsequent reduction in noise in the output signal. For example, when a small signal is desired to be output by the PWM, the switches may be operated for shorter time durations. Thus, the switches couple the noise sources to ground for a duration of a cycle to reduce contribution of noise to the output. But, when a larger signal is desired to be output by the PWM, the switches may be operated for longer time durations or the conventional time durations described above.

Abstract: A gate pulse modulation waveform-shaping circuit includes an input terminal, an output pair, and a gate pulse modulation waveform-shaping control circuit. The input terminal receives a control signal. The output pair is connected to a scan line for outputting a gate output voltage. The gate pulse modulation waveform-shaping control circuit is connected to the output pair for adjusting a voltage waveform on the scan line. The gate pulse modulation waveform-shaping control circuit is based on the control signal to use a time interval or fixed discharge voltage to generate a desired delay for adjusting a discharge slope thereby generating different discharge time on the scan line, so that the gate output voltage has a voltage waveform including at least two waveform segments each with a non-zero sliding slope and at least two waveform segments each with a zero slope.

Abstract: An output circuit sends out, to an input circuit, a control pilot signal generated by a voltage source. A voltage transformer is provided to a control pilot line on the output side of the output circuit, and a communication unit transmits and receives communication signals via the voltage transformer. A voltage transformer is provided to the control pilot line on the input side of the input circuit, and a communication unit transmits and receives the communication signals via the voltage transformer. A low-pass filter is provided to the control pilot line between the input circuit and the voltage transformer.

Abstract: A pulse generator includes a latch module for storing first/second states, a pulse clock module for generating a clock pulse, and a delay module for delaying the clock pulse at a second latch-module input. The latch module has a first latch-module input coupled to a clock, the second latch-module input, and a latch-module output. The pulse clock module has a first pulse-clock-module input coupled to the clock, a second pulse-clock-module input coupled to the latch-module output, and a pulse-clock-module output. The delay module is coupled between the latch-module output and second pulse-clock-module input or between the pulse-clock-module output and second latch-module input. The delay module provides functionally I1IA at a delay module output, where I1 is a function of I and IA is a function of IN0 and B0, and where I is a delay module input, B0 is a first input bit, and IN0 is a first net input.

Abstract: Provided herein are apparatus and methods for single phase spot circuits. In certain implementations, a single phase spot circuit propagates a spot from input to output in response to a clock edge of a single phase clock signal. The single phase spot circuit holds the spot for about one clock cycle, thereby providing higher maximum operating frequency relative to multiphase spot circuits that hold a spot for about half of a clock cycle. Two or more single phase spot circuits can be electrically connected in a ring to operate as a spot divider. The single phase spot circuits can be used to advance a spot, represented using either a one or a zero, from one spot circuit to the next in response to a clock edge. In certain implementations, as the spot advances, a single phase spot circuit clears the spot from its input via a feedback element.

Abstract: An array of photon sensitive devices is configured to provide outputs. Pulse shaping circuits operate to shape a respective output of the array in a normal mode of operation and shape a calibration signal in a calibration mode of operation.

Abstract: Apparatuses and methods for duty cycle adjustment are disclosed herein. An example apparatus may include a node, a phase mixer, and a duty cycle adjuster circuit. The phase mixer may have a first step duty cycle response and may be configured to provide a first output signal to the node in accordance with the first step duty cycle response. The duty cycle adjuster circuit may have a second step duty cycle response complementary to the first step duty cycle response and may be configured to provide a second signal to the node in accordance with the second step duty cycle response.

Abstract: In a capacitive load drive circuit, first capacitive loads of a first capacitive load group are supplied a first driving signal and second capacitive loads of a second capacitive load group are supplied a second driving signal. A first driving signal generator generates the first driving signal from a control signal according to characteristics of the first capacitive load group, and a second driving signal generator generates the second driving signal from a control signal according to characteristics of the second capacitive load group. A control signal supply portion supplies a common control signal to the first driving signal generator and the second driving signal generator.

Abstract: A power supply system has a current source configured to provide an output current, a load supplied by the current source, and a current ripple suppression circuit. The current ripple suppression circuit has a first end and a second end, wherein the first end of the current ripple suppression circuit is coupled to the load, and the second end of the current ripple suppression circuit is coupled to a reference ground; wherein the current ripple suppression circuit is configured to suppress the current ripple in the output current and adaptively adjust the output current of the current source at a predetermined current level.

Abstract: A clock dithering circuit that provides cancellation of digital noise spurs is disclosed. The clock dithering circuit includes a control unit that receives an input clock. An ICG (integrated clock gating) cell receives the input clock and receives an enable signal from the control unit. The ICG cell generates a gated clock. A coarse dither unit receives the gated clock and receives a coarse select signal from the control unit. The coarse dither unit generates a coarse dither clock. A fine dither unit receives the coarse dither clock and receives a fine select signal from the control unit. The fine dither unit generates a fine dither clock.

Abstract: A PWM signal generation circuit according to the present invention includes a duty setting unit (10) configured to generate a duty control signal designating a duty ratio corresponding to each period of a PWM signal on the basis of an initial duty setting signal, a target duty setting signal, a slope setting signal, and a clock signal, a period setting unit (20) configured to output a period setting value, and an output control unit (30) configured to generate the PWM signal having a period corresponding to the period setting value and having a duty ratio corresponding to a value of the duty control signal. The duty setting unit (10) increases the value of the initial duty ratio to the value of the target duty ratio each time the number of a clock pulse of the clock signal reaches the period setting value reaches the slope setting value.

Abstract: In one embodiment, a method of controlling an AC-DC power converter, can include: (i) receiving, by a filter capacitor, a first branch current from an input current of the AC-DC power converter; (ii) receiving, by a power converting circuit, a second branch current from the input current; (iii) receiving, by the power converting circuit, a feedback signal that represents an output signal of the power converting circuit, and a triangular wave signal that is determined by the first branch current; (iv) generating a first conduction time based on the feedback signal such that the power converting circuit produces a first converting current; and (v) generating a second conduction time based on the triangular wave signal such that the power converting circuit produces a second converting current having a same absolute value as the first branch current.

Abstract: A switching mode power supply, having: a power switch; an energy storage component coupled to the power switch; a current sense resistor configured to generate a current sense signal; a mode select resistor configured to generate a mode select resistor; a ZCD (Zero Cross Detecting) circuit configured to generate a ZCD signal; and a control circuit configured to provide a switch control signal to control the on and off of the power switch, the control circuit having a multi-function pin configured to receive the mode select signal, the current sense signal and the ZCD signal.

Abstract: A method and a device for generating PWM pulses for an inverter are provided. The three-phase inverter's characteristic of including high frequency complementary switches is used. Only three PWM peripheral units of a DSP control unit are used to output PWM high frequency signals, and a detection control unit determine for each phase two currently high frequency complementary switches according to the states of detected level signals outputted by a preset number of GPIO interfaces. The PWM high frequency signals are distributed for each phase to one of the two switches, and the PWM high frequency signals are inversed and then sent to the other one of the two switches. In addition, the states of other switches are maintained unchanged according to a preset correspondence between states of switches of a multi-level inverter and outputted level signals in different switching periods.

Abstract: A multiplex circuit includes a plurality of input transistors that correspondingly receive a plurality of input signals of different switching points; a plurality of common base transistors, each common base transistor corresponding to a respective input transistor and having an emitter that is connected in series to a collector of the respective input transistor; and an output end that is connected to a collector of each of the common base transistors, and to which a signal that is obtained by combining signals output by each of the input transistors based on the plurality of input signals.

Abstract: A controller for generating jitters in a constant current mode of a power converter includes a current pin, an auxiliary pin, a constant current control unit, and a control signal generation unit. The current pin is used for receiving a primary side voltage determined according to a resistor and a primary side current flowing through the power converter. The auxiliary pin is used for receiving a voltage corresponding to an auxiliary winding of the power converter. The constant current control unit is used for generating an adjustment signal according to the primary side voltage, a discharge time corresponding to the voltage, and a reference voltage. The reference voltage has a predetermined range jitter voltage. The control signal generation unit is used for adjusting a period of a gate control signal according to the adjustment signal.

Abstract: A gated differential logic circuit can include a header device having a first terminal coupled to a supply voltage, and a second terminal; a second header device having a third terminal coupled to the supply voltage, and a fourth terminal; a footer device having a fifth terminal coupled to ground, and a sixth terminal; and a second footer device having a seventh terminal coupled to ground, and an eighth terminal. The circuit further includes a driver circuit having a first supply terminal coupled to the second terminal and a first ground terminal coupled to the sixth terminal, and a second driver circuit having a second supply terminal coupled to the fourth terminal and a second ground terminal coupled to the eighth terminal. A capacitor can couple the first supply terminal to the second ground terminal, while a second capacitor may couple the second supply terminal to the first ground terminal.

Abstract: Embodiments of a drain modulator that uses high power switch sensing to control active pulldown are generally described herein. In some embodiments, a logic and sense module is arranged to receive a control signal for controlling an on and an off state of an input of a switch to turn a high power voltage at an output of the switch on and off. A pullup module and a pulldown module are coupled to the input of the switch. An active pulldown module coupled to the output of the switch. The logic and sense module monitors the input to the switch and activates the active pulldown module to drain the output of the switch to a zero voltage when the input of the switch transitions to the off state.

Abstract: A pulse stretching circuit having a pulse delay circuit for receiving an input pulse signal and for outputting a delay pulse signal, and a pulse adjustment circuit, connected to the pulse delay circuit, receiving the input pulse signal and the delay pulse signal and for outputting an output pulse signal having a pulse width longer than a pulse width of the input pulse signal. The pulse adjustment circuit causes a leading edge of the output pulse signal in response to a leading edge of the input pulse signal, keeps a state in which the output pulse signal is displaced with the leading edge thus caused longer than a total time of times for both pulse widths of the input pulse signal and the delay pulse signal, and causes a trailing edge of the output pulse signal in response to a trailing edge of the delay pulse signal.

Abstract: A multi-phase signal generator and a multi-phase signal generating method thereof. The multi-phase signal generator includes a signal generator, a first comparator, a second comparator and a logic operation circuit. The signal generator generates a periodic signal. The first comparator receives the periodic signal and respectively compares the periodic signal with a first reference voltage and a second reference voltage to generate a first output signal. The second comparator receives the periodic signal and compares the periodic signal with a first threshold voltage to generate a second output signal. The logic operation circuit performs logic operations on the first output signal and the second output signal so as to generate a plurality of first phase output signals.

Abstract: To provide a duty detection circuit including: a plurality of duty detectors that detect a duty ratio of internal clocks; a controller that controls the plurality of duty detectors so that the plurality of duty detectors operates in different phases from one another; and an output selecting unit that selects one of duty detection signals from the plurality of duty detectors. According to the present invention, since the duty detectors operate in the different phases from one another, the output selecting unit can output a duty detection signal with a higher frequency than a generation frequency with which each duty detector generates the duty detection signal. Accordingly, when the duty detection circuit according to the present invention is used to adjust a clock of the DLL circuit, a control period of the DLL circuit can be reduced.